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RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Test Technology Overview.

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1 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Test Technology Overview

2 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Goals l To educate the general digital systems designer on the fundamentals of test technology in a manner that will assist him/her in designing testable systems m Provide information on the goals and techniques for testing systems m Provide information on techniques to increase the testability of designs m Provide information on how to incorporate these techniques into a general digital design methodology

3 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques m Ad hoc design for testability techniques m Structured design for testability techniques q Scan design q Boundary scan

4 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline (Cont.) l Built-In Self Test m Definitions m Test generation techniques for BIST m Signature analysis m BIST case study m Autonomous Built-In Self Test l Synthesis for Test l DFT Standards m IEEE Std. 1149.1 m IEEE Std. 1149.1b m IEEE Std. 1149.5 m IEEE Std. 1029.1 m MIL-HDBK-XX47

5 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline (Cont.) l Design Flows with DFT l Summary l References

6 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

7 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Introduction The Testing Problem l This module presents techniques that are used to detect defects in digital ICs and PC board systems l The goal of testing is to apply a minimum set of input vectors to each device to determine if it contains a defect l The first step is to detect defects at the manufacturing level at the earliest point possible

8 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service The Testing Problem l Costs increase dramatically as faulty components find their way into higher levels of integration m $1.00 to fix an IC (throw it out) m $10.00 to find and replace bad IC on a PC board m $100.00 to find bad PC board in a system m $1000.00 to find bad component in fielded system

9 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service The Testing Problem (Cont.) l Apply a set of test vectors to each device off the manufacturing line and compare outputs to the known good response l The optimum test set will detect the greatest number of defects that can be present in a device with the least number of test vectors (high defect coverage) l Types of test sets: m Exhaustive - apply every possible input vector m Functional - test every function of the device m Fault Model Derived - find a test for every “modeled” fault

10 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Testing Which Type is Closest to Optimum? Consider a 74181 ALU Chip - 14 inputs l Exhaustive testing m Will detect 100% of detectable faults m Requires 2 14 = 16,384 test vectors m A 16 bit ALU with 38 inputs would take 7.64 hours to exhaustively test at 10 MHz l Functional testing m Will detect 100% of detectable faults m Total functional testing will take over 448 vectors q Each logical mode can be tested with about 8 vectors q Each arithmetic mode can be tested with about 20 vectors m There is no algorithmic way to verify that all functional modes have been tested (designer expertise required)

11 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Testing Which Type is Closest to Optimum? (Cont.) l Modeled fault testing (consider single-stuck-at faults) m Will detect 100% of detectable modeled faults m Requires only 47 vectors m Vectors can be generated and analyzed (for fault coverage) using computer programs m The number of defects actually detected by this test vector set depends on the quality of the fault model m The key is to select a fault model that can be applied to the appropriate level of circuit abstraction (logic level) and that maps to the most possible physical defects

12 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Testing Current Practice l Use fault simulation on functional test set developed during design to determine list of undetected faults l Use this list of undetected faults as input to ATPG tool l If fault coverage is unsatisfactory, redesign or use DFT techniques to make undetected faults testable OR l Use structured DFT/BIST techniques from the bottom up

13 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Testing and Rapid Prototyping l To be effective, test must be incorporated into the design process at the highest levels l To avoid having a major impact on the speed of the design process, techniques for incorporating test must be efficient Test Technology SYSTEM DEF. FUNCTION DESIGN HW & SW PART. HW DESIGN SW DESIGN HW FAB SW CODE INTEG. & TEST VIRTUAL PROTOTYPE RASSP DESIGN LIBRARIES AND DATABASE Primarily software Primarily hardware HW & SW CODESIGN

14 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

15 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Fault Attributes Fault Characteristics CauseDurationValue Nature Extent Permanent Transient Intermittent Determinate Indeterminate Local Global Hardware Software Analog Digital Specification Mistakes External Disturbances Implementation Mistakes Component Defects [Johnson89 ]

16 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Fault Modeling l Goals m Model defects in the device at the highest level of abstraction possible q Reduces the number of individual defects that have to be considered q Reduces the complexity of the device description that must be used in test generation and analysis q Allows test generation and analysis to be done as early in the design process as possible m Model as high a percentage as possible of the actual physical defects that can occur in the device

17 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Fault Models l Stuck-at faults m Single stuck-at faults m Multiple stuck-at faults l Stuck-open faults l Bridging faults l Delay faults

18 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Single Stuck-at Fault Model l Assumptions m Only one line in the circuit is faulty at a time m The fault is permanent (as opposed to transient) m The effect of the fault is as if the faulty node is tied to either Vcc (s-a-1), or Gnd (s-a-0) m The function of the gates in the circuit is unaffected by the fault A B C 0 0 0 0 1 0 1 0 0 1 1 1 Fault-Free Gate V cc A B C Fault: A s-a-1 A B C 0 0 0 0 1 1 1 0 0 1 1 1 Faulty Gate

19 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Single Stuck-at Fault Model (Cont.) l Advantages m Can be applied at the logic level or module level m Reasonable numbers of faults 2n (n=number of circuit nodes) m Algorithms for automatic test pattern generation (ATPG) and faults simulation are well developed and efficient m Research indicates that the single stuck-at fault model covers about 90% of the possible manufacturing defects in CMOS circuits q Source-drain shorts, oxide pinholes, missing features, diffusion contaminants, metallization shorts, etc. m Other useful fault models (stuck-open, bridging faults) can be mapped into (sequences of) stuck-at faults l Disadvantages m Does not cover all defects in CMOS or other devices

20 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Multiple Stuck-at Fault Model l Assumptions m Same as single stuck-at faults except: m 2 or more lines in the circuit can be faulty at the same time l Advantage m If used in conjunction with single stuck-at faults, it covers a greater percentage of physical defects l Disadvantages m Large number of faults 3 n -1 (n=number of circuit nodes) m Algorithms for ATPG and fault simulation are much more complex and not as well developed m Does not cover a significantly larger number of detects that single stuck-at faults

21 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Stuck-open Fault Model l Assumptions m A single physical line in the circuit is broken m The resulting unconnected node is not tied to either Vcc or Gnd V DD V SS A B F Line Break Break above results in a “memory-effect” in the behavior of the circuit With AB=10, there is not path from either VDD or VSS to the output - F retains the previous value for some undetermined discharge time

22 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Stuck-open Fault Model (Cont.) l Advantages m Covers physical defects not covered by single or multiple stuck-at fault models m Can be tested with sequences of stuck-at fault tests q In the previous example (Nor gate), apply AB=00 (test for F s-a-0) and force F to Vcc q Apply AB=10 (test for A s-a-0) to force F to Gnd and observe results l Disadvantages m Requires a larger number of tests (sequence for each fault) m Algorithms for ATPG and fault simulation are more complex and less well developed m Requires a lower level circuit description (transistor level), at least for development of the fault list

23 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Bridging Fault Model l Assumptions m Two nodes of a circuit are shorted together m Usually assumed to be a low resistance path (hard short) m Three classes are typically considered: q Bridging within a logic element (transistor gates, sources, or drains shorted together) q Bridging between logic nodes (i.e. inputs or outputs of logic elements) without feedback q Bridging between logic nodes with feedback m Typically not considered is bridging of non-logical nodes between logic elements (transistor shorts across logic elements)

24 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Bridging Fault Model (Cont.) l Advantages m Covers a large percentage of physical defects - some research indicates that bridging faults account for up to 30% of all defects l Disadvantages m ATPG algorithms are more complex - testing requires setting the two bridged nodes to opposite values and observing the effect m Requires a lower level circuit description for bridging faults within logic elements

25 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Delay Fault Model l Assumptions m The logic function of the circuit-under-test is error free m Some physical defect, such as process variations, etc., makes some delays in the circuit-under-test greater than some defined bounds m Two delay fault models are typically used: q Gate delay, or transitional fault model q Path delay fault model

26 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Transitional Delay Fault Model l A logical model for a defect that delays either a rising or falling transition on a specific line in the circuit m Slow-to-rise m Slow-to-fall l Advantage m If a delay fault is large enough, it behaves as a temporary stuck-at fault, and single stuck-at fault testing techniques can be applied l Disadvantages m Two patterns are required for detection initialization and transition detection (propagation) m The minimum delay fault size that can be detected is difficult to determine

27 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Transitional Fault Model Example of Minimum Delay Fault Detectable B A C D E 0 0 1 1 Delay = 2 Delay = 6 Delay = 2 01 Slow-to- Rise Fault 681012 Z [Waicukauski87]

28 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Path Delay Fault Model l A fault model in which the total delays in a path from inputs to outputs in a circuit exceeds some maximum value l Advantages m Detects more delay faults - i.e., in transitional fault model, the delay of a faulty gate may be compensated for by other faster gates in the path m Can be used with more aggressive statistical design philosophy l Disadvantages m Large number of possible paths in circuit - exponential with number of gates m Algorithms for test generation are more complex and less well developed

29 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

30 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Test Generation Definitions Test Vector An input vector for the circuit-under-test that causes the presence of a fault to be observable at a primary output Automatic Test Pattern Generation The process of generating a test pattern for a specific fault using some type of algorithm Detected Fault A fault for which a valid test vector has been generated Undetected Fault A fault for which a test vector has not been generated Redundant Fault A fault for which no test pattern exists (because of redundant logic in the circuit)

31 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Test Generation Definitions (Cont.) Fault Coverage The percentage of total faults for which test patterns have been generated: Fault Efficiency The percentage of faults that either are detected or PROVEN redundant (usually used to measure the effectiveness of a test generator): Fault Efficiency = 100 X Number of Detected Faults + Number of Redundant Faults Total Number of Faults in the CUT Fault Coverage = 100 X Number of Detected Faults Total Number of Faults in the CUT

32 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Test Generation Definitions (Cont.) Controllability A testability metric that measures the difficulty in driving a node to a specific value Observability A testability metric that measures the difficulty in propagating the value on node to a primary output Testability Measure A metric that attempts to determine how difficult it will be to generate a test for a specific line in the circuit. This metric: -Provides feedback to the designer on testability without actually performing test generation -Assists in the test generation process -Is based on controllability and observability

33 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Test Generation Definitions (Cont.) Sensitization The process of driving the circuit to a state where the fault causes an actual erroneous value in the device at the point of the fault. E.g., for single stuck-at faults, driving the node to the value opposite the stuck-at value Propagation The process of driving the circuit to a state where the error becomes observable at the primary outputs Justification The process of determining the input combination necessary to drive an internal circuit node to a specified value (consistency)

34 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Test Generation Process Circuit Under Test A s-a-0 A s-a-1 B s-a-0 B s-a-1 C s-a-0 C s-a-1 D s-a-0 D s-a-1 E s-a-0 E s-a-1 F s-a-0 F s-a-1... A s-a-0 Generate list of undetected faults (collapse) Select a fault for test generation A B C D E 1 0 1 X X Generate a test vector for that fault (ATPG) A s-a-0 F s-a-1 H s-a-0 N s-a-0 M s-a-1... Generate a list of other faults detected by that test vector (Fault Simulation) 4A s-a-0 A s-a-1 B s-a-0 B s-a-1 C s-a-0 C s-a-1 D s-a-0 D s-a-1 E s-a-0 E s-a-1 F s-a-0 4F s-a-1... Mark those detected faults off of the fault list Exit when all faults are detected or proven untestable LOOP: Select an undetected fault for test generation

35 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Test Generation/Testing Disconnect l Test vectors developed by the “design team” often must be significantly modified by the “test team” m Vectors are incompatible with the Automatic Test Equipment (ATE) q Test vectors overflow scan-data, format-data, or timing-data memory q Test vector set is not compact enough to fit in pattern memory q Test vectors don’t address bi-directional conflicts q Test vectors included comparisons with tristate values

36 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Test Generation/Testing Disconnect (Cont.) l Solution - virtual testing 100101 001010 100101 101010 101001 010100 010110 111101 101010 000100 100101 001010 100101 101010 101001 010100 010110 111101 101010 000100 Virtual Prototype ATPG Vectors & Timing Data HDL Model of ATE system Virtual Tester

37 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

38 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Automatic Test Pattern Generation (ATPG) Algorithms l The objective is to automatically generate a test for faults in the circuit-under-test l Major classes of methods: m Pseudorandom m Ad-Hoc m Algorithmic q D-algorithm q PODEM q FAN and related algorithms q Others...

39 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Pseudorandom Test Generation l Simply generate an input vector using a pseudorandom number generator and perform fault simulation to determine if it detects the target fault l The characteristics of the fault greatly influence how well pseudorandom test generation will work m Easy-to-detect faults m Hard-to-detect faults l Typically used in the beginning of the test generation process to remove easy-to-detect faults from the fault list

40 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Pseudorandom Test Generation (Cont.) Fault Coverage vs. Number of Pseudorandom Test Vectors Fault Coverage Number of Test Vectors Cutoff Point 100% Deterministic ATPG

41 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Ad-Hoc l Uses functional test vectors developed by designers for functional verification and design debugging by: m Fault simulating to determine fault coverage m Determining locations of undetected faults m Adding additional functional tests to exercise areas of design with undetected faults m Re-fault simulating and repeating until desired fault coverage is achieved l No special test generation system is required, only fault simulator l Utilizes existing vectors and designer expertise l Achieving high fault coverage may be difficult and time consuming - especially for synthesized designs

42 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service D Algorithm l First algorithm proved “complete” - developed by Roth at IBM in 1966 m Complete - can be proven that the algorithm will generate a test for a fault if it exists l Introduced D notation m D - “1” in the good circuit “0” in the faulty m D’ - “0” in the good circuit “1” in the faulty (Dbar) l PDCF - Primitive D cube of failure - a set of inputs to a module that will sensitize a specific fault within the module l PDC - Propagation D cube - a set of inputs to a module that will propagate a D from the inputs to the outputs

43 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service D Algorithm (Cont.) Fault PDCF A B C A s-a-0 1 1 D B s-a-0 1 1 D C s-a-0 1 1 D A s-a-1 0 1 D’ B s-a-1 1 0 D’ C s-a-1 X 0 D’ 0 X D’ AND Gate PDCFs A B C A B C 1 D D D 1 D 1 D’ D’ D’ 1 D’ D D D D’ D’ D’ AND Gate PDCs Good Faulty Circuit Circuit D Value Value Value 1 0 D 0 1 D’ D Notation

44 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service D Algorithm (Cont.) Example B A C D E F G H J K L I s-a-1 A B C D E F G H I J K L D’ 1 X D’ 1 1 1 X D’ 1 1 0 1 0 D’ 0 1 1 0 0 1 0 0 D’ 0 D’ 1 1 0 X 0 0 1 0 0 D’ 0 D’ TC0 TC1 TC2 TC3 TC4 TC5 Initial test cube Pick PDCF Imply from G to A and B Set objective K=0 and imply I and F Imply from I to E and H Justify H A B C D E F G H I J K L D’ X 1 D’ X 1 D’ 1 1 TC0 TC1 TC2 Initial test cube Pick PDCF Imply K and L from I ; no test [Klenke92]

45 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service PODEM l Path Oriented DEcision Making - developed in 1981 by Goel to address the problem D algorithm had with XOR gates m D algorithm is exponentially complex to the number of internal circuit nodes - XOR gates make the complexity of the D algorithm approach this limit l PODEM expresses the search space in terms of assignments to the primary inputs only l PODEM is also a branch-and-bound algorithm which is exponentially complex to the number for circuit inputs - usually a much smaller number than circuit nodes

46 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service PODEM (Cont.) Example B A C D E F G H J K L I s-a-1 A B C D E F 10 10 10 10 10 10 Inconsistent Test [Klenke92]

47 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service FAN and Related Algorithms l FAN is an improvement on PODEM designed to utilize circuit topology information to increase search efficiency l Both the D algorithm and PODEM have trouble with areas of reconvergent fanout l Reconvergent fanout can cause complex interactions between internal circuit nodes l Example: M <= 1 R = 1... The requirement for M <= 1 to propagate the D value through the AND gate causes R to be set to 1 which terminates the propagation path Q = 1 L = D

48 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Others... l Many powerful heuristics have been developed that utilize knowledge of the circuit topology to prune the search space m Use of testability measures m Learned implications m “Saving” portions of the search space that lead to a successful test m Switching search techniques when excessive backtracking results (propagation first vs. sensitization first, etc.) l These techniques have lead to the development of very fast commercial ATPG systems for combinational circuits

49 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Sequential Circuit Test Generation m Can be treated as a form of combinational logic testing m Abstract behavior of the machine in terms of its state transition graph (STG) is also used m Problem occurs when the test vector depends on present state lines or the fault effect is propagated to the next state lines Combinational Logic F/F Present State Next State Primary Inputs Primary Outputs Huffman Model PS i NS i IiIi

50 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Sequential Circuit Test Generation (Cont.) l The problem is usually cast into 4 major steps: m Step 1 - Combinational test generation - generate test for fault in combinational logic in terms of primary inputs and present state lines (I i, PS i ) m Step 2 - Derive input sequence necessary to drive machine from initial state to state PS i using STG m Step 3 - If effect of fault in step 1 was propagated to next state lines, a faulty state NS F was created - derive input sequence necessary to differentiate between NS F and NS i using STG m Construct test sequence by concatenating sequence from step 2, input vector from step 1, and sequence from step 3, and fault simulate q Because steps 2 and 3 are typically done using STG of good machine, this is necessary to determine if resulting sequence is a test for the target fault

51 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

52 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Fault Simulation Definitions Good circuit A logic model of the circuit-under-test without any faults inserted Faulty circuit A logic model of the circuit-under-test with one or more fault models inserted Fault specification Defining the set of modeled faults and performing fault collapsing Fault insertion Selecting a subset of faults to be simulated and creating the data structures to indicate the presence of the faults

53 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Fault Simulation Definitions (Cont.) Equivalent fault Two faults f i and f j are equivalent if there is no test that will distinguish between them Dominant fault A fault f i dominates a fault f j if every test that detects f i also f j detects Fault collapsing The process of reducing the fault set by removing equivalent (and dominated) faults uncollapsed fault set equivalence fault collapsing dominance fault collapsing s-a- 1 s-a- 0 A B C A B C A B C

54 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Fault Tables f 6 = C s-a-1 f 5 = B s-a-1 f 4 = A s-a-1 f 3 = C s-a-0 f 2 = B s-a-0 f 1 = A s-a-0 f 0 = no faults Good/Faulty Circuit Response T 1 = 00 1 1 1 0 1 1 1 T 2 = 01 1 1 1 0 0 1 1 T 3 = 10 1 1 1 0 1 0 1 T 4 = 11 0 1 1 0 0 0 1 A B C Fault Table T 1 1 T 2 1 1 T 3 1 1 T 4 1 1 1 f 1 f 2 f 3 f 4 f 5 f 6 To construct fault table, XOR f 1 -f 6 columns with f 0 column

55 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Fault Table Reduction To collapse faults, remove all but one equivalent columns and all dominating columns Fault Table T 1 1 T 2 1 1 T 3 1 1 T 4 1 1 1 f 1 f 2 f 3 f 4 f 5 f 6 Collapsed Fault Table T 1 T 2 1 T 3 1 T 4 1 f 4 f 5 f 6 Collapsed Fault Table T 1 T 2 1 T 3 1 T 4 1 f 4 f 5 f 6 To collapse tests, remove all but one equivalent rows and all dominated rows Reduced Fault Table T 2 1 T 3 1 T 4 1 f 4 f 5 f 6

56 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Fault Simulation Algorithms l The goal is to determine the list of faults in a circuit-under-test that are detected by a specific test vector l The general procedure is to simulate the good and faulty circuits and determine if they produce different outputs l Consists of five specific tasks: m Good circuit simulation m Fault specification (fault list generation and collapsing) m Fault insertion m Fault-effect generation and propagation m Fault detection and discarding

57 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Fault Simulation Algorithms (Cont.) l Major types: m Parallel fault simulation m Deductive fault simulation m Concurrent fault simulation m Parallel Pattern Single Fault Propagation (PPSFP)

58 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Parallel Fault Simulation l The good circuit and a fixed number of faulty circuits N are simultaneously simulated l The values of lines in the circuit are packed into the words of the host computer - if the host has a word length of W, then N=W-1 l For a group of F faults, F/N passes are required for fault simulation l Bitwise logical operations of the host computer (and, or, xor, not) are used to simulate the gates of the circuit-under-test l Fault insertion is also handled by bitwise operations of “masks”

59 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Parallel Fault Simulation (Cont.) Define masks for signal S and fault in position i of word: mask(S) i =1 if a fault exists on S for the fault in the ith position when S is simulated fvalue(S) i =1 if the fault is s-a-1, 0 if the fault is s-a-0 Then a new signal S’ with the faults injected can be defined as: S’ = S mask(S) + mask(S) fvalue(S) MASKMASK SS’ Model of fault injection [Fujiwara85]

60 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Parallel Fault Simulation (Cont.) Example (Word Width W = 5 bits) MASKMASK MASKMASK MASKMASK A = [11111]A’ = [10111] B = [00000]B’ = [00100] C = [11011]C’ = [11001] Fault Nos. 3 & 4 detectable at line C Bit Position Fault 1 Fault-Free 2 A s-a-0 3 B s-a-1 4 C s-a-0 5 C s-a-1 Line Mask Fvalue A [ 01000 ] [ 00000 ] B [ 00100 ] [ 00100 ] C [ 00011 ] [ 00001 ] [Fujiwara85]

61 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Deductive Fault Simulation l Explicitly simulates the behavior of the good circuit only l Simultaneously deduces from the “good” state, all faults that are detectable at any line l Only one pass through the circuit is needed although it takes a long time to make this pass l More memory intensive than parallel fault simulation l For each line in the circuit A, a list of faults L A that produces the complement of the good state of A is calculated

62 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Deductive Fault Simulation (Cont.) A = 0 B = 0 C = 1 D = 1 E = 0 aeae bcbc abcdabcd adfadf L E = ((L A  L B )  L C  L D )  {E/1} = {d,E/1} [Fujiwara85]

63 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Concurrent Fault Simulation l Designed to take advantage of the fact that the behavior of the good and faulty circuits is rarely different l Needs only one pass through the circuit l Builds fault list at each node in the circuit (linked list of faults available at that node given the current circuit state) l Resimulates circuit and reconstructs fault lists in an event-driven manner l Removes detected faults from fault list l May require a lot of memory early in the simulation process when many faults are undetected

64 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Concurrent Fault Simulation (Cont.) 0 0 0 0 0 0 A B D C E A/1; 10; 0 B/1; 01; 0 D/1; 00; 1 C/1; 01; 1 D/1; 10; 1 E/1; 00; 1 1 0 0 0 0 0 A B D C E * A/0; 00; 0 * B/1; 11; 1 * D/1; 10; 1 * B/1; 10; 1 C/1; 01; 1 D/1; 10; 1 E/1; 00; 1 * 1 [Fujiwara85]

65 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Parallel Pattern Single Fault Propagation l A single fault is simulated at a time l Multiple patterns are simulated in a single pass/word similar to parallel fault simulation (single fault propagation - SFP) l A fault is simulated until the faulty values either become identical to the fault-free values or the fault is detected l SFP takes advantage of the fact that most faults are either detected in a simulation pass or have their effects “die out” fairly rapidly within a small area of the circuit l PPFSP is currently one of the most efficient fault simulation methods

66 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Sequential Circuit Fault Simulation l Like test generation, fault simulation is more complex for sequential circuits vs. combinational circuits l Inputs are applied as a sequence of vectors, one at each time step (clock period) l Fault lists propagated to Next State lines at time i must be applied to Present State lines along with faulty values at time i+1

67 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Sequential Circuit Fault Simulation (Cont.) Combinational Logic F/F Present State Next State Primary Inputs Primary Outputs PS i NS i IiIi 1 1 0 1 0 0 0 1 0 Input Vector Sequence... t i-1 titi t i+1 PS i = 10 A s-a-1, PS i = 11 C s-a-0, PS i = 01 H s-a-1, PS i = 11... Present State and Fault list from t i-1 t i-1 A s-a-0 I s-a-0 D s-a-1 M s-a-1 G s-a-0... titi Next State, list of faults propagated to Next State lines PS i = 10 A s-a-1, PS i = 11 C s-a-0, PS i = 01 H s-a-1, PS i = 11... List of detected faults titi

68 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

69 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Introduction l This section assumes basic familiarity with the following subjects: m Testing goals and objectives m Single stuck-at faults m Basic Automatic Test Pattern Generation (ATPG) algorithms m Basic fault simulation algorithms l A review of these subject can be found in the previous section

70 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

71 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service I DDQ Testing l All of the test techniques discussed thus far use voltage measurement (value) techniques l Many defects in CMOS circuits can be detected by current measuring techniques l A fully static CMOS gate consumes significant current only when switching l Quiescent current for MOS devices (I DDQ ) is typically in the fA range l Most physical defects will raise that current level by several orders of magnitude or more

72 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service I DDQ Testing (Cont.) V DD V SS I DD V OUT V IN Defect V IN V OUT I DD I DDQ TIME * Defect No Defect [Soden92]

73 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service I DDQ Testing (Cont.) l Advantages m Test generation is easier - faults must be activated, but not propagated to a Primary Output m I DDQ testing can detect defects that are not modeled by the stuck-at model q Bridging faults q Gate oxide defects q Shorts between any two of the four terminals of a transistor q Partial defects - defects that do not affect the logic of the circuit, but may effect reliability q Some delay faults q Some stuck-open faults

74 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service I DDQ Testing (Cont.) l Disadvantages m Since normal I DDQ is very low, measurements must be very precise q Measurement takes a significant amount of time (1ms) q Setting I DDQ threshold for bad devices is hard m Circuit-under-test must contain all static devices (slower), i.e., no: q Dynamic circuitry q Pull-ups or pull-downs on I/O buffers q Specialized speed optimized circuitry such as RAM sense amps that draw significant static current

75 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service I DDQ Fault Modeling l Stuck-at Fault Model m Drive the faulty node to the value opposite the stuck-at value l Transistor Short Model m Specific patterns can be derived to test for all possible combinations of shorts between all four terminals l Bridging Fault Model m Only physically adjacent nodes need be tested m Drive the adjacent nodes to opposite values

76 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service I DDQ Fault Modeling (Cont.) Fault Coverage in % Vector Number bridge transistor short pseudo-stuck-at 100 50 0 020406080 Fault Coverage Profile for Three I DDQ Models [Maxwell92]

77 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service I DDQ Test Generation l Every Vector I DDQ m Utilize logic test patterns developed for voltage-sensing test m Measure I DDQ after every vector m Most useful for first silicon prototype testing l Selective I DDQ m Perform I DDQ measurement on selected subset of entire vector set m Run entire functional test at speed, but “pause” after vector selected for I DDQ measurement l Supplemental I DDQ m Add a specific set of vectors designed for I DDQ measurement to the end of the full-speed functional tests

78 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service I DDQ Measurement Techniques l Off-Chip Measurement Unit (tester power supply) l On-Chip Measurement Unit m Built-in current monitors have been proposed, but not yet widely realized m A major consideration is not degrading the at-speed performance of the device-under-test Tester PS Logic I DD VOVO V DD C DD 1 nf 5 V VOVO  t  V O Time DUT [Soden92]

79 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service I DDQ Design for Testability l Internal Tri-State Buses m Short periods of bus contention may be functionally OK, but cause problems with IDDQ testability m Design controllers for non-overlapping bus drivers l Pull-ups and Pull-downs m Pull-up (down) resistors are commonly used in I/O pads m Eliminate or use separate power supply for I/O pads l Dynamic Circuitry m Precharge - discharge type logic typically used for high speed design m Ensure all nodes are precharged on every clock cycle l Circuits with Non-Zero Static Current m Sense-Amps for memory cells, etc. m Avoid or use separate power supply

80 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l I DDQ Testing l Introduction (Part 2) l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

81 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Section Outline l Design for Testability Techniques m Ad hoc design for testability techniques m Structured design for testability techniques

82 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Design for Testability Techniques l The goal of Design for Testability techniques is to increase the ease with which a device can be tested m Increase the controllability and observability of internal points in the circuit l Categories of Techniques m Ad Hoc (Problem oriented) q Partitioning q Degating (form of partitioning) q Test points q Bus structured architectures m Structured Techniques q Scan Design q Boundary scan

83 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Ad Hoc Design for Testability Techniques l Partitioning - “Divide and Conquer” m Physically divide the system into multiple chips or boards m On board-level systems, use jumper wires to divide subunits m Has major performance penalties Module 2 Module 3 Module 1 System [Williams83]

84 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Ad Hoc Design for Testability Techniques (Cont.) l Degating - another technique for separating modules on a chip/board with lower performance penalties Data_In Data_Out Test_Data_In Degate Data_Out Degate Test_Data_In Data_In 1 0 Test_Data_In 0 Degating Logic Clock DegatingModule Partitioning Degate Test_Data 1 Test_Data_2 Degate Test_Clock OSC Module 1 Module 2 [Williams83]

85 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Ad Hoc Design for Testability Techniques (Cont.) l Test Points - insert additional lines to control and observe internal nodes Module 2Module 1 Extra pinsDegate Line [Williams83]

86 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Ad Hoc Design for Testability Techniques (Cont.) l Bus Structured Architecture - bus adds internal control and observe points ROM RAM Micropro- cessor I/O Controller Address Bus Inputs Outputs [Williams83]

87 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Structured Design for Testability Techniques l Scan Design - the general technique is to make a FSM testable by making the internal state variables controllable and observable m This is accomplished by changing the latches for the state bits to scannable latches SRLs Outputs Inputs Scan Out Scan In Clocks (C1, C2, A, B) [Williams83] Combin- ational Logic

88 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Level Sensitive Scan Design (LSSD) L1 L2 D C I A B +L1 +L2 D C I A B +L1 +L2 [Williams83]

89 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service LSSD (Cont.) L1 L2 L1 L2 L1 L2 Scan in A B +L2 Scan out Chip border I I I Board Modules (Chip, MCM) Scan in A B Scan out [Williams83]

90 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service LSSD Design Rules l Rule 1: All internal storage is implemented in hazard-free polarity-hold latches l Rule 2: The latches are controlled by two or more non-overlapping clocks such that latches that feed one another can not have the same clock l Rule 3: It must be possible to identify a set of clock primary inputs from which the clock inputs to SRLs are controlled either through simple powering trees or through logic that is gated by SRLs and/or non-clock primary inputs l Rule 4: Clock primary inputs may not feed the data inputs to latches either directly or through combinational logic, but may only feed the clock input to the latches or the primary outputs

91 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service LSSD Advantages/Disadvantages l Advantages m With LSSD, the testing problem is transformed from one of sequential circuit testing to one of combinational circuit testing m By adding controllability/observability to the state variables, LSSD also eases functional testing l Disadvantages m Additional area is required to fabricate the LSSD latches (area overhead) m Additional time is required to latch the next state into the LSSD registers (speed overhead) m Additional time is required to scan in/out test vectors and responses - at-speed testing is not supported (testing overhead) m Clock generation and distribution for LSSD is more difficult

92 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Random Access Scan Outputs Inputs SDO Y Decoder X Decoder Clear and Clocks SDI SDK Q SDO Data SDI -CK SCK X-adr Y-adr Polarity-hold-type addressable latch [Williams83] Addressable Storage Elements Combin- ational Logic

93 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Boundary-Scan (JTAG) l Consists of adding scan registers to the inputs and outputs of ICs l Allows for efficient testing at the board level m Testing of board-level interconnect m Isolation and testing of chips via chip-level BIST or the application of chip-level tests via the test bus l Requires the addition four I/O ports to the chip - Test Access Port (TAP) m TCK - test clock m TMS - test mode signal m TDI - serial test data in m TDO - serial test data out l Also requires the addition of logic to control the testing process - TAP Controller

94 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Boundary-Scan Cell 0 1 S 1DQQ 0 1 S IN SIN ShiftDRClockDRUpdateDR Mode_Control OUT SOUT MUXMUX MUXMUX QBQB QAQA [IEEE1149.1]

95 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Boundary-Scan Cell Modes Normal Mode: Mode_Control = ‘0’ m Data passes from IN to OUT Scan Mode: ShiftDR = ‘1’, ClockDR = scan clock m Serial data is shifted in from SIN and out to SOUT Capture Mode: ShiftDR = ‘0’, ClockDR = 1 clock pulse m Data on the IN line is clocked into Q A Update Mode: with Q A loaded, Mode_Control = ‘1’, UpdateDR = 1 clock pulse m Data clock into Q A is applied to OUT

96 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Boundary-Scan Chip Architecture Miscellaneous Registers Instruction Register Bypass Register TAPTAP MUXMUX BS Test Bus Circuitry APPLICATION LOGIC TDI TMS TCK TDO OPTIONAL BIST registers Scan registers S in S out I/O PadBoundary-scan cellBoundary-scan path [IEEE1149.1]

97 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service PCB with Boundary Scan BSI BSO Logic function [IEEE1149.1]

98 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Boundary-Scan Test Modes Mode_ControlSOut ClockDRSInShiftDR 0 1 0 1 MUX Mode_Control SOut ClockDRSInShiftDR 0 1 0 1 MUX External (Interconnect) Test Mode Chip 1Chip 2Interconnect [IEEE1149.1]

99 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Boundary-Scan Test Modes (Cont.) Logic function Mode_ControlSOut ClockDRSInShiftDR 0 1 0 1 MUX Mode_Control SOut ClockDRSInShiftDR 0 1 0 1 MUX Internal Test Mode [IEEE1149.1]

100 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Boundary-Scan Test Modes (Cont.) Logic function Mode_ControlSOut ClockDRSInShiftDR 0 1 0 1 MUX Mode_Control SOut ClockDRSInShiftDR 0 1 0 1 MUX Sample Mode [IEEE1149.1]

101 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Boundary-Scan Advantages/Disadvantages l Advantages m Area and speed overhead are lower than scan design m Boundary-Scan can be used to do functional testing/debugging q IC internal functional tests q IC cluster functional tests q IC/cluster emulation íControl internal buses and nets q Hardware/Software integration tests íUse internal scan to load/examine registers, single step, load microcode, etc. l Disadvantage m Boundary-scan has some area, speed, and testing overhead in the same manner as scan design

102 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

103 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Section Outline l Built-In Self Test m Definitions m Test generation techniques for BIST m Signature analysis m BIST case study m Autonomous Built-In Self-Test

104 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Built-In Self Test Definitions Built-In Self Test (BIST) The capability of a chip, board, or system to test itself The goal of Built-In Self Test is to add devices to a design that will allow it to test itself Built-In-Test Equipment (BITE) The hardware/software incorporated into a unit to provide DFT or BIST On-Line BIST BIST in which testing occurs during normal operation Concurrent On-Line BIST A form of on-line BIST in which testing occurs simultaneously with normal function Nonconcurrent On-Line BIST A form of on-line BIST where testing is carried out while the system is in an idle state

105 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Built-In Self Test Definitions (Cont.) Off-Line BIST BIST in which testing occurs when the system is not in its normal operation Functional Off-Line BIST Off-line BIST that uses tests based on the functional description of the circuit-under-test Structural Off-Line BIST Off-line BIST that uses tests based on the structure of the circuit-under-test Pseudo Random Pattern Generator (PRPG) a multi-output device that generates pseudorandom output patterns - usually implemented with a Linear Feedback Shift Register (LFSR) Multiple-Input Signature Register (MISR) a multi-input device that compresses a series of input patterns into a (pseudo) unique signature

106 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Test-Pattern Generation for BIST l Exhaustive Testing - apply all 2n input patterns to a combinational circuit with n inputs m Binary counter can be used as a TPG l Pseudorandom testing - generate patterns that appear to be random but are in fact deterministic (repeatable) m LFSR used as a TPG m Weighted Pseudorandom Test Generation - LFSR used as TPG with combinational circuit to modify the probability of a "1" or "0" so they are nonuniform m Adaptive Pseudorandom Test Generation - weighted random testing with the weights being modified using output of fault simulation - more than one weight used l Pseudoexhaustive Testing - segment device and test each portion exhaustively

107 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Pseudorandom Test Generation LFSRs 10 State S0S0 01S1S1 10S 2 =S 1 0 1 Output sequence... Repeated subsequence 11 State S0S0 11S 2 =S 1 1 1 Output sequence... Repeated subsequence Feedback Shift RegisterLinear Feedback Shift Register 1 1 01S0S0 01S 4 =S 0 1 1 00S1S1 1 10S2S2 0 11S3S3 0 1 1 0 0 Output sequence... Repeated subsequence ++...... [Abramovici90]

108 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Maximal Length LFSR 01 State S0S0 01S 7 =S 0 1 1 0 0 1 0 1 1 1 0 0 Output sequence... Repeated subsequence Linear Feedback Shift Register 1 1 +... 11S6S6 1 11S5S5 0 10S4S4 1 01S3S3 0 10S2S2 0 00S1S1 1 Generates a cyclic state sequence of length 2 n - 1 (no all zeros case) [Abramovici90]

109 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service LFSR Canonical Forms and Characteristic Polynomials... DQ DQDQ DQ C2C2 C1C1 C n-1 CnCn +++... Q1Q1 Q2Q2 Q3Q3 QnQn = 1... DQDQ DQ DQ C2C2 C1C1 C n-1 + + +... Q1Q1 Q2Q2 Q3Q3 QnQn CnCn = 1 Type 1 LFSR Type 2 LFSR P(x) = 1 + c 1 x + c 2 x 2 +... + c n x n Characteristic Polynomial [Abramovici90]

110 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Signature Analysis l Test Patterns for BIST can be generated at-speed by an LFSR with only a clock input l The outputs of the circuit-under-test must be compared to the known good response l In general, collecting each output response and off-loading it from the CUT for comparison is too inefficient to be practical l The general solution is to compress the entire output stream into a single signature value l Signature Analysis is a compression technique based on the concept of cyclic redundancy checking (CRC) m The simplest form of this technique is based on a single input LFSR

111 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Signature Analysis (Cont.) + +... SR G(x)Q(x) Initial state: I(x) = 0 Final State: R(x) G(x) P(x) = Q(x) + R(x) P(x) or G(x) = P(x)Q(x) + R(x) number of bit streams that produce a specific signature: 2m2m 2n2n = 2 m-n m - bits in input stream n - bits in signature register number of erroneous bits streams that produce the same signature as a particular fault-free response: 2 m-n - 1 total proportion of masking error streams: 2 m-n - 1 2 m - 1 P SA (M | m,n) =  2 -n for m >> n [Abramovici90]

112 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Signature Analysis Example 12345 +++ XZ P(x) = 1 + x 2 + x 4 + x 5 Input sequence: 1 1 1 1 0 1 0 1 (8 bits) G(x) = x 7 + x 6 + x 5 + x 4 + x 2 + 1 Time Input Stream Register contents Output stream 1 2 3 4 5 0 1 0 1 0 1 1 1 1 0 0 0 0 0 Initial state 1 1 0 1 0 1 1 1 1 0 0 0 0 5 1 0 1 0 1 1 1 1 6 1 0 0 0 0 1 0 1 7 1 0 0 0 0 1 0 1 8 Remainder 0 0 1 0 1 1 0 1 Remainder Quotient R(x) = x 2 + x 4 Q(x) = 1 + x 2...... Check: P(x): x 5 + x 4 + x 2 + 1 x 2 + 1 Q(x): x 7 + x 6 + x 4 + x 2 + x 5 + x 4 + x 2 + 1 = x 7 + x 6 + x 5 + 1 Thus: P(x)Q(x) + R(x) = x 7 + x 6 + x 5 + x 4 + x 2 + 1 = G(x) [Abramovici90]

113 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Multiple Input Signature Register... DQDQ DQ DQ + + + Q1Q1 Q2Q2 Q3Q3 QnQn C n-2 C1C1 C n-1 CnCn + D1D1 D2D2 D3D3 DnDn [Abramovici90]

114 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Built-In Logic Block Observer (BILBO) Mu x B1B1 B2B2 S in S out Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q5Q5 Q6Q6 Q7Q7 Q8Q8 Z1Z1 Z2Z2 Z3Z3 Z4Z4 Z5Z5 Z6Z6 Z7Z7 Z8Z8 Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q5Q5 Q6Q6 Q7Q7 Q8Q8 Z1Z1 Z2Z2 Z3Z3 Z4Z4 Z5Z5 Z6Z6 Z7Z7 Z8Z8 System Orientation Mode B 1 B 2 = 11 L1L1 L2L2 L3L3 L4L4 L5L5 L6L6 L7L7 L8L8 [Williams83]

115 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service BILBO (Cont.) Shift Register Mode B 1 B 2 = 00 L1L1 L2L2 L3L3 L4L4 L5L5 L6L6 L7L7 L8L8 S in S out Multiple Input Signature Register Mode B 1 B 2 = 10 Z1Z1 Z2Z2 Z3Z3 Z4Z4 Z5Z5 Z6Z6 Z7Z7 Z8Z8 L1L1 L2L2 L3L3 L4L4 L5L5 L6L6 L7L7 L8L8 [Williams83]

116 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service BILBO Testing BILBO Combina- tional Network 1 Combina- tional Network 2 SA RegPN Gen BILBO Combina- tional Network 1 Combina- tional Network 2 PN GenSA Reg [Williams83]

117 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service BIST Case Study - TMS32010 Data Path ALU R2 R3 R1a R1b Multiplier 88 6 16 Control Inputs [Kim88]

118 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service BILBO Scheme ALU R2 R3 R1a R1b Multiplier 88 6 16 Control Inputs PRPG BILBO PRPG MISR 2 testing sessions required [Kim88]

119 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Single Signature Testing Scheme ALU R2 R3 R1a R1b Multiplier 88 6 16 Control Inputs PRPG MISR 1 testing session required [Kim88]

120 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service MISR Scheme I ALU R3 R1a R1b Multiplier 88 6 16 Control Inputs PRPG MISR 1 testing session required 0 22 Extended R2 [Kim88]

121 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service MISR Scheme II ALU R2 R3 R1a R1b Multiplier 88 6 16 Control Inputs PRPG MISR PRPG MISR 1 testing session required [Kim88]

122 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Test Case Results No. of test patterns BILBO scheme Single signature testing MISR scheme I Average Minimum Maximum Fault coverage (%) 2,177 830 3,619 100 > 3,000 - - 64.5 1,457 634 2,531 100 MISR scheme II 1,378 721 2,121 100 [Kim88]

123 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Autonomous Built-In Self-Test (ABIST) l An approach to testing in which a module contains logic that allows it to test itself IC, PCB or SYSTEM BISTed Module n BISTed Module 1 LogicVision BIST Controller Circuit Under Test Test Data Response Turn BIST On Go/No Go Status Diagnostic Data To Other Circuits

124 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Memory BIST Overview TAP BIST Controller Collar SRAM Control ADDR: DIN DOUT DO b log2w b bist control memory control bist address memory address serial data-in data-in serial data-out BIST go done COMPSTAT LogicVision

125 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

126 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Synthesis for Test l Synthesis for test is: m Synthesizing inherently testable circuits m Incorporating BIST circuitry into a behaviorally synthesized circuit m Constraining logic synthesis to conform to structured DFT techniques like scan m Developing a complete test program for a synthesized circuit l The definition depends on the user and on the level of synthesis supported m Gate-level test synthesis m RTL test synthesis

127 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Elements of Synthesis for Test l Methodology selection - selection of the overall set of rules, structures, and design constraints to be used in including testability in the design process l Test structure insertion - the actual insertion of the selected test structures into the description of the circuit-under-test l Circuit verification - insuring that the test circuitry and the circuit-under-test operate as intended during test as well as normal operation l Program preparation - generation of the actual test programs used during manufacture - generation of test patterns, construction of scan strings, etc.

128 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Gate-Level Synthesis for Test l Most mature technology - commercially available l Five separate activities: m Methodology selection - usually a limited number of fixed DFT method available m Automatic test structure insertion q Select which flip-flops belong in which scan chain(s) q Connect successive elements in the chain(s) q Connect global signals m DFT rule checking - check for design techniques which could cause a problem with the selected methodology m Automatic test pattern generation - generate tests for the circuit-under-test given the DFT method and fault model m Test vector translation - reformatting test vectors for specific ATE equipment used

129 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Gate-Level Synthesis for Test (Cont.) A B C D CLK F DQ DQ DQ

130 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service RTL Synthesis for Test l Tools less mature from a commercial standpoint l Activities: m Methodology selection - selection of a test methodology for a specific module(s) m Automatic test structure insertion - insertion of RTL statements necessary to generate DFT circuitry m Test structure verification - tools may be available to actually fix DFT violations m Test program preparation - conversion of RTL level test vectors to gate level compatible vectors may be difficult

131 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

132 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Section Outline l DFT Standards m IEEE Std. 1149.1 m IEEE Std. 1149.1b m IEEE Std. 1149.5 m IEEE Std. 1029.1 m MIL-HDBK-XX47

133 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service DFT Standards l IEEE Std. 1149.1 - Test Access Port and Boundary-Scan Architecture m Defines the architecture of the TAP and Boundary Scan cells m IEEE 1149.1b - defines the Boundary-Scan Description Language (BSDL) l IEEE Std. P1149.2 - Extended Serial-Digital Interface Standard m Defines a scheme that supports board-level interconnect testing and internal-scan testing of components l IEEE Std. P1149.3 - Real Time Test Bus Standard m Proposed to define standards for real-time testability bus (work discontinued)

134 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service DFT Standards (Cont.) l IEEE Std. P1149.4 - Mixed-Signal Test Bus Standard m Proposed to extend the concept of boundary-scan to analog and mixed signal devices l IEEE Std. P1149.5 - Module Test and Maintenance Bus Standard m Defines specifications for a serial test and maintenance bus for systems with two or more modules plugged into a backplane l IEEE Std. 1029.1 - Waveform and Vector Exchange Specification (WAVES) m Defines standard for VHDL description of stimulus vectors and responses l MIL-HDBK-XX47 Testability Analysis Handbook m Defined the DoD view of Design for Test

135 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service IEEE Std. 1149.1 Standard Test Access Port and Boundary-Scan Architecture l Defines standard terms l Defines the boundary-scan cell architecture, TAP controller architecture, and board-under-test architecture described previously l Defines the test modes described previously l Defines alternative cell and board architectures l Defines the actual state diagram for the TAP controller l Defines timing relationships for controller states and TAP port events l Defines the functionality of the Instruction, Test Data, and Bypass registers

136 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service TAP Controller State Diagram Test-Logic- Reset Run-Test-/ Idle TMS=1 0 Select- DR-Scan Capture-DR Shift-DR Exit-DR Pause-DR Exit2-DR Update-DR Select- IR-Scan Capture-IR Shift-IR Exit-IR Pause-IR Exit2-IR Update-IR 0 0 0 0 11 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 1 1 1 1100 0 [IEEE 1149.1]

137 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Test Logic Operation: Data Scan TCK TMS Controller state TDI Data input to IR IR shift-register Data input to TDR TDR shift-register Parallel output of TDR TDO Select-DR-Scan Run-Test/Idle Capture-DR Exit1-DRExit2-DRExit1-DR Update-DR Shift-DR Pause-DR Shift-DR Select-DR-Scan Select-IR-Scan Run-Test/Idle Test-Logic-Reset Parallel output of IR = Don’t care or Undefined Output Inactive Output from selected test data register InstructionIDCODE Old DataNew Data [IEEE 1149.1]

138 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service IEEE Std. 1149.1b BSDL l BSDL is intended to provide a machine-readable means of representing some parts of the documentary information specified in 1149.1 l The goal of the language is to facilitate communication between companies, individuals, and tools that need to exchange information on the design of test logic; for example: m Suppliers can supply BSDL descriptions of components that support 1149.1 to purchasers m ATPG tools could use BSDL description of components on a board to generate test vectors m BSDL descriptions of 1149.1-compliant components could be used for synthesis

139 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service IEEE Std. 1149.1b BSDL (Cont.) l BSDL is a subset of IEEE Std 1076-1993 VHDL l A standard VHDL package STD_1149_1_1994 is defined m Attributes q TAP Ports q TAP Instructions m Types q Cell Data q ID Codes m Constants q Cell Types

140 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service IEEE Std. P1149.5 Standard Module Test and Maintenance (MTM) Bus Protocol l Defines a standardized serial, backplane Test and Maintenance bus l Intended for use in the test, diagnosis, and maintenance of electronic subsystems and modules m Module Test m Subsystem Test m Subsystem Diagnosis m Software/Hardware Development l Defines MTM-Bus architecture l Defines MTM-Bus protocol m Physical layer m Link layer m Message layer

141 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service MTM-Bus Signals... M-moduleS-module Clock Source Master Data (MMD) Slave Data (MSD) Pause Request (MPR) Control (MCTL) Clock (MCLK) [IEEEP1149.5]

142 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service MTM Protocol Layers Physical Layer Master Link Layer Master Message Layer Slave Link Layer Slave Message Layer Applications [IEEEP1149.5 ]

143 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module to MTM Test Bus Translation IEEE Std. 1149.5 MTM-Bus Bus Transceiver ANSI/IEEE Std. 1149.1 Bus Other Board-level Test Buses.................. Test-bus Interface [IEEEP1149.5]

144 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service IEEE Std. 1029.1 Waveform and Vector Exchange Specification (WAVES) l A language for specifying stimulus and response patterns for digital electronic systems l Provides for unambiguously exchanging such patterns between and among design and test environments l Can represent various levels of waveform detail m Simulator event trace data m Highly structured test vectors typical of automatic test equipment l WAVES is a subset of IEEE Standard 1076-1987 VHDL l WAVES declarations and procedures declared in separate package - instantiated with circuit- under-test in test bench

145 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service IEEE Std. 1029.1 WAVES (Cont.) l WAVES Package: m Required Declarations q Logic Value - values to be applied directly to DUT q Pin Codes - “input” values used to list waveform q Test Pins - list of pins in the waveform m Waveform Generator Procedure - reads “input values” and applies them to the DUT q Values can be build in to the generator procedure ïSimple list ïGenerator algorithm q Values can be read from an external file

146 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service MIL-HDBK-XX47 Testability Analysis Handbook l Outlines the DoD documents that relate to DFT m MIL-STD-2165A, Testability Program for Systems and Equipment m MIL-STD-499A, Engineering Management m MIL-STD-470A, Maintainability Program Requirements for Systems and Equipments m MIL-STD-1388-1A, Logistics Support Analysis m MIL-STD-785, Reliability Program for Systems and Equipments Development and Production m MIL-HDBK-59, Department of Defense Computer-Aided Acquisition and Logistics Support (CALS) Program Implementation Guide m MIL-STD-1814, Integrated Diagnostics, Roadmap, and Requirements Document

147 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service MIL-HDBK-XX47 (Cont.) l Test Design and Assessment m Incorporate embedded and external test capability for a system or equipment that will satisfy testability performance requirements m Assess the level of test effectiveness that will be achieved for a system or equipment m Ensure the effective integration and compatibility of this test capability with other diagnostic elements l Outputs m Product fault detection and fault isolation performance levels that achieve the specified test effectiveness requirements

148 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

149 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Design Flows with DFT Create Initial Design Verify Functionality Insert/Verify Boundary-Scan Circuitry Synthesize/ Optimize Design Insert Internal Scan Circuitry Synthesize/ Optimize Incrementally Generate/Verify Test Patterns Hand off to Vendor Mentor Graphics Corp. System Design Station AutoLogic BLOCKS System 1076/QuickVHDL Design Architect AutoLogic VHDL AutoLogic AutoLogic VHDL AutoLogic QuickSim II QuickVHDL =b+c; a< BSDAdvisor DFTAdvisor

150 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

151 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service Summary l A background on general testing was provided m Fault Modeling m Test Generation m Faults Simulation m I DDQ Testing l A background on Design for Test was provided m DFT Techniques m Built-in Self Test Techniques m Hierarchical DFT Techniques m Synthesis for Test l Finally, a background on how testing and DFT is used in the design process was provided m DFT Standards m Design flows with DFT

152 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service References [Aitken95] Aitken, R. C., “An Overview of Test Synthesis Tools,” IEEE Design and Test of Computers, pp. 8-15, Summer 1995. [Abadir94] Abadir, M., G. McFall, S. Spencer, K. Drake, J. Evans “A Hierarchical Design for Test (DFT) Methodology for the Rapid Prototyping of Application Specific Signal Processing (RASSP),” Preliminary Working Document, Version 0.73, August 10, 1994. [Abramovici90] Abramovici, M., M. A. Breuer, A. D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990. [Agarwal95] Agarwal, V. K., “Hierarchical and Integrated Build-In Self-Test CAD Tools,” Proceedings of the RASSP PI Meeting January 9-13, 1995. [Fujiwara85] Fujiwara, H. Logic Testing and Design for Testability, The MIT Press, 1985. [Hayes85] Hayes, John P., “Fault Modeling,” IEEE Design and Test of Computers, April, 1985, pp. 37- 44. [Hemmady94] Hemmady, S., “VLSI Test Automation: Fact or Fiction?,” ASIC $ EDA, September 1994, pp. 56-58. [IEEE1149.1] IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture [IEEEP1149.5] IEEE P1149.5 Standard Module Test and Maintenance (MTM) Bus Protocol [Johnson89] Johnson, B. W., Design and Analysis of Fault Tolerant Digital Systems, Addison-Wesley, 1989. [Kim88] Kim, K., D. S. Ha, “On Using Signature Registers as Pseudorandom Pattern Generators in Built-In Self-Testing,” IEEE Transactions on Computer-Aided Design, Vol. 7, No. 8, August 1988, pp. 919-928.

153 RASSP Reinventing Electronic Design Methodology Architecture Infrastructure ARPA Tri-Service References [Klenke92] Klenke, R. H., R. D. Williams, J. H. Aylor, “Parallel-Processing Techniques for Automatic Test Pattern Generation,” IEEE Computer, January 1992, pp. 71-84. [Lesser80] Lesser, J. D., J. J. Shedletsky, “An Experimental Delay Test Generator for LSI Logic,”, IEEE Transactions on Computers, March, 1980, pp. 235-248. [Sedmak95] Sedmak, R., J. Evans, “Tutorial on the RASSP Design-for-Test ability Methodology,” 2nd Annual RASSP Conference, 1995. [Soden92] Soden, J. M., C. F. Hawkins, R. K. Gulati, and W. Mao, “I DDQ Testing: A Review,” Journal of Electronic Testing: Theory and Applications, 1992, pp. 5-17. [MAbadir94] Abadir, M. S., “Hierarchical Design for Testability Tools for RASSP,” Supplemental presentation material for the Martin Marietta RASSP Semi-Annual Government Review, February, 23 & 24, 1994. [Maxwell92] Maxwell, P. C., R. C. Aitken, “IDDQ Testing as a Component of a Test Suite: The Need for Several Fault Coverage Metrics,” Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 3, No. 4, December 1992, pp. 19-30. [Maly87] Maly, W., “Realistic Fault Modeling for VLSI Testing,” Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, pp. 173-180. [Malaiya86] Malaiya, Y. K., A. P. Jayasumana, R. Rajsuman, “A Detailed Examination of Bridging Faults,” IEEE, 1986, pp. 78-81. [Williams83] Williams, T. W., K. P. Parker, “Design for Testability - A Survey,” Proceedings of the IEEE, Vol. 71, No. 1, January 1983, pp. 98 - 112. [Waicukauski87] Waicukauski, J. A., et. al., “Transitional Fault Simulation,” IEEE Design & Test, April, 1987, pp. 32-38.


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