Presentation is loading. Please wait.

Presentation is loading. Please wait.

Copyright  1995-1999 SCRA 1 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Technology Overview RASSP.

Similar presentations


Presentation on theme: "Copyright  1995-1999 SCRA 1 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Technology Overview RASSP."— Presentation transcript:

1 Copyright  SCRA 1 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Technology Overview RASSP Education & Facilitation Program Module 43 Version 3.00 Copyright SCRA All rights reserved. This information is copyrighted by the SCRA, through its Advanced Technology Institute (ATI), and may only be used for non-commercial educational purposes. Any other use of this information without the express written permission of the ATI is prohibited. Certain parts of this work belong to other copyright holders and are used with their permission. All information contained, may be duplicated for non-commercial educational use only provided this copyright notice and the copyright acknowledgements herein are included. No warranty of any kind is provided or implied, nor is any liability accepted regardless of use. The United States Government holds “Unlimited Rights” in all data contained herein under Contract F C Such data may be liberally reproduced and disseminated by the Government, in whole or in part, without restriction except as follows: Certain parts of this work to other copyright holders and are used with their permission; This information contained herein may be duplicated only for non-commercial educational use. Any vehicle, in which part or all of this data is incorporated into, shall carry this notice.

2 Copyright  SCRA 2 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Rapid Prototyping Design Process Test Technology SYSTEM DEF. FUNCTION DESIGN HW & SW PART. HW DESIGN SW DESIGN HW FAB SW CODE INTEG. & TEST VIRTUAL PROTOTYPE RASSP DESIGN LIBRARIES AND DATABASE Primarily software Primarily hardware HW & SW CODESIGN

3 Copyright  SCRA 3 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Goals l To educate the general digital systems designer on the fundamentals of test technology in a manner that will assist him/her in designing testable systems l Provide information on the goals and techniques for testing systems m Provide information on techniques to increase the testability of designs m Provide information on how to incorporate these techniques into a general digital design methodology

4 Copyright  SCRA 4 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques m Ad hoc design for testability techniques m Structured design for testability techniques q Scan design q Boundary scan

5 Copyright  SCRA 5 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline (Cont.) l Built-In Self Test m Definitions m Test generation techniques for BIST m Signature analysis m BIST case study m Autonomous Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards m IEEE Std m IEEE Std b m IEEE Std m IEEE Std m MIL-HDBK-XX47

6 Copyright  SCRA 6 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline (Cont.) l Design Flows with DFT l Summary l References

7 Copyright  SCRA 7 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

8 Copyright  SCRA 8 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Introduction The Testing Problem l This module presents techniques that are used to detect defects in digital ICs and PC board systems l The goal of testing is to apply a minimum set of input vectors to each device to determine if it contains a defect l The first step is to detect defects at the manufacturing level at the earliest point possible

9 Copyright  SCRA 9 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP The Testing Problem l Costs increase dramatically as faulty components find their way into higher levels of integration m $1.00 to fix an IC (throw it out) m $10.00 to find and replace bad IC on a PC board m $ to find bad PC board in a system m $ to find bad component in fielded system

10 Copyright  SCRA 1010 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP The Testing Problem (Cont.) l Apply a set of test vectors to each device off the manufacturing line and compare outputs to the known good response l The optimum test set will detect the greatest number of defects that can be present in a device with the least number of test vectors (high defect coverage) l Types of test sets: m Exhaustive - apply every possible input vector m Functional - test every function of the device m Fault Model Derived - find a test for every “modeled” fault

11 Copyright  SCRA1 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Testing Which Type is Closest to Optimum? Consider a ALU Chip - 14 inputs l Exhaustive testing m Will detect 100% of detectable faults m Requires 2 14 = 16,384 test vectors m A 16 bit ALU with 38 inputs would take 7.64 hours to exhaustively test at 10 MHz l Functional testing m Will detect 100% of detectable faults m Total functional testing will take over 448 vectors q Each logical mode can be tested with about 8 vectors q Each arithmetic mode can be tested with about 20 vectors m There is no algorithmic way to verify that all functional modes have been tested (designer expertise required)

12 Copyright  SCRA 1212 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Testing Which Type is Closest to Optimum? (Cont.) l Modeled fault testing (consider single-stuck-at faults) m Will detect 100% of detectable modeled faults m Requires only 47 vectors m Vectors can be generated and analyzed (for fault coverage) using computer programs m The number of defects actually detected by this test vector set depends on the quality of the fault model m The key is to select a fault model that can be applied to the appropriate level of circuit abstraction (logic level) and that maps to the most possible physical defects

13 Copyright  SCRA 1313 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Testing Current Practice l Use fault simulation on functional test set developed during design to determine list of undetected faults l Use this list of undetected faults as input to ATPG tool l If fault coverage is unsatisfactory, redesign or use DFT techniques to make undetected faults testable OR l Use structured DFT/BIST techniques from the bottom up

14 Copyright  SCRA 1414 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Testing and Rapid Prototyping l To be effective, test must be incorporated into the design process at the highest levels l To avoid having a major impact on the speed of the design process, techniques for incorporating test must be efficient Test Technology SYSTEM DEF. FUNCTION DESIGN HW & SW PART. HW DESIGN SW DESIGN HW FAB SW CODE INTEG. & TEST VIRTUAL PROTOTYPE RASSP DESIGN LIBRARIES AND DATABASE Primarily software Primarily hardware HW & SW CODESIGN Model Year

15 Copyright  SCRA 1515 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

16 Copyright  SCRA 1616 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Fault Attributes Cause n Specification Mistakes n Implementation Mistakes n External Component Defects n Disturbances Interval Constant Intermittent Transient Characteristics Hardware Software Value Certain Unpredictable Breadth Local Global

17 Copyright  SCRA 1717 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Fault Modeling l Goals m Model defects in the device at the highest level of abstraction possible q Reduces the number of individual defects that have to be considered q Reduces the complexity of the device description that must be used in test generation and analysis q Allows test generation and analysis to be done as early in the design process as possible m Model as high a percentage as possible of the actual physical defects that can occur in the device

18 Copyright  SCRA 1818 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Fault Models l Stuck-at faults m Single stuck-at faults m Multiple stuck-at faults l Stuck-open faults l Bridging faults l Delay faults

19 Copyright  SCRA 1919 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Single Stuck-at Fault Model l Assumptions m Only one line in the circuit is faulty at a time m The fault is permanent (as opposed to transient) m The effect of the fault is as if the faulty node is tied to either Vcc (s-a-1), or Gnd (s-a-0) m The function of the gates in the circuit is unaffected by the fault A B C Fault-Free Gate V cc A B C Fault: A s-a-1 A B C Faulty Gate

20 Copyright  SCRA 2020 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Single Stuck-at Fault Model (Cont.) l Advantages m Can be applied at the logic level or module level m Reasonable numbers of faults 2n (n=number of circuit nodes) m Algorithms for automatic test pattern generation (ATPG) and faults simulation are well developed and efficient m Research indicates that the single stuck-at fault model covers about 90% of the possible manufacturing defects in CMOS circuits q Source-drain shorts, oxide pinholes, missing features, diffusion contaminants, metallization shorts, etc. m Other useful fault models (stuck-open, bridging faults) can be mapped into (sequences of) stuck-at faults l Disadvantages m Does not cover all defects in CMOS or other devices

21 Copyright  SCRA 2121 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Multiple Stuck-at Fault Model l Assumptions m Same as single stuck-at faults except: m 2 or more lines in the circuit can be faulty at the same time l Advantage m If used in conjunction with single stuck-at faults, it covers a greater percentage of physical defects l Disadvantages m Large number of faults 3 n -1 (n=number of circuit nodes) m Algorithms for ATPG and fault simulation are much more complex and not as well developed m Does not cover a significantly larger number of detects that single stuck-at faults

22 Copyright  SCRA2 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Stuck-open Fault Model l Assumptions m A single physical line in the circuit is broken m The resulting unconnected node is not tied to either Vcc or Gnd V DD V SS A B F Line Break Break above results in a “memory-effect” in the behavior of the circuit With AB=10, there is not path from either VDD or VSS to the output - F retains the previous value for some undetermined discharge time

23 Copyright  SCRA 2323 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Stuck-open Fault Model (Cont.) l Advantages m Covers physical defects not covered by single or multiple stuck-at fault models m Can be tested with sequences of stuck-at fault tests q In the previous example (Nor gate), apply AB=00 (test for F s-a-0) and force F to Vcc q Apply AB=10 (test for A s-a-0) to force F to Gnd and observe results l Disadvantages m Requires a larger number of tests (sequence for each fault) m Algorithms for ATPG and fault simulation are more complex and less well developed m Requires a lower level circuit description (transistor level), at least for development of the fault list

24 Copyright  SCRA 2424 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Bridging Fault Model l Assumptions m Two nodes of a circuit are shorted together m Usually assumed to be a low resistance path (hard short) m Three classes are typically considered: q Bridging within a logic element (transistor gates, sources, or drains shorted together) q Bridging between logic nodes (i.e. inputs or outputs of logic elements) without feedback q Bridging between logic nodes with feedback m Typically not considered is bridging of non-logical nodes between logic elements (transistor shorts across logic elements)

25 Copyright  SCRA 2525 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Bridging Fault Model (Cont.) l Advantages m Covers a large percentage of physical defects - some research indicates that bridging faults account for up to 30% of all defects m Disadvantages m ATPG algorithms are more complex - testing requires setting the two bridged nodes to opposite values and observing the effect m Requires a lower level circuit description for bridging faults within logic elements

26 Copyright  SCRA 2626 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Delay Fault Model l Assumptions m The logic function of the circuit-under-test is error free m Some physical defect, such as process variations, etc., makes some delays in the circuit-under-test greater than some defined bounds m Two delay fault models are typically used: q Gate delay, or transitional fault model q Path delay fault model

27 Copyright  SCRA 2727 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Transitional Delay Fault Model l A logical model for a defect that delays either a rising or falling transition on a specific line in the circuit m Slow-to-rise m Slow-to-fall l Advantage m If a delay fault is large enough, it behaves as a temporary stuck-at fault, and single stuck-at fault testing techniques can be applied m Disadvantages m Two patterns are required for detection initialization and transition detection (propagation) m The minimum delay fault size that can be detected is difficult to determine

28 Copyright  SCRA 2828 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Transitional Fault Model Example of Minimum Delay Fault Detectable B A C D E Delay = 2 Delay = 6 Delay = 2 01 Slow-to- Rise Fault Z [Waicukauski87] © IEEE 1987

29 Copyright  SCRA 2929 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Path Delay Fault Model l A fault model in which the total delays in a path from inputs to outputs in a circuit exceeds some maximum value l Advantages m Detects more delay faults - i.e., in transitional fault model, the delay of a faulty gate may be compensated for by other faster gates in the path m Can be used with more aggressive statistical design philosophy l Disadvantages m Large number of possible paths in circuit - exponential with number of gates m Algorithms for test generation are more complex and less well developed

30 Copyright  SCRA 3030 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

31 Copyright  SCRA 3131 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation Definitions Test Vector An input vector for the circuit-under-test that causes the presence of a fault to be observable at a primary output Automatic Test Pattern Generation The process of generating a test pattern for a specific fault using some type of algorithm Detected Fault A fault for which a valid test vector has been generated Undetected Fault A fault for which a test vector has not been generated Redundant Fault A fault for which no test pattern exists (because of redundant logic in the circuit)

32 Copyright  SCRA 3232 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation Definitions (Cont.) Fault Coverage The percentage of total faults for which test patterns have been generated: Fault Efficiency The percentage of faults that either are detected or PROVEN redundant (usually used to measure the effectiveness of a test generator): Fault Efficiency = 100 X Number of Detected Faults + Number of Redundant Faults Total Number of Faults in the CUT Fault Coverage = 100 X Number of Detected Faults Total Number of Faults in the CUT

33 Copyright  SCRA3 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation Definitions (Cont.) Controllability A testability metric that measures the difficulty in driving a node to a specific value Observability A testability metric that measures the difficulty in propagating the value on node to a primary output Testability Measure A metric that attempts to determine how difficult it will be to generate a test for a specific line in the circuit. This metric: -Provides feedback to the designer on testability without actually performing test generation -Assists in the test generation process -Is based on controllability and observability

34 Copyright  SCRA 3434 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation Definitions (Cont.) Sensitization The process of driving the circuit to a state where the fault causes an actual erroneous value in the device at the point of the fault. E.g., for single stuck-at faults, driving the node to the value opposite the stuck-at value Propagation The process of driving the circuit to a state where the error becomes observable at the primary outputs Justification The process of determining the input combination necessary to drive an internal circuit node to a specified value (consistency)

35 Copyright  SCRA 3535 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation Process Circuit Under Test A s-a-0 A s-a-1 B s-a-0 B s-a-1 C s-a-0 C s-a-1 D s-a-0 D s-a-1 E s-a-0 E s-a-1 F s-a-0 F s-a-1... A s-a-0 Generate list of undetected faults (collapse) Select a fault for test generation A B C D E X X Generate a test vector for that fault (ATPG) A s-a-0 F s-a-1 H s-a-0 N s-a-0 M s-a-1... Generate a list of other faults detected by that test vector (Fault Simulation) 4A s-a-0 A s-a-1 B s-a-0 B s-a-1 C s-a-0 C s-a-1 D s-a-0 D s-a-1 E s-a-0 E s-a-1 F s-a-0 4F s-a-1... Mark those detected faults off of the fault list Exit when all faults are detected or proven untestable LOOP: Select an undetected fault for test generation

36 Copyright  SCRA 3636 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation/Testing Disconnect l Test vectors developed by the “design team” often must be significantly modified by the “test team” m Vectors are incompatible with the Automatic Test Equipment (ATE) q Test vectors overflow scan-data, format-data, or timing-data memory q Test vector set is not compact enough to fit in pattern memory q Test vectors don’t address bi-directional conflicts q Test vectors included comparisons with tristate values

37 Copyright  SCRA 3737 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Generation/Testing Disconnect (Cont.) l Solution - virtual testing Virtual Prototype ATPG Vectors & Timing Data HDL Model of ATE system Virtual Tester

38 Copyright  SCRA 3838 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Hierarchical Design for Test l Built-In Self Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

39 Copyright  SCRA 3939 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Automatic Test Pattern Generation (ATPG) Algorithms l The objective is to automatically generate a test for faults in the circuit-under-test l Major classes of methods: m Pseudorandom m Ad-Hoc m Algorithmic q D-algorithm q PODEM q FAN and related algorithms q Others...

40 Copyright  SCRA 4040 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Pseudorandom Test Generation l Simply generate an input vector using a pseudorandom number generator and perform fault simulation to determine if it detects the target fault l The characteristics of the fault greatly influence how well pseudorandom test generation will work m Easy-to-detect faults m Hard-to-detect faults l Typically used in the beginning of the test generation process to remove easy-to-detect faults from the fault list

41 Copyright  SCRA 4141 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Pseudorandom Test Generation (Cont.) Fault Coverage vs. Number of Pseudorandom Test Vectors Fault Coverage Number of Test Vectors Cutoff Point 100% Deterministic ATPG

42 Copyright  SCRA 4242 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Ad-Hoc l Uses functional test vectors developed by designers for functional verification and design debugging by: m Fault simulating to determine fault coverage m Determining locations of undetected faults m Adding additional functional tests to exercise areas of design with undetected faults m Re-fault simulating and repeating until desired fault coverage is achieved l No special test generation system is required, only fault simulator l Utilizes existing vectors and designer expertise l Achieving high fault coverage may be difficult and time consuming - especially for synthesized designs

43 Copyright  SCRA 4343 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP D Algorithm l First algorithm proved “complete” - developed by Roth at IBM in 1966 m Complete - can be proven that the algorithm will generate a test for a fault if it exists l Introduced D notation m D - “1” in the good circuit “0” in the faulty m D’ - “0” in the good circuit “1” in the faulty (Dbar) l PDCF - Primitive D cube of failure - a set of inputs to a module that will sensitize a specific fault within the module l PDC - Propagation D cube - a set of inputs to a module that will propagate a D from the inputs to the outputs

44 Copyright  SCRA4 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP D Algorithm (Cont.) A B C A B C 1 D D D 1 D 1 D’ D’ D’ 1 D’ D D D D’ D’ D’ AND Gate PDCs Good Faulty Circuit Circuit D Value Value Value 1 0 D 0 1 D’ Fault PDCF A B C A s-a D B s-a D C s-a D A s-a D’ B s-a D’ C s-a-1 X 0 D’ C s-a-1 0 X D’ AND Gate PDCFs D Notation

45 Copyright  SCRA 4545 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP D Algorithm (Cont.) Example B A C D E F G H J K L I s-a-1 [Klenke92] © IEEE 1992 A B C D E F G H I J K L D’ 1 X D’ X D’ D’ D’ 0 D’ X D’ 0 D’ TC0 TC1 TC2 TC3 TC4 TC5 Initial test cube Pick PDCF Imply from G to A and B Set objective K=0 and imply I and F Imply from I to E and H Justify H A B C D E F G H I J K L D’ X 1 D’ X 1 D’ 1 1 TC0 TC1 TC2 Initial test cube Pick PDCF Imply K and L from I ; no test

46 Copyright  SCRA 4646 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP PODEM l Path Oriented DEcision Making - developed in 1981 by Goel to address the problem D algorithm had with XOR gates m D algorithm is exponentially complex to the number of internal circuit nodes - XOR gates make the complexity of the D algorithm approach this limit m PODEM expresses the search space in terms of assignments to the primary inputs only l PODEM is also a branch-and-bound algorithm which is exponentially complex to the number for circuit inputs - usually a much smaller number than circuit nodes

47 Copyright  SCRA 4747 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP PODEM (Cont.) Example B A C D E F G H J K L I s-a-1 A B C D E F Inconsistent Test [Klenke92] © IEEE 1992

48 Copyright  SCRA 4848 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP FAN and Related Algorithms l FAN is an improvement on PODEM designed to utilize circuit topology information to increase search efficiency l Both the D algorithm and PODEM have trouble with areas of reconvergent fanout l Reconvergent fanout can cause complex interactions between internal circuit nodes l Example: M <= 1 R = 1... The requirement for M <= 1 to propagate the D value through the AND gate causes R to be set to 1 which terminates the propagation path Q = 1 L = D

49 Copyright  SCRA 4949 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Others... l Many powerful heuristics have been developed that utilize knowledge of the circuit topology to prune the search space m Use of testability measures m Learned implications m “Saving” portions of the search space that lead to a successful test m Switching search techniques when excessive backtracking results (propagation first vs. sensitization first, etc.) l These techniques have lead to the development of very fast commercial ATPG systems for combinational circuits

50 Copyright  SCRA 5050 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Sequential Circuit Test Generation m Can be treated as a form of combinational logic testing m Abstract behavior of the machine in terms of its state transition graph (STG) is also used m Problem occurs when the test vector depends on present state lines or the fault effect is propagated to the next state lines Combinational Logic F/F Present State Next State Primary Inputs Primary Outputs Huffman Model PS i NS i IiIi

51 Copyright  SCRA 5151 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Sequential Circuit Test Generation (Cont.) l The problem is usually cast into 4 major steps: m Step 1 - Combinational test generation - generate test for fault in combinational logic in terms of primary inputs and present state lines (I i, PS i ) m Step 2 - Derive input sequence necessary to drive machine from initial state to state PS i using STG m Step 3 - If effect of fault in step 1 was propagated to next state lines, a faulty state NS F was created - derive input sequence necessary to differentiate between NS F and NS i using STG m Construct test sequence by concatenating sequence from step 2, input vector from step 1, and sequence from step 3, and fault simulate m Because steps 2 and 3 are typically done using STG of good machine, this is necessary to determine if resulting sequence is a test for the target fault

52 Copyright  SCRA 5252 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

53 Copyright  SCRA 5353 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Fault Simulation Definitions Good circuit A logic model of the circuit-under-test without any faults inserted Faulty circuit A logic model of the circuit-under-test with one or more fault models inserted Fault specification Defining the set of modeled faults and performing fault collapsing Fault insertion Selecting a subset of faults to be simulated and creating the data structures to indicate the presence of the faults

54 Copyright  SCRA 5454 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Fault Simulation Definitions (Cont.) Equivalent fault Two faults f i and f j are equivalent if there is no test that will distinguish between them Dominant fault A fault f i dominates a fault f j if every test that detects f i also f j detects Fault collapsing The process of reducing the fault set by removing equivalent (and dominated) faults uncollapsed fault set equivalence fault collapsing dominance fault collapsing s-a- 1 s-a- 0 A B C A B C A B C

55 Copyright  SCRA5 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Fault Tables f 6 = C s-a-1 f 5 = B s-a-1 f 4 = A s-a-1 f 3 = C s-a-0 f 2 = B s-a-0 f 1 = A s-a-0 f 0 = no faults Good/Faulty Circuit Response T 1 = T 2 = T 3 = T 4 = A B C Fault Table T 1 1 T T T f 1 f 2 f 3 f 4 f 5 f 6 To construct fault table, XOR f 1 -f 6 columns with f 0 column

56 Copyright  SCRA 5656 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Fault Table Reduction To collapse faults, remove all but one equivalent columns and all dominating columns Fault Table T 1 1 T T T f 1 f 2 f 3 f 4 f 5 f 6 Collapsed Fault Table T 1 T 2 1 T 3 1 T 4 1 f 4 f 5 f 6 Collapsed Fault Table T 1 T 2 1 T 3 1 T 4 1 f 4 f 5 f 6 To collapse tests, remove all but one equivalent rows and all dominated rows Reduced Fault Table T 2 1 T 3 1 T 4 1 f 4 f 5 f 6

57 Copyright  SCRA 5757 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Fault Simulation Algorithms l The goal is to determine the list of faults in a circuit-under-test that are detected by a specific test vector l The general procedure is to simulate the good and faulty circuits and determine if they produce different outputs l Consists of five specific tasks: m Good circuit simulation m Fault specification (fault list generation and collapsing) m Fault insertion m Fault-effect generation and propagation m Fault detection and discarding

58 Copyright  SCRA 5858 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Fault Simulation Algorithms (Cont.) l Major types: m Parallel fault simulation m Deductive fault simulation m Concurrent fault simulation m Parallel Pattern Single Fault Propagation (PPSFP)

59 Copyright  SCRA 5959 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Parallel Fault Simulation l The good circuit and a fixed number of faulty circuits N are simultaneously simulated l The values of lines in the circuit are packed into the words of the host computer - if the host has a word length of W, then N=W-1 l For a group of F faults, F/N passes are required for fault simulation l Bitwise logical operations of the host computer (and, or, xor, not) are used to simulate the gates of the circuit-under-test l Fault insertion is also handled by bitwise operations of “masks”

60 Copyright  SCRA 6060 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Parallel Fault Simulation (Cont.) Define masks for signal S and fault in position i of word: mask(S) i =1 if a fault exists on S for the fault in the ith position when S is simulated fvalue(S) i =1 if the fault is s-a-1, 0 if the fault is s-a-0 Then a new signal S’ with the faults injected can be defined as: S’ = S mask(S) + mask(S) fvalue(S) MASKMASK SS’ Model of fault injection

61 Copyright  SCRA 6161 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Parallel Fault Simulation (Cont.) Example (Word Width W = 5 bits) MASKMASK MASKMASK MASKMASK A = [11111]A’ = [10111] B = [00000]B’ = [00100] C = [00100]C’ = [00101] Fault Nos. 3 & 5 detectable at line C Bit Position Fault 1 Fault-Free 2 A s-a-0 3 B s-a-1 4 C s-a-0 5 C s-a-1 Line Mask Fvalue A [ ] [ ] B [ ] [ ] C [ ] [ ]

62 Copyright  SCRA 6262 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Deductive Fault Simulation l Explicitly simulates the behavior of the good circuit only l Simultaneously deduces from the “good” state, all faults that are detectable at any line l Only one pass through the circuit is needed although it takes a long time to make this pass l More memory intensive than parallel fault simulation l For each line in the circuit A, a list of faults L A that produces the complement of the good state of A is calculated

63 Copyright  SCRA 6363 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Deductive Fault Simulation (Cont.) A = 0 B = 1 C = 1 D = 1 aeae cdcd abcabc L D = L A  (L B  L C )  {D/0} = {b,D/0}

64 Copyright  SCRA 6464 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Concurrent Fault Simulation l Designed to take advantage of the fact that the behavior of the good and faulty circuits is rarely different l Needs only one pass through the circuit l Builds fault list at each node in the circuit (linked list of faults available at that node given the current circuit state) l Resimulates circuit and reconstructs fault lists in an event-driven manner l Removes detected faults from fault list l May require a lot of memory early in the simulation process when many faults are undetected

65 Copyright  SCRA 6565 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Concurrent Fault Simulation (Cont.) A B D C E A/0; 00; 0 D/0; 10; 0 A/0; 00; 0 C/0; 10; 0 D/0; 10; 0 E/0; 11; A B D C E * A/1; 10; 1 * B/1; 01; 1 * D/1; 00; 1 * A/1; 10; 1 * B/1; 01; 1 * D/1; 00; 1 * E/1; 01; 1 * 0 1

66 Copyright  SCRA6 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Parallel Pattern Single Fault Propagation l A single fault is simulated at a time l Multiple patterns are simulated in a single pass/word similar to parallel fault simulation (single fault propagation - SFP) l A fault is simulated until the faulty values either become identical to the fault-free values or the fault is detected l SFP takes advantage of the fact that most faults are either detected in a simulation pass or have their effects “die out” fairly rapidly within a small area of the circuit l PPFSP is currently one of the most efficient fault simulation methods

67 Copyright  SCRA 6767 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Sequential Circuit Fault Simulation l Like test generation, fault simulation is more complex for sequential circuits vs. combinational circuits l Inputs are applied as a sequence of vectors, one at each time step (clock period) l Fault lists propagated to Next State lines at time i must be applied to Present State lines along with faulty values at time i+1

68 Copyright  SCRA 6868 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Sequential Circuit Fault Simulation (Cont.) Combinational Logic F/F Present State Next State Primary Inputs Primary Outputs PS i NS i IiIi Input Vector Sequence... t i-1 titi t i+1 PS i = 10 A s-a-1, PS i = 11 C s-a-0, PS i = 01 H s-a-1, PS i = Present State and Fault list from t i-1 t i-1 A s-a-0 I s-a-0 D s-a-1 M s-a-1 G s-a-0... titi Next State, list of faults propagated to Next State lines PS i = 10 A s-a-1, PS i = 11 C s-a-0, PS i = 01 H s-a-1, PS i = List of detected faults titi

69 Copyright  SCRA 6969 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

70 Copyright  SCRA 7070 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Introduction l This section assumes basic familiarity with the following subjects: m Testing goals and objectives m Single stuck-at faults m Basic Automatic Test Pattern Generation (ATPG) algorithms m Basic fault simulation algorithms l A review of these subject can be found in the previous section

71 Copyright  SCRA 7171 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

72 Copyright  SCRA 7272 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP I DDQ Testing l All of the test techniques discussed thus far use voltage measurement (value) techniques l Many defects in CMOS circuits can be detected by current measuring techniques l A fully static CMOS gate consumes significant current only when switching l Quiescent current for MOS devices (I DDQ ) is typically in the fA range l Most physical defects will raise that current level by several orders of magnitude or more

73 Copyright  SCRA 7373 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Copyright 1992 Kluwer Academic Publishers. Used with permission. I DDQ Testing (Cont.) V DD V SS I DD V OUT V IN Defect V IN V OUT I DD I DDQ TIME * Defect No Defect [Soden92]

74 Copyright  SCRA 7474 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP I DDQ Testing (Cont.) l Advantages m Test generation is easier - faults must be activated, but not propagated to a Primary Output m I DDQ testing can detect defects that are not modeled by the stuck-at model q Bridging faults q Gate oxide defects q Shorts between any two of the four terminals of a transistor q Partial defects - defects that do not affect the logic of the circuit, but may effect reliability q Some delay faults q Some stuck-open faults

75 Copyright  SCRA 7575 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP I DDQ Testing (Cont.) l Disadvantages m Since normal I DDQ is very low, measurements must be very precise q Measurement takes a significant amount of time (1ms) q Setting I DDQ threshold for bad devices is hard m Circuit-under-test must contain all static devices (slower), i.e., no: q Dynamic circuitry q Pull-ups or pull-downs on I/O buffers q Specialized speed optimized circuitry such as RAM sense amps that draw significant static current

76 Copyright  SCRA 7676 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP I DDQ Fault Modeling l Stuck-at Fault Model m Drive the faulty node to the value opposite the stuck-at value l Transistor Short Model m Specific patterns can be derived to test for all possible combinations of shorts between all four terminals l Bridging Fault Model m Only physically adjacent nodes need be tested m Drive the adjacent nodes to opposite values

77 Copyright  SCRA7 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP I DDQ Fault Modeling (Cont.) Fault Coverage in % Vector Number bridge transistor short pseudo-stuck-at Fault Coverage Profile for Three I DDQ Models [Maxwell92] Copyright 1992 Kluwer Academic Publishers. Used with permission.

78 Copyright  SCRA 7878 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP I DDQ Test Generation l Every Vector I DDQ m Utilize logic test patterns developed for voltage-sensing test m Measure I DDQ after every vector m Most useful for first silicon prototype testing l Selective I DDQ m Perform I DDQ measurement on selected subset of entire vector set m Run entire functional test at speed, but “pause” after vector selected for I DDQ measurement l Supplemental I DDQ m Add a specific set of vectors designed for I DDQ measurement to the end of the full-speed functional tests

79 Copyright  SCRA 7979 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP I DDQ Measurement Techniques l Off-Chip Measurement Unit (tester power supply) l On-Chip Measurement Unit m Built-in current monitors have been proposed, but not yet widely realized m A major consideration is not degrading the at-speed performance of the device-under-test Tester PS Logic I DD VOVO V DD C DD 1 nf 5 V VOVO  t  V O Time DUT [Soden92] Copyright 1992 Kluwer Academic Publishers. Used with permission.

80 Copyright  SCRA 8080 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP I DDQ Design for Testability l Internal Tri-State Buses m Short periods of bus contention may be functionally OK, but cause problems with IDDQ testability m Design controllers for non-overlapping bus drivers l Pull-ups and Pull-downs m Pull-up (down) resistors are commonly used in I/O pads m Eliminate or use separate power supply for I/O pads l Dynamic Circuitry m Precharge - discharge type logic typically used for high speed design m Ensure all nodes are precharged on every clock cycle l Circuits with Non-Zero Static Current m Sense-Amps for memory cells, etc. m Avoid or use separate power supply

81 Copyright  SCRA 8181 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l I DDQ Testing l Introduction (Part 2) l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

82 Copyright  SCRA 8282 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Section Outline l Design for Testability Techniques m Ad hoc design for testability techniques m Structured design for testability techniques

83 Copyright  SCRA 8383 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Design for Testability Techniques l The goal of Design for Testability techniques is to increase the ease with which a device can be tested m Increase the controllability and observability of internal points in the circuit l Categories of Techniques m Ad Hoc (Problem oriented) q Partitioning q Degating (form of partitioning) q Test points q Bus structured architectures m Structured Techniques q Scan Design q Boundary scan

84 Copyright  SCRA 8484 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Ad Hoc Design for Testability Techniques l Partitioning - “Divide and Conquer” m Physically divide the system into multiple chips or boards m On board-level systems, use jumper wires to divide subunits m Has major performance penalties Module 2 Module 3 Module 1 System [Williams83] © IEEE 1983

85 Copyright  SCRA 8585 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Ad Hoc Design for Testability Techniques (Cont.) l Degating - another technique for separating modules on a chip/board with lower performance penalties Data_In Data_Out Test_Data_In Degate Data_Out Degate Test_Data_In Data_In 1 0 Test_Data_In 0 Degating Logic Clock Degating Module Partitioning Degate Test_Data 1 Test_Data_2 Degate Test_Clock OSC Module 1 Module 2 [Williams83] © IEEE 1983

86 Copyright  SCRA 8686 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Ad Hoc Design for Testability Techniques (Cont.) l Test Points - insert additional lines to control and observe internal nodes Module 2Module 1 Extra pinsDegate Line [Williams83] © IEEE 1983

87 Copyright  SCRA 8787 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Ad Hoc Design for Testability Techniques (Cont.) l Bus Structured Architecture - bus adds internal control and observe points ROM RAM Micropro- cessor I/O Controller Address Bus Inputs Outputs [Williams83] © IEEE 1983

88 Copyright  SCRA8 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Structured Design for Testability Techniques l Scan Design - the general technique is to make a FSM testable by making the internal state variables controllable and observable l This is accomplished by changing the latches for the state bits to scannable latches SRLs Outputs Inputs Scan Out Scan In Clocks (C1, C2, A, B) [Williams83] Combin- ational Logic © IEEE 1983

89 Copyright  SCRA 8989 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Level Sensitive Scan Design (LSSD) L1 L2 D C I A B +L1 +L2 D C I A B +L1 +L2 [Williams83] © IEEE 1983

90 Copyright  SCRA 9090 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP LSSD (Cont.) L1 L2 L1 L2 L1 L2 Scan in A B +L2 Scan out Chip border I I I Board Modules (Chip, MCM) Scan in A B Scan out [Williams83] © IEEE 1983

91 Copyright  SCRA 9191 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP LSSD Design Rules l Rule 1: All internal storage is implemented in hazard-free polarity-hold latches l Rule 2: The latches are controlled by two or more non-overlapping clocks such that latches that feed one another can not have the same clock l Rule 3: It must be possible to identify a set of clock primary inputs from which the clock inputs to SRLs are controlled either through simple powering trees or through logic that is gated by SRLs and/or non-clock primary inputs l Rule 4: Clock primary inputs may not feed the data inputs to latches either directly or through combinational logic, but may only feed the clock input to the latches or the primary outputs

92 Copyright  SCRA 9292 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP LSSD Advantages/Disadvantages l Advantages m With LSSD, the testing problem is transformed from one of sequential circuit testing to one of combinational circuit testing m By adding controllability/observability to the state variables, LSSD also eases functional testing l Disadvantages m Additional area is required to fabricate the LSSD latches (area overhead) m Additional time is required to latch the next state into the LSSD registers (speed overhead) m Additional time is required to scan in/out test vectors and responses - at-speed testing is not supported (testing overhead) m Clock generation and distribution for LSSD is more difficult

93 Copyright  SCRA 9393 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Random Access Scan Outputs Inputs SDO Y Decoder X Decoder Clear and Clocks SDI SDK Q SDO Data SDI -CK SCK X-adr Y-adr Polarity-hold-type addressable latch [Williams83] Addressable Storage Elements Combin- ational Logic © IEEE 1983

94 Copyright  SCRA 9494 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Boundary-Scan l Consists of adding scan registers to the inputs and outputs of ICs l Allows for efficient testing at the board level m Testing of board-level interconnect m Isolation and testing of chips via chip-level BIST or the application of chip-level tests via the test bus l Requires the addition four I/O ports to the chip - Test Access Port (TAP) m TCK - test clock m TMS - test mode signal m TDI - serial test data in m TDO - serial test data out l Also requires the addition of logic to control the testing process - TAP Controller

95 Copyright  SCRA 9595 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Boundary-Scan Cell 0 1 S 1DQQ 0 1 S IN SIN ShiftDRClockDRUpdateDR Mode_Control OUT SOUT MUXMUX MUXMUX QBQB QAQA [IEEE1149.1] © IEEE 1990

96 Copyright  SCRA 9696 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Boundary-Scan Cell Modes Normal Mode: Mode_Control = ‘0’ m Data passes from IN to OUT Scan Mode: ShiftDR = ‘1’, ClockDR = scan clock m Serial data is shifted in from SIN and out to SOUT Capture Mode: ShiftDR = ‘0’, ClockDR = 1 clock pulse m Data on the IN line is clocked into Q A Update Mode: with Q A loaded, Mode_Control = ‘1’, UpdateDR = 1 clock pulse m Data clock into Q A is applied to OUT

97 Copyright  SCRA 9797 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Boundary-Scan Chip Architecture Miscellaneous Registers Instruction Register Bypass Register TAPTAP MUXMUX BS Test Bus Circuitry APPLICATION LOGIC TDI TMS TCK TDO OPTIONAL BIST registers Scan registers S in S out I/O PadBoundary-scan cellBoundary-scan path [IEEE1149.1] © IEEE 1990

98 Copyright  SCRA 9898 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP PCB with Boundary Scan BSI BSO Logic function [IEEE1149.1] © IEEE 1990

99 Copyright  SCRA9 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Boundary-Scan Test Modes Mode_ControlSOut ClockDRSInShiftDR MUX Mode_Control SOut ClockDRSInShiftDR MUX External (Interconnect) Test Mode Chip 1Chip 2Interconnect [IEEE1149.1] © IEEE 1990

100 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Boundary-Scan Test Modes (Cont.) Logic function Mode_ControlSOut ClockDRSInShiftDR MUX Mode_Control SOut ClockDRSInShiftDR MUX Internal Test Mode [IEEE1149.1] © IEEE 1990

101 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Boundary-Scan Test Modes (Cont.) Logic function Mode_ControlSOut ClockDRSInShiftDR MUX Mode_Control SOut ClockDRSInShiftDR MUX Sample Mode [IEEE1149.1] © IEEE 1990

102 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Boundary-Scan Advantages/Disadvantages l Advantages m Area and speed overhead are lower than scan design m Boundary-Scan can be used to do functional testing/debugging q IC internal functional tests q IC cluster functional tests q IC/cluster emulation íControl internal buses and nets q Hardware/Software integration tests íUse internal scan to load/examine registers, single step, load microcode, etc. l Disadvantage m Boundary-scan has some area, speed, and testing overhead in the same manner as scan design

103 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

104 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Section Outline l Built-In Self Test m Definitions m Test generation techniques for BIST m Signature analysis m BIST case study m Autonomous Built-In Self-Test

105 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Built-In Self Test Definitions Built-In Self Test (BIST) The capability of a chip, board, or system to test itself The goal of Built-In Self Test is to add devices to a design that will allow it to test itself Built-In-Test Equipment (BITE) The hardware/software incorporated into a unit to provide DFT or BIST On-Line BIST BIST in which testing occurs during normal operation Concurrent On-Line BIST A form of on-line BIST in which testing occurs simultaneously with normal function Nonconcurrent On-Line BIST A form of on-line BIST where testing is carried out while the system is in an idle state

106 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Built-In Self Test Definitions (Cont.) Off-Line BIST BIST in which testing occurs when the system is not in its normal operation Functional Off-Line BIST Off-line BIST that uses tests based on the functional description of the circuit-under-test Structural Off-Line BIST Off-line BIST that uses tests based on the structure of the circuit-under-test Pseudo Random Pattern Generator (PRPG) a multi-output device that generates pseudorandom output patterns - usually implemented with a Linear Feedback Shift Register (LFSR) Multiple-Input Signature Register (MISR) a multi-input device that compresses a series of input patterns into a (pseudo) unique signature

107 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test-Pattern Generation for BIST l Exhaustive Testing - apply all 2n input patterns to a combinational circuit with n inputs m Binary counter can be used as a TPG l Pseudorandom testing - generate patterns that appear to be random but are in fact deterministic (repeatable) m LFSR used as a TPG m Weighted Pseudorandom Test Generation - LFSR used as TPG with combinational circuit to modify the probability of a "1" or "0" so they are nonuniform m Adaptive Pseudorandom Test Generation - weighted random testing with the weights being modified using output of fault simulation - more than one weight used l Pseudoexhaustive Testing - segment device and test each portion exhaustively

108 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Pseudorandom Test Generation LFSRs 10 State S0S0 01S1S1 10S 2 =S Output sequence... Repeated subsequence 11 State S0S0 11S 2 =S Output sequence... Repeated subsequence Feedback Shift RegisterLinear Feedback Shift Register S0S0 01S 4 =S S1S1 1 10S2S2 0 11S3S Output sequence... Repeated subsequence [Abramovici90] © IEEE 1990

109 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Maximal Length LFSR 01 State S0S0 01S 7 =S Output sequence... Repeated subsequence Linear Feedback Shift Register S6S6 1 11S5S5 0 10S4S4 1 01S3S3 0 10S2S2 0 00S1S1 1 Generates a cyclic state sequence of length 2 n - 1 (no all zeros case) [Abramovici90] © IEEE 1990

110 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP LFSR Canonical Forms and Characteristic Polynomials... DQ DQDQ DQ C2C2 C1C1 C n-1 CnCn Q1Q1 Q2Q2 Q3Q3 QnQn = 1... DQDQ DQ DQ C2C2 C1C1 C n Q1Q1 Q2Q2 Q3Q3 QnQn CnCn = 1 Type 1 LFSR Type 2 LFSR P(x) = 1 + c 1 x + c 2 x c n x n Characteristic Polynomial [Abramovici90] © IEEE 1990

111 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Signature Analysis l Test Patterns for BIST can be generated at-speed by an LFSR with only a clock input l The outputs of the circuit-under-test must be compared to the known good response l In general, collecting each output response and off-loading it from the CUT for comparison is too inefficient to be practical l The general solution is to compress the entire output stream into a single signature value l Signature Analysis is a compression technique based on the concept of cyclic redundancy checking (CRC) m The simplest form of this technique is based on a single input LFSR

112 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Signature Analysis (Cont.) SR G(x)Q(x) Initial state: I(x) = 0 Final State: R(x) G(x) P(x) = Q(x) + R(x) P(x) or G(x) = P(x)Q(x) + R(x) number of bit streams that produce a specific signature: 2m2m 2n2n = 2 m-n m - bits in input stream n - bits in signature register number of erroneous bits streams that produce the same signature as a particular fault-free response: 2 m-n - 1 total proportion of masking error streams: 2 m-n m - 1 P SA (M | m,n) =  2 -n for m >> n [Abramovici90] © IEEE 1990

113 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Signature Analysis Example XZ P(x) = 1 + x 2 + x 4 + x 5 Input sequence: (8 bits) G(x) = x 7 + x 6 + x 5 + x 4 + x Time Input Stream Register contents Output stream Initial state Remainder Remainder Quotient R(x) = x 2 + x 4 Q(x) = 1 + x Check: P(x): x 5 + x 4 + x x Q(x): x 7 + x 6 + x 4 + x 2 + x 5 + x 4 + x = x 7 + x 6 + x Thus: P(x)Q(x) + R(x) = x 7 + x 6 + x 5 + x 4 + x = G(x) [Abramovici90] © IEEE 1990

114 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Multiple Input Signature Register... DQDQ DQ DQ Q1Q1 Q2Q2 Q3Q3 QnQn C n-2 C1C1 C n-1 CnCn + D1D1 D2D2 D3D3 DnDn [Abramovici90] © IEEE 1990

115 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Built-In Logic Block Observer (BILBO) Mu x B1B1 B2B2 S in S out Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q5Q5 Q6Q6 Q7Q7 Q8Q8 Z1Z1 Z2Z2 Z3Z3 Z4Z4 Z5Z5 Z6Z6 Z7Z7 Z8Z8 Q1Q1 Q2Q2 Q3Q3 Q4Q4 Q5Q5 Q6Q6 Q7Q7 Q8Q8 Z1Z1 Z2Z2 Z3Z3 Z4Z4 Z5Z5 Z6Z6 Z7Z7 Z8Z8 System Orientation Mode B 1 B 2 = 11 L1L1 L2L2 L3L3 L4L4 L5L5 L6L6 L7L7 L8L8 [Williams83] © IEEE 1983

116 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP BILBO (Cont.) Shift Register Mode B 1 B 2 = 00 L1L1 L2L2 L3L3 L4L4 L5L5 L6L6 L7L7 L8L8 S in S out Multiple Input Signature Register Mode B 1 B 2 = 10 Z1Z1 Z2Z2 Z3Z3 Z4Z4 Z5Z5 Z6Z6 Z7Z7 Z8Z8 L1L1 L2L2 L3L3 L4L4 L5L5 L6L6 L7L7 L8L8 [Williams83] © IEEE 1983

117 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP BILBO Testing BILBO Combina- tional Network 1 Combina- tional Network 2 SA RegPN Gen BILBO Combina- tional Network 1 Combina- tional Network 2 PN GenSA Reg [Williams83] © IEEE 1983

118 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP BIST Case Study - TMS32010 Data Path ALU R2 R3 R1a R1b Multiplier Control Inputs [Kim88] © IEEE 1988

119 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP BILBO Scheme ALU R2 R3 R1a R1b Multiplier Control Inputs PRPG BILBO PRPG MISR 2 testing sessions required [Kim88] © IEEE 1988

120 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Single Signature Testing Scheme ALU R2 R3 R1a R1b Multiplier Control Inputs PRPG MISR 1 testing session required [Kim88] © IEEE 1988

121 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP MISR Scheme I ALU R3 R1a R1b Multiplier Control Inputs PRPG MISR 1 testing session required 0 22 Extended R2 [Kim88] © IEEE 1988

122 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP MISR Scheme II ALU R2 R3 R1a R1b Multiplier Control Inputs PRPG MISR PRPG MISR 1 testing session required [Kim88] © IEEE 1988

123 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Case Results No. of test patterns BILBO scheme Single signature testing MISR scheme I Average Minimum Maximum Fault coverage (%) 2, , > 3, , , MISR scheme II 1, , [Kim88] © IEEE 1988

124 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Autonomous Built-In Self-Test (ABIST) l An approach to testing in which a module contains logic that allows it to test itself IC, PCB or SYSTEM BISTed Module n BISTed Module 1 [Agarwal95] BIST Controller Circuit Under Test Test Data Response Turn BIST On Go/No Go Status Diagnostic Data To Other Circuits

125 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Memory BIST Overview TAP BIST Controller Collar SRAM Control ADDR: DIN DOUT DO b log2w b bist control memory control bist address memory address serial data-in data-in serial data-out BIST go done COMPSTAT [Agarwal95]

126 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Self-Testing System Architecture Field Diagnosis System Software test & maint. processor card 1149 Master and BIST Memory CPU ASIC PCB LogicMemory BIST TAP Boundary Scan ASIC [Agarwal95]

127 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Generations of Test Solutions l Completely External Testing: m Generation 1: Functional verification vectors used as manufacturing test vectors (fault simulate & supplement with additional functional vectors to raise fault coverage) m Generation 2: Scan insertion and Automatic Test Pattern Generation l Electronic Systems Test Automation (ESTA) m Generation 3: Automatic Built-In Self-Test (ABIST) using 1149.X m Generation 4: Hierarchical and integrated BIST (HIBIST) from chip to system [Agarwal95]

128 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Benefits of ESTA l Reduces time to market during design and manufacturing m Production test development time can be reduced from weeks to days m Simplifies and manages the test development process m Handles very complex designs m Compatible with HDL and synthesis-based design flow l Reduces cost over full product test lifecycle m Reduces tester capital costs m Spans the test hierarchy from IC to MCM/PCB to system m Allows test data to be manipulated for reuse at higher levels m Permits field diagnosis [Agarwal95]

129 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Benefits of ESTA (Cont.) l Enhances quality m Permits very high fault coverage tests m Supports at-speed test m Tests embedded or hard-to-reach functionality m Supports validation of test structures and data [Agarwal95]

130 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

131 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Hierarchical Design For Test l Testability must be considered at all levels of the design m ASIC/FPGA m MCM m Board m System l System-level test requirements must be propagated down to the lower level of the design to exploit design options at these levels l Additional DFT features could be added to an ASIC to assist in testing other chips connected to it l The alternative is to rigidly specify DFT rules for each level of the design m Does not support COTS use [MAbadir94]

132 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Hierarchical Design For Test (Cont.) l Testability requirements must be captured at an early stage of the design process l Standard interfaces should be used to simplify testing interconnects l A hierarchical test strategy has three main components: m Partitioning of the design into independently testable units (test kernels) m Specification of test methods for each test kernel q Full scan, functional testing, boundary scan m Setting of targets for trade-off parameters q Fault coverage, test application time, test cost [MAbadir94]

133 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Hierarchical Design For Test (Cont.) MCM SEM-E U1 U2 System Test Bus LRM Test Controller RAM ASIC DSP Proc. MCM Test Controller bus ASIC Chip Internal Circuit Partition On-chip Test Controller [MAbadir94]

134 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

135 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Synthesis for Test l Synthesis for test is: m Synthesizing inherently testable circuits m Incorporating BIST circuitry into a behaviorally synthesized circuit m Constraining logic synthesis to conform to structured DFT techniques like scan m Developing a complete test program for a synthesized circuit l The definition depends on the user and on the level of synthesis supported m Gate-level test synthesis m RTL test synthesis

136 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Elements of Synthesis for Test l Methodology selection - selection of the overall set of rules, structures, and design constraints to be used in including testability in the design process l Test structure insertion - the actual insertion of the selected test structures into the description of the circuit-under-test l Circuit verification - insuring that the test circuitry and the circuit-under-test operate as intended during test as well as normal operation l Program preparation - generation of the actual test programs used during manufacture - generation of test patterns, construction of scan strings, etc.

137 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Gate-Level Synthesis for Test l Most mature technology - commercially available l Five separate activities: m Methodology selection - usually a limited number of fixed DFT method available m Automatic test structure insertion q Select which flip-flops belong in which scan chain(s) q Connect successive elements in the chain(s) q Connect global signals m DFT rule checking - check for design techniques which could cause a problem with the selected methodology m Automatic test pattern generation - generate tests for the circuit-under-test given the DFT method and fault model m Test vector translation - reformatting test vectors for specific ATE equipment used

138 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Gate-Level Synthesis for Test (Cont.) A B C D CLK F DQ DQ DQ

139 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP RTL Synthesis for Test l Tools less mature from a commercial standpoint l Activities: m Methodology selection - selection of a test methodology for a specific module(s) m Automatic test structure insertion - insertion of RTL statements necessary to generate DFT circuitry m Test structure verification - tools may be available to actually fix DFT violations m Test program preparation - conversion of RTL level test vectors to gate level compatible vectors may be difficult

140 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

141 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Section Outline l DFT Standards m IEEE Std m IEEE Std b m IEEE Std m IEEE Std m MIL-HDBK-XX47

142 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP DFT Standards l IEEE Std Test Access Port and Boundary-Scan Architecture m Defines the architecture of the TAP and Boundary Scan cells m IEEE b - defines the Boundary-Scan Description Language (BSDL) l IEEE Std. P Extended Serial-Digital Interface Standard m Defines a scheme that supports board-level interconnect testing and internal-scan testing of components l IEEE Std. P Real Time Test Bus Standard m Proposed to define standards for real-time testability bus (work discontinued)

143 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP DFT Standards (Cont.) l IEEE Std. P Mixed-Signal Test Bus Standard m Proposed to extend the concept of boundary-scan to analog and mixed signal devices l IEEE Std. P Module Test and Maintenance Bus Standard m Defines specifications for a serial test and maintenance bus for systems with two or more modules plugged into a backplane l IEEE Std Waveform and Vector Exchange Specification (WAVES) m Defines standard for VHDL description of stimulus vectors and responses l MIL-HDBK-XX47 Testability Analysis Handbook m Defined the DoD view of Design for Test

144 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP IEEE Std Standard Test Access Port and Boundary-Scan Architecture l Defines standard terms l Defines the boundary-scan cell architecture, TAP controller architecture, and board-under-test architecture described previously l Defines the test modes described previously l Defines alternative cell and board architectures l Defines the actual state diagram for the TAP controller l Defines timing relationships for controller states and TAP port events l Defines the functionality of the Instruction, Test Data, and Bypass registers

145 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP TAP Controller State Diagram Test-Logic- Reset Run-Test-/ Idle TMS=1 0 Select- DR-Scan Capture-DR Shift-DR Exit-DR Pause-DR Exit2-DR Update-DR Select- IR-Scan Capture-IR Shift-IR Exit-IR Pause-IR Exit2-IR Update-IR [IEEE ] © IEEE 1990

146 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Logic Operation: Data Scan TCK TMS Controller state TDI Data input to IR IR shift-register Data input to TDR TDR shift-register Parallel output of TDR TDO Select-DR-Scan Run-Test/Idle Capture-DR Exit1-DRExit2-DRExit1-DR Update-DR Shift-DR Pause-DR Shift-DR Select-DR-Scan Select-IR-Scan Run-Test/Idle Test-Logic-Reset Parallel output of IR = Don’t care or Undefined Output Inactive Output from selected test data register InstructionIDCODE Old DataNew Data [IEEE ] © IEEE 1990

147 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP IEEE Std b BSDL l BSDL is intended to provide a machine-readable means of representing some parts of the documentary information specified in l The goal of the language is to facilitate communication between companies, individuals, and tools that need to exchange information on the design of test logic; for example: l Suppliers can supply BSDL descriptions of components that support to purchasers m ATPG tools could use BSDL description of components on a board to generate test vectors m BSDL descriptions of compliant components could be used for synthesis

148 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP IEEE Std b BSDL (Cont.) l BSDL is a subset of IEEE Std VHDL l A standard VHDL package STD_1149_1_1994 is defined m Attributes q TAP Ports q TAP Instructions m Types q Cell Data q ID Codes m Constants q Cell Types

149 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP IEEE Std. P Standard Module Test and Maintenance (MTM) Bus Protocol l Defines a standardized serial, backplane Test and Maintenance bus l Intended for use in the test, diagnosis, and maintenance of electronic subsystems and modules m Module Test m Subsystem Test m Subsystem Diagnosis m Software/Hardware Development l Defines MTM-Bus architecture l Defines MTM-Bus protocol m Physical layer m Link layer m Message layer

150 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP MTM-Bus Signals... M-moduleS-module Clock Source Master Data (MMD) Slave Data (MSD) Pause Request (MPR) Control (MCTL) Clock (MCLK) [IEEEP1149.5] © IEEE 1995

151 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP MTM Protocol Layers Physical Layer Master Link Layer Master Message Layer Slave Link Layer Slave Message Layer Applications [IEEEP ] © IEEE 1995

152 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module to MTM Test Bus Translation IEEE Std MTM-Bus Bus Transceiver ANSI/IEEE Std Bus Other Board-level Test Buses Test-bus Interface [IEEEP1149.5] © IEEE 1995

153 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP IEEE Std Waveform and Vector Exchange Specification (WAVES) l A language for specifying stimulus and response patterns for digital electronic systems l Provides for unambiguously exchanging such patterns between and among design and test environments l Can represent various levels of waveform detail m Simulator event trace data m Highly structured test vectors typical of automatic test equipment l WAVES is a subset of IEEE Standard VHDL l WAVES declarations and procedures declared in separate package - instantiated with circuit- under-test in test bench

154 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP IEEE Std WAVES (Cont.) l WAVES Package: m Required Declarations q Logic Value - values to be applied directly to DUT q Pin Codes - “input” values used to list waveform q Test Pins - list of pins in the waveform m Waveform Generator Procedure - reads “input values” and applies them to the DUT q Values can be build in to the generator procedure ïSimple list ïGenerator algorithm q Values can be read from an external file

155 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP MIL-HDBK-XX47 Testability Analysis Handbook l Outlines the DoD documents that relate to DFT m MIL-STD-2165A, Testability Program for Systems and Equipment m MIL-STD-499A, Engineering Management m MIL-STD-470A, Maintainability Program Requirements for Systems and Equipments m MIL-STD A, Logistics Support Analysis m MIL-STD-785, Reliability Program for Systems and Equipments Development and Production m MIL-HDBK-59, Department of Defense Computer-Aided Acquisition and Logistics Support (CALS) Program Implementation Guide m MIL-STD-1814, Integrated Diagnostics, Roadmap, and Requirements Document

156 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP MIL-HDBK-XX47 (Cont.) l Test Design and Assessment m Incorporate embedded and external test capability for a system or equipment that will satisfy testability performance requirements m Assess the level of test effectiveness that will be achieved for a system or equipment m Ensure the effective integration and compatibility of this test capability with other diagnostic elements l Outputs m Product fault detection and fault isolation performance levels that achieve the specified test effectiveness requirements

157 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

158 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Lockheed Martin ATL DFT Methodology The Expanded Definition of “Testing” in the DFT Methodology System Definition Architecture Definition Detailed Design Manufacturing Field Support The “Testing” Process [Sedmak95]

159 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP ATL DFT Methodology Terms and Definitions Prediction The assessment of the degree of compliance to test requirements through analysis or comparison with similar library elements  Examples of means: Circuit level testability measures, topological dependency models Verification The assessment of the degree of compliance to test requirements through simulation or closed form proof  Examples of means: Deterministic fault simulation, exhaustive test coverage proofs Measurement The assessment of the degree of compliance to test requirements through monitoring test performance on a physical item under test Examples of means: Automatic fault history logging, ATE- based data collection [Sedmak95]

160 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP ATL DFT Methodology Additional Terms and Definitions Metrics Quantitative parameters used for requirements specification, compliance tracking, tradeoff analysis, and selection TMAT The Test Metrics/Tool Application Table, used in the Methodology to select a metric and tool(s), or method, to predict, verify, or measure compliance [Sedmak95]

161 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Relationship of Test Requirements, Test Strategies and Test Architectures Test Requirements Test Strategies (TSD) Tester Architecture Testability Architecture DFT & BIST Features, Test Vectors Test Access & Vectors Test Architecture (TA) Testbench Architecture Testbenches Test Plans Test Means Test Procedures [Sedmak95]

162 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP System Test Requirements Test Strategies (TSD) Tester Architecture Testability Architecture DFT & BIST Features, Test Vectors Test Access & Vectors Test Architecture (TA) Testbench Architecture Testbenches Test Plans Test Means Test Procedures Subsystem Test Requirements Test Strategies (TSD) Tester Architecture Testability Architecture DFT & BIST Features, Test Vectors Test Access & Vectors Test Architecture (TA) Testbench Architecture Testbenches Test Plans Test Means Test Procedures Board Test Requirements Test Strategies (TSD) Tester Architecture Testability Architecture DFT & BIST Features, Test Vectors Test Access & Vectors Test Architecture (TA) Testbench Architecture Testbenches Test Plans Test Means Test Procedures MCM Test Requirements Test Strategies (TSD) Tester Architecture Testability Architecture DFT & BIST Features, Test Vectors Test Access & Vectors Test Architecture (TA) Testbench Architecture Testbenches Test Plans Test Means Test Procedures Chip Test Requirements Test Strategies (TSD) Tester Architecture Testability Architecture DFT & BIST Features, Test Vectors Test Access & Vectors Test Architecture (TA) Testbench Architecture Testbenches Test Plans Test Means Test Procedures Requirements Predict, Verify & Measure Relationship of Test Requirements, Test Strategies, and Test Architectures across Packaging Hierarchy [Sedmak95]

163 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Strategy Diagram (TSD) l Used to bridge from requirements to implementation and through to manufacturing and field support m Organizes and manages the key data generated during, and flowing between the methodology process steps m Based on simple three dimensional spreadsheet type structures and operations m Fault populations flow through various test means until they are Detected, Isolated and Corrected [Sedmak95]

164 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Strategy Diagram (Cont.) l Examples of applications include: m Capturing quantitative test requirements m Developing test strategies and making tradeoffs, including analysis of the mixing of test means m Flowing requirements down to lower assembly levels m Capturing predicted, verified, and measured (PVM) test performance data and comparing it against requirements for compliance tracking m Rolling up test performance PVM data from lower levels for system level analysis m Performing parametric analysis such as test time, product quality [Sedmak95]

165 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP ATL DFT Methodology in the RASSP Methodology Manufacturing/ Integration & Test Field Support DFT/BIST Flowdown and Implementation Detailed Design DFT/BIST HW DFT/BIST SW DFT/BIST Strategy and Architecture Development Architecture Definition DFT/BIST HW Ver DFT/BIST SW Ver RASSP Design Process HW/SW Codesign System Definition Detailed Design HW SW RASSP Reuse Library Systems Hardware Test Architecture Software Etc.. Architecture Definition HW SW HW SW F.D. Model Year N-1 Results F.D. Manufacturing Test Req.'s. Customer & Derived Consolidated Test Requirements System Definition Field Test & ARM Req.'s. Customer & Derived Development Test Req.'s. Customer & Derived PREDICT VERIFY MEASURE Test Requirements Compliance Tracking Model Year Architecture Test Architecture Manufacturing/ Integration & Test Field Support DFT HW Select DFT SW Select [Sedmak95]

166 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP ATL HW Testability Architecture l Bias towards Boundary Scan and BIST but accommodate COTS and use ATE when required and/or practical l “Lead - Follow - or Get out of the Way” philosophy for MCM/ board and system test l Hierarchical array of dedicated Test & Maintenance Busses and controllers (IEEE , P1149.5, Scan Bridge™, and/or ASP™ as required) l Re-useable (within and between packaging level) BIST controllers, PRPG’s and SAR’s l Accommodates ‘Spoilers’ m COTS m NDI m Development Only Contracts m Expendables LRU LRU Test Controller Module Executive Board Backplane Board Test Controls Test Bus Chip Test Bus TAP Chip TAP Chip TAP Chip System Maintenance Controller System Maintenance Bus Operating System [Sedmak95]

167 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP RASSP Concepts which DFT Leverages RASSP concepts provides a good framework for integrating design with test. [Sedmak95]

168 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Benefits of Integrating DFT into RASSP 1. Consolidate test requirements 2. Incorporate TSD construct 3. Extend concept of re- use 4. Implement conformance checking (via TSD). 5. Model test resources in VP 6. Integrate test architecture with MYA ApproachBenefit 1. Reduce overall test development efforts and cost 2. Bridge requirements to implementation 3. Minimize impact of test on schedule and cost 4. Consistent framework for feedback of model year results. 5. Concurrent test development shortens schedule 6. Consistent use; Model year upgrades of test resources [Sedmak95]

169 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Design-For-Test Integration Tasks l Work Flows and Activity Definitions l DFT Tool Integration's m CAT or Test Specific (Fault simulation, Testability Analysis, DFT/ BIST insertion, ATPG,...) m CAE or Re-use of functional engineering tools (HDL Entry, SW development, simulation, Data Management,...) l Re-use Libraries m Object Class Hierarchy (DOCH) m Contents of re-use elements (what data constitutes a re- use element) m Initial population of critical elements l Templates and standards for test related product data l Training m Benefits m Process m Tools [Sedmak95]

170 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Module Outline l Introduction (Part 1) l Fault Modeling l Test Generation l Automatic Test Pattern Generation Algorithms l Fault Simulation Algorithms l Introduction (Part 2) l I DDQ Testing l Design for Testability Techniques l Built-In Self Test l Hierarchical Design for Test l Synthesis for Test l DFT Standards l Design Flows with DFT l Summary

171 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Summary l A background on general testing was provided m Fault Modeling m Test Generation m Faults Simulation m I DDQ Testing l A background on Design for Test was provided m DFT Techniques m Built-in Self Test Techniques m Hierarchical DFT Techniques m Synthesis for Test l Finally, a background on how testing and DFT is used in the design process was provided m DFT Standards m Design flows with DFT

172 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP References [Aitken95] Aitken, R. C., “An Overview of Test Synthesis Tools,” IEEE Design and Test of Computers, pp. 8-15, Summer [Abadir94] Abadir, M., G. McFall, S. Spencer, K. Drake, J. Evans “A Hierarchical Design for Test (DFT) Methodology for the Rapid Prototyping of Application Specific Signal Processing (RASSP),” Preliminary Working Document, Version 0.73, August 10, [Abramovici90] Abramovici, M., M. A. Breuer, A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Computer Society Press, 1990 ; © IEEE 1990 [Agarwal95] Agarwal, V. K., “Hierarchical and Integrated Build-In Self-Test CAD Tools,” Proceedings of the RASSP PI Meeting January 9-13, [Fujiwara85] Fujiwara, H. Logic Testing and Design for Testability, The MIT Press, [Hayes85] Hayes, John P., “Fault Modeling,” IEEE Design and Test of Computers, April, 1985, pp [Hemmady94] Hemmady, S., “VLSI Test Automation: Fact or Fiction?,” ASIC $ EDA, September 1994, pp [IEEE] All referenced IEEE material is used with permission. [IEEE1149.1] IEEE Standard Test Access Port and Boundary-Scan Architecture; © IEEE 1990 [IEEEP1149.5] IEEE P Standard Module Test and Maintenance (MTM) Bus Protocol; ; © IEEE 1995 [Johnson89] Johnson, B. W., Design and Analysis of Fault Tolerant Digital Systems, Addison-Wesley, [Kim88] Kim, K., D. S. Ha, “On Using Signature Registers as Pseudorandom Pattern Generators in Built-In Self-Testing,” IEEE Transactions on Computer-Aided Design, Vol. 7, No. 8, August 1988, pp ; © IEEE 1988

173 Copyright  SCRA Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP References (cont.) [Klenke92] Klenke, R. H., R. D. Williams, J. H. Aylor, “Parallel-Processing Techniques for Automatic Test Pattern Generation,” IEEE Computer, January 1992, pp ; © IEEE 1992 [Lesser80] Lesser, J. D., J. J. Shedletsky, “An Experimental Delay Test Generator for LSI Logic,”, IEEE Transactions on Computers, March, 1980, pp [Richards97] Richards, M., Gadient, A., Frank, G., eds. Rapid Prototyping of Application Specific Signal Processors, Kluwer Academic Publishers, Norwell, MA, 1997 [Sedmak95] Sedmak, R., J. Evans, “Tutorial on the RASSP Design-for-Test ability Methodology,” 2nd Annual RASSP Conference, [Soden92] Soden, J. M., C. F. Hawkins, R. K. Gulati, and W. Mao, “I DDQ Testing: A Review,” Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, Norwell, MA, 1992, pp [MAbadir94] Abadir, M. S., “Hierarchical Design for Testability Tools for RASSP,” Supplemental presentation material for the Martin Marietta RASSP Semi-Annual Government Review, February, 23 & 24, [Maxwell92] Maxwell, P. C., R. C. Aitken, “IDDQ Testing as a Component of a Test Suite: The Need for Several Fault Coverage Metrics,” Journal of Electronic Testing: Theory and Applications (JETTA), Kluwer Academic Publishers, Norwell, MA, Vol. 3, No. 4, December 1992, pp [Maly87] Maly, W., “Realistic Fault Modeling for VLSI Testing,” Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, pp [Malaiya86] Malaiya, Y. K., A. P. Jayasumana, R. Rajsuman, “A Detailed Examination of Bridging Faults,” IEEE, 1986, pp [Waicukauski87] Waicukauski, J. A., et. al., “Transitional Fault Simulation,” IEEE Design & Test, April, 1987, pp ; © IEEE 1987 [Williams83] Williams, T. W., K. P. Parker, “Design for Testability - A Survey,” Proceedings of the IEEE, Vol. 71, No. 1, January 1983, pp ; © IEEE 1983


Download ppt "Copyright  1995-1999 SCRA 1 Methodology Reinventing Electronic Design Architecture Infrastructure DARPA Tri-Service RASSP Test Technology Overview RASSP."

Similar presentations


Ads by Google