1. 1 IKI10230 Pengantar Organisasi Komputer Kuliah no. 11: Control Unit Sumber: 1. Paul Carter, PC Assembly Language 2. Hamacher. Computer Organization, ed-5 3. Materi kuliah CS61C/2000 & CS152/1997, UCB 5 Mei 2004 L. Yohanes Stefanus (yohanes@cs.ui.ac.id) Bobby Nazief (nazief@cs.ui.ac.id) bahan kuliah: http://www.cs.ui.ac.id/kuliah/POK/

2. 2 Prosesor: Control & Datapath Processor (active) Computer Control (“brain”) Datapath (“brawn”) Memory (passive) (where programs, data live when running) Devices Input Output

3. 3 Review: Organisasi Prosesor (Single-bus) Y Z MDR MAR PC TEMP R(n-1) R0 IR Instruction Decoder ALU Carry-in Add Sub XOR Address lines Data lines Control lines Memory bus ALU control lines Control Unit Datapath Unit

4. 4 Interaksi Memori  [Control,Datapath] Data Out Clk 5 RwRaRb Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

5. 5 Interaksi Control  Datapath STEPCONTROL SIGNALS 1.PC out, MAR in, Read, Clear Y, Set carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.R3 out, MAR in, Read 5.R1 out, Y in, WMFC 6.MDR out, Add, Z in 7.Z out, R1 in, End Control Instruction Datapath IR Conditions Control Signals PC out MAR in ADD Ri in

6. 6 Pengendalian Eksekusi Instruksi: Hardwired Control

7. 7 Hardwired Control Organization Encoder Control Step Counter Clock IR Status Flags Condition Codes Instruction Decoder Step Decoder MOV CLK    T 1 T 2    T n    Control Signals             ADD INS n Run End Reset

8. 8 Hardwired Control Encoding °Fungsi Logika: Z in = T 1 + T 6  ADD + T 5  JMP + … °Z in akan terjadi pada: T 1 : untuk setiap instruksi (instruksi berikut: PC+1) T 5 : untuk instruksi ADD T 6 : untuk instruksi JMP ADD JMP T6T6 T5T5 T1T1  Z in

9. 9 Pengendalian Eksekusi Instruksi: Microprogrammed Control

10. 10 Microprogramming °Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global Microprogramming: -- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note: -- IBM 360 Series first to distinguish between architecture & organization -- Same instruction set across wide range of implementations, each with different cost/performance

11. 11 Microinstructions STEPCONTROL SIGNALS 1.PC out, MAR in, Read, Clear Y, Carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.R3 out, MAR in, Read 5.R1 out, Y in, WMFC 6.MDR out, Add, Z in 7.Z out, R1 in, End 00110000010111100 01000000001000010 10001000000000000 00010000100000100 00000101000000010 00001000010001000 00000010001000001 IR in PC in PC out MAR in MDR out Y in R1 in R1 out R3 out Z in Z out Clear Y Carry-in Add Read WMFC End 12345671234567

12. 12 Microinstruction Organization μAR Control Store μIR Status Flags Condition Codes IR Decoding Circuits Next Address μ Instruction Decoder    Control Signals

13. 13 Microinstruction Encoding 000: No transfer 001: PC out 010: MDR out 011: Z out 100: Rsrc out 101: Rdst out 000: No transfer 001: PC in 010: IR in 011: Z in 100: Rsrc in 101: Rdst in 0000: ADD 0001: SUB. 1111: XOR 000: No transfer 001: MAR in 010: MDR in 011: TEMP in 100: Y in F3 F1 F0 F2 (3 bits) (8 bits) (3 bits) Address of next microinstruction F4 F9 (1 bit)... (4 bits) F8 (1 bit) 0: NextAdrs 1: InstDec 0: No action 1: OR mode F10 (1 bit) 0: No action 1: OR indsrc

14. 14 Content of μStore F0F1F2F3F4F5 F6F6 F7F7 F8F8 F9F9 F10F10 00100101100100000110000 00201100110000000001000 01101001000000000000000 00000000000000000000110 12210001100100000110000 17001110000000000001001 17101000000100000101000 17201000010000000000000 17310101100000000000000 00001110100000000000000 000 001 002 003 121 122 170 171 172 173

15. 15 /Etc

16. 16 “Macroinstruction” Interpretation Main Memory execution unit control memory CPU ADD SUB AND DATA...... User program plus Data this can change! AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) one of these is mapped into one of these

17. 17 Control: Hardware vs. Microprogrammed °Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial RepresentationFinite State Diagram Microprogram Sequencing ControlExplicit Next State Microprogram counter Function + Dispatch ROMs Logic RepresentationLogic EquationsTruth Tables Implementation TechniquePLAROM “hardwired control”“microprogrammed control”