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The Role of Programmable DSPs in 3G Handsets Chaitali Sengupta February, 2002.

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Presentation on theme: "The Role of Programmable DSPs in 3G Handsets Chaitali Sengupta February, 2002."— Presentation transcript:

1 The Role of Programmable DSPs in 3G Handsets Chaitali Sengupta February, 2002

2 Overview 3G Wireless Standards Functional view of 3GPP FDD-DS (WCDMA) Complexity analysis Mapping to architecture System design methodology

3 Wireless Cellular Systems Backbone Network IS-95, GSM, IS-136 3rd Gen. (W-CDMA, …..) PSTN ISDN

4 3G Wireless Standards Focus: 3GPP FDD Direct Sequence Mode (WCDMA) 2G - Today 2.5G G GPRS IS95B IS95 PDCToday’s Market % 9% 66% 10% 15% CDMA2000 J-WCDMA EDGE IS136 W-CDMA GSMGSM

5 3GPP FDD-DS mode Parameters defining the FDD-DS (WCDMA) 3G standard ParameterDescription/value Carrier spacing5 MHz Physical frame length10ms Spreading factor2 k, k=2-8: UL, 2 k, k=2-9: DL Channel codingConvolutional and Turbo MultirateVariable spreading / multicode Diversity techniquesMultiple Tx antennas, Multipath Maximum data rates384Kbps / 2Mbps

6 Handset top level ARM DSP ABB RF MMI APPLICATION TASKS PROTOCOL STACK DATA I/O LCD, Camera, Etc. L1 SW L1 DBB HARDWARE

7 WCDMA System Downlink SOURCE CODING CHANNEL CODING, INTERLEA VER, ETC SPREADING ABB and RF DEINTERLEAVERDESPREADER ABB and RF CHANNEL ESTIMATION user’s bits TRANSMITTER RECEIVER (BASE STATION) (MOBILE USER) channel MRC (multipath and Tx diversity) DPE AND FINGER ALLOCATION TIME TRACKING AUTOMATIC GAIN CONTROL FREQUENCY TRACKING RATE MATCHING VITERBI/TURBO (CHANNEL DECODER) VOCODER, APPLICATION, ETC CRC CHECK

8 Despread I/Q data from A/D MRC CCTrCH DPE Layer3 (RRC) and Protocol stack (control) AFC to ABB & RF Search 1 RX Spreading (Chip-level) CCTrCH processing to D/A TX vocoder Viterbi Turbo MAC (L2) de-ciphering vocoder applications Protocol stack (data) Ch. Est. Finger alloc. DLL power control Directed search Initial search Measurements (neighbor & active set) AGC Set Maintenance ciphering MAC (L2) applications DBB Functional View

9 DBB Design Goals Power, power, power –But: DBB is % of total handset power Flexibility –Evolving standards –Fine tuning in field Scalability –Increasing data rates Fast design cycle Cost

10 Complexity Analysis Decoders Search/track Despread MRC A: 8 Kbps voice only B: 12.2 Kbps voice Kbps data C: 2 Mbps data A B C

11 HW/SW partitioning Processing requirements depend on: –data rate, number of strong cells in the vicinity, wireless channel conditions, etc. Primary tradeoff: power vs. flexibility Dedicated HW: –Lowest power achievable for target functions –Lower flexibility to change SW processing on low power DSPs –Higher flexibility

12 HW/SW partitioning Category 1: Definitely in HW in the near term, –Very high MIPS or data I/O requirements –E.g. despreading Category 2: Definitely in SW –Reasonable processing requirements –Requires flexibility –E.g. channel estimation Category 3: In HW or SW based –Total power targets –Service scenarios for a specific implementation –Maximal Ratio Combining (MRC)

13 Despread I/Q data from A/D MRC CCTrCH DPE Layer3 (RRC) and Protocol stack (control) AFC to ABB & RF Search 1 RX Spreading (Chip-level) CCTrCH processing to D/A TX vocoder Viterbi Turbo MAC (L2) de-ciphering vocoder applications Protocol stack (data) Ch. Est. Finger alloc. DLL power control Directed search Initial search Measurements (neighbor & AS) AGC Set Maintenance ciphering MAC (L2) applications SW SW/HW HW

14 Co-processor approach How to get flexibility at low power and cost? “loosely coupled” (LCC) and “tightly coupled” (TCC) coprocessors –Based on average time to complete an “instruction” Find a DSP/coprocessor partition that balances flexibility with a reasonable MIPs level on the DSP. E.g., for Viterbi decoding: –the DSP could perform all the data processing up to the branch metric generation and –a coprocessor could perform the remaining high MIPS tasks of state metric update and trace back.

15 Tightly coupled coprocessors TCC: task completes in the order of a few instruction cycles Small amount of data processed per task The DSP will freeze during the operation of the TCC. TCC to main processor communication typically occurs through register reads and writes. E.g. bit manipulation coprocessor Processors that allow instruction set enhancement through hardware TCC units by means of a “Co-processor Port” –ARM processor (the ARM7TDMI), and the TMS320C55x processor With time, the function of the TCC may migrate into the DSP

16 TMS320C55x TCC Memory System Instruction decode Register file T C C I/f TCC instructions Tightly coupled coprocessors

17 Loosely coupled coprocessors LCC: Task will run in parallel to the DSP for many instruction cycles before it requires more interaction with the DSP. Solves the serious problem of bus bandwidth –Computational units local to the data and arranged specifically for the data access required for a class of computations. In time the LCC functionality will migrate to the DSP: –When DSP bus bandwidth and computational power is sufficient. E.g. LCC for WCDMA chip rate processing (despreading, time tracking, path search) –Coprocessor can perform simple but high MIPS tasks –DSP provides configuration (e.g. averaging length for path search) –In effect the system is fully programmable within the domain of WCDMA chip rate processing.

18 chips from AFE SRAM CORRELATOR COPROCESSOR Analog Front end (AFE) Input buffer Output buffer Datapath Address Generation Address Generation Controller & Counters Instruction buffer PN Generation DSP DSP/ coprocessor interface Loosely coupled coprocessors

19 Centralized v.s. Distributed Architectures The WCDMA system is parallel in nature Centralized approach: –Resource sharing between functions –Centralized and more complex control –Lesser area Distributed approach –Possibly lesser power as components may be switched off when idle –Less complex control Most practical systems need a mix of both

20 Handset top level ARM DSP ABB RF MMI APPLICATION TASKS PROTOCOL STACK DATA I/O LCD, Camera, Etc. L1 SW L1 DBB HARDWARE

21 Control plane and Data processing Use of a DSP and micro-controller combination –DSP is responsible for the heavy-duty signal processing –Control plane is divided between the DSP and the micro- controller. DSP typically deals with low latency hard real time functions Micro-controller provides –Centralized control of all physical layer resources –Higher layers in the protocol stack with decreasing real time content Texas Instruments OMAP TM architecture consisting of an ARM9 and a C55x processor.

22 Modem and Applications Same platform or multiple? Issues: –Development logistics –Protecting the real time nature of the modem Type approval –Power and cost of course! In practice there will possibly be both types –Separate platforms: high end phones, –Single platform: low end primarily voice and less demanding applications

23 System Analysis Methodology How to manage design of such complex systems with so many optimization criteria? Top down methodology Characterization of application –Control plane –Data plane Characterization of architecture options Abstract models of performance for fast simulations of application to architecture mapping.

24 Summary 3G handset DBB has processing requirements several times higher than 2G Power is the driving criteria followed by cost and flexibility Completely DSP SW processing is not possible Challenges: –Choice of system partitioning –Design of dedicated HW with sufficient flexibility working with programmable DSPs –Methodology to support such decisions!

25 Reference The Role of Programmable DSPs in Dual Mode (2G+3G) Handsets. C. Sengupta, N. Veau, S. Sriram, Z. Gu, P. Folacci, S. Kinjo. Book chapter in: The Application of Programmable DSPs in Mobile Communications. Editors: A. Gatherer and E. Auslander

26 Performance Simulation APPLICATION Scenario (1) Scenario (N) Data plane Control plane Processes Control flow (messages) Data flow System steady state ARCHITECTURE Components (e.g DSP core, peripherals, DMA) Platform Schedulers / rules (e.g. bus arbitration policies, DMA protocols, scheduling policies) MAPPING Mapping options Resource consumption (of process mapped to component; in MHz, memory, IO) SIMULATION (in VCC: data plane driven by control plane, no actual data processing or data transfer ) PERFORMANCE (Total MHz, memory, I/O)


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