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Current and Future Directions in Hybridization for Pixelated Particle Detectors Alan Huffman Center for Materials and Electronic Technologies
Copyright © 2004 MCNC-RDI. All rights reserved. Outline Who is RTI? Solder Bump Technology – Bumping process – Post bump processes Wafers thinning Dicing control – Hybridization Current Programs and Results – CMS – MEDIPIX Future Technologies for Hybridization – 3D integration technology – Alternative bump materials – Alternatives to sawing
Copyright © 2004 MCNC-RDI. All rights reserved. A Crisis of Identity…Who is RTI? RTI acquired the research groups formerly known as MCNC Research & Development Center in March 2005 RTI/MCNC has over 15 years experience in the development and implementation of flip chip technology, including the spin off of Unitive Electronics in 1998 (Amkor) Fine pitch flip chip (<100 µm) has been ongoing since 1997
Copyright © 2004 MCNC-RDI. All rights reserved. Important Points of Pixel Devices for Bumping I/O pitch typically less than 100 µm High interconnect counts, from a few thousand to over 65,000 Large readout and sensor chip size (~ 1 cm 2 and larger) Multi-chip modules (MCM) typically needed to create large area sensor arrays Materials used must withstand high radiation environment Flux-free assembly processes are a necessity
Copyright © 2004 MCNC-RDI. All rights reserved. Fine Pitch Solder Bumping Formation of fine pitch solder bumps uses essentially the same processes as ‘standard’ pitch flip chip Tighter control must be maintained over the processes than for typical wafer level packaging (WLP) applications due to smaller geometries Additional post-wafer bumping processes are sometimes needed (i.e. wafer thinning) which can easily damage small solder bumps
Copyright © 2004 MCNC-RDI. All rights reserved. RTI Fine Pitch Bumping Process Flow Incoming Wafer With I/O Pads Repassivation With BCB UBM Deposition Apply and Define Plating Template Plate Solder or Wettable Metal Strip Resist Template Reflow Etch Field UBM
Copyright © 2004 MCNC-RDI. All rights reserved. Solder Bumped ROC and Sensor (US-CMS) 25 µm bump base diameter and 25 µm bump height Ni/Au bump bonding pads
Copyright © 2004 MCNC-RDI. All rights reserved. Solder Bumped ROC and Sensor (MEDIPIX) 50 µm pitch readout chip with eutectic Sn/Pb bumps 50 µm pitch sensor chip with Ni/Au bump bond pads
Copyright © 2004 MCNC-RDI. All rights reserved. Post-Bumping Wafer Thinning Wafer thinning is done after bumping to prevent excessive handling and processing of thin wafers A protective layer is applied to the wafer to protect the bumps during the taping, thinning, and de-taping processes Wafer thinning process consists of two steps – Grind: to quickly remove Si from the wafer backside – Stress relief: to remove the damaged Si layer and alleviate the stress created in the silicon during the grind Protective layer is removed prior to dicing
Copyright © 2004 MCNC-RDI. All rights reserved. Dicing Considerations Thinned ROC wafers are more susceptible to damage during dicing and require different blades and parameters Dicing kerf must be very close to the active area (50 µm or less) on ROCs to allow close placement in multi-chip module assembly Thin, high resistivity silicon sensors are susceptible to chipping and microcracking during dicing, which increases the leakage current
Copyright © 2004 MCNC-RDI. All rights reserved. Poorly Diced Sensor Wafers
Copyright © 2004 MCNC-RDI. All rights reserved. Cleanly Diced Sensor
Copyright © 2004 MCNC-RDI. All rights reserved. Assembly Processes Flip chip assembly of fine pitch bumped devices requires high placement accuracy bonder Assembly of multi-chip module detectors have ROCs in very close proximity (~150 µm); process must not disturb previously placed die Use of flux for reflow is undesirable due to difficulty removing flux residue under large chips
Copyright © 2004 MCNC-RDI. All rights reserved. Chip-to-substrate gap reduces from 65µm to 22µm for 25µm diameter bumps Standard Vs. Fine-Pitch Assembly 250um Pitch 50um Pitch
Copyright © 2004 MCNC-RDI. All rights reserved. Plasma Assisted Dry Soldering (PADS) Replaces flux in assembly process Solder-bearing parts treated prior to assembly Short (10-15 min) treatment time Leaves no residues on chip or substrate Proven applications in SMT, MEMS, photonics, and standard flip chip packaging and assembly processes
Copyright © 2004 MCNC-RDI. All rights reserved. Current Programs
Copyright © 2004 MCNC-RDI. All rights reserved. CMS Detector Modules Readout chips are fabricated on full thickness 8-inch silicon wafers and are thinned to 200 µm prior to assembly, 4160 bumps per chip Sensor wafers are fabricated on thin, high resistivity wafers Bump size is 25 micron base diameter with a minimum I/O pitch of 50 microns 6 different module sizes: 1x1, 1x2, 1x5, 2x3, 2x4, 2x5 Full detector will require over 800 total modules with about 5000 individual readout chips Total number of bumped connections is over 20,000,000
Copyright © 2004 MCNC-RDI. All rights reserved. 2x4 detector module in test fixture Courtesy: US-CMS FPix Collaboration Pixilated Detector Module Assemblies
Copyright © 2004 MCNC-RDI. All rights reserved. Yield Data Recent evaluation of CMS detector modules (1x1, 1x2, 1x5, 2x3, 2x4, 2x5 arrays, 76 total modules) – 1134 bad bump connections out of about 2,000,000 – Bump bonding yield of 99.94% Leakage current measurements previously completed on 61 modules – 60 of 61 modules meet leakage current specifications at 250V – 59 of 61 modules meet leakage current specifications at 600V – Power consumption on all modules within spec Courtesy: US-CMS FPix Collaboration
Copyright © 2004 MCNC-RDI. All rights reserved. Sensor Wafer 029 Yield Data Courtesy: US-CMS FPix Collaboration
Copyright © 2004 MCNC-RDI. All rights reserved. Yield Data Courtesy: US-CMS FPix Collaboration
Copyright © 2004 MCNC-RDI. All rights reserved. MEDIPIX Consortium - CERN X-ray/gamma ray detector devices working in single photon counting mode 55 µm pitch, uniform in both directions Detector modules of 1x1 (~1 in 2 ) and 2x2 (~4 in 2 ) MEDIPIX ASIC is used in conjunction with different sensor devices for a number of applications – X-ray imaging – Biological radiography – Neutron detection
Copyright © 2004 MCNC-RDI. All rights reserved. MEDIPIX 2x2 detector array Pixilated Detector Module Assemblies
Copyright © 2004 MCNC-RDI. All rights reserved. MEDIPIX2 Images Courtesy: MEDIPIX Collaboration
Copyright © 2004 MCNC-RDI. All rights reserved. MEDIPIX2 Images Courtesy: MEDIPIX Collaboration
Copyright © 2004 MCNC-RDI. All rights reserved. Future Hybridization Technologies 3D Integration Alternative Bump Materials Alternative Singulation Processes
Copyright © 2004 MCNC-RDI. All rights reserved. 3D Integration Through via interconnects (TVI) are formed through bulk silicon in active devices Allows multiple device layers to be interconnected front-to-back TVIs can be formed before or after devices are physically joined together – Significant process differences between vias first process and vias last process – Process used dictated by device design and process compatibility Allows array sizes not limited to 1xN or 2xN modules: true area array ROC placement
Copyright © 2004 MCNC-RDI. All rights reserved. Benefits of 3D Integration: Pixelated Devices Detector/Sensor Arrays 3-D ROIC 3-D Interconnects 3-D Integration allows massively parallel signal processing Dramatically increased electronic functionality in each pixel Actuator Arrays 3-D Interconnects DARPA Coherent Communications, Imaging & Targeting (CCIT) program Spatial light modulators w/digital control of optical wave front phases MEMS Actuator Mirror 3-D Sensor Arrays Large formats with high resolution On-chip signal processing Reduction of size, weight & power 3-D Actuator Arrays Large formats with high resolution Low switching energy & latency Reduction of size, weight & power
Copyright © 2004 MCNC-RDI. All rights reserved. Test Structure Operability Test Demonstrated 99.98% operability in 256x256 arrays with 4 m vias on 30 m pitch 65,536 interconnects in ~1 cm 2 Si IC 25 m Operability Map Nonfunctional cell 20 m 256x256 ROIC Insulator Copper Si IC 14 Defective pixels
Copyright © 2004 MCNC-RDI. All rights reserved. Imaging Demonstration Demonstrated image from 256x256 MWIR FPA built on 2- layer stack with 4 mdiameter3-D interconnects (one per cell) FPA cross section Thermal image
Copyright © 2004 MCNC-RDI. All rights reserved. Alternative Bump Materials Non-collapsible bump materials may be useful for extremely small bump interconnections (~5 µm dia.) Sn-capped Cu bumps
Copyright © 2004 MCNC-RDI. All rights reserved. Alternatives to Saw Dicing Silicon etching using Bosch process allows damage-free singulation of ROCs and sensor devices Dicing streets must be free of metal Deposit and pattern photoresist Bosch etching Bosch etching complete Photoresist removal
Copyright © 2004 MCNC-RDI. All rights reserved. Conclusion RTI has developed a number of technologies to enable the successful bumping and hybridization of pixel devices Currently applying these technologies to CMS and MEDIPIX projects for detector manufacture New technologies under development will someday enable smaller pixel sizes in larger arrays with more functionality
Fin Alan Huffman
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