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Programmable Architectures for Communication Systems D. K. Arvind Institute for Computing Systems Architecture, Division of.

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Presentation on theme: "Programmable Architectures for Communication Systems D. K. Arvind Institute for Computing Systems Architecture, Division of."— Presentation transcript:

1 Programmable Architectures for Communication Systems D. K. Arvind Institute for Computing Systems Architecture, Division of Informatics, The University of Edinburgh, Mayfield Road, Edinburgh EH9 3JZ, Scotland.

2 Edinburgh - The Capital City

3 Overview   University of Edinburgh   Division of Informatics   Edinburgh InfoLab   Research   Collaboration

4 University of Edinburgh   Founded in 1583   Student Population - 18,023 :   Undergraduate - 15,350; Postgraduate - 2,673   Staff - 6,649 :   Academic Staff - 3,312

5 “Informatics is the study of the structure, behaviour, and interactions of both natural and artificial computational systems.” ( Division of Informatics Institute for Adaptive and Neural Computation Institute for Adaptive and Neural Computation Centre for Intelligent Systems and their Applications Centre for Intelligent Systems and their Applications Institute for Communicating and Collaborative Systems Institute for Communicating and Collaborative Systems Institute for Perception, Action and Behaviour Institute for Perception, Action and Behaviour Laboratory for Foundations of Computer Science Laboratory for Foundations of Computer Science Institute for Computing Systems Architecture Institute for Computing Systems Architecture

6 Division of Informatics Division of Informatics   enjoys an international reputation for both its teaching and research   Only department in the UK awarded the top 5*A research rating in Computer Science in Dec   UK’s biggest department with 87 research-active staff and 165 PhD students   Edinburgh-Stanford strategic research partnership   Location of the National e-Science Centre   Awarded top Excellent rating in the Teaching Quality Assessment

7 The Future …. Proliferation of Peer-to-Peer computing Proliferation of Peer-to-Peer computing fundamental force of change and restructuring fundamental force of change and restructuring Examples Examples Cybiko - P2P wireless networked games Cybiko - P2P wireless networked games Napster - P2P sharing of music Napster - P2P sharing of music Freenet - P2P information store Freenet - P2P information store DoCoMo – P2P communication DoCoMo – P2P communication Unregulated communications channels Unregulated communications channels ISM, UWB, free-space optics, ….. ISM, UWB, free-space optics, ….. System-on-Chip components System-on-Chip components banalisation of silicon technology banalisation of silicon technology Silicon falling behind Silicon falling behind storage & bandwidth improving at a greater rate storage & bandwidth improving at a greater rate

8 P2P systems - Challenges Portability - Java,.NET Portability - Java,.NET Performance - exploit concurrency Performance - exploit concurrency Mobility - size and energy consumption Mobility - size and energy consumption Flexibility - soft- and hard-programmability Flexibility - soft- and hard-programmability

9 Research Focus “To explore novel architectures for P2P systems using banalised technology, and enlighten future development of disruptive products and business change” Our research is seeking programmable solutions which : harness progress in (a) technology (b) theory harness progress in (a) technology (b) theory implement high-performance algorithms and applications efficiently implement high-performance algorithms and applications efficiently

10 Disruptive technology opportunities System Architectures to explore … Personal switch/P2P processor Personal switch/P2P processor Hubless, ephemeral, transient networks Hubless, ephemeral, transient networks Info-torch/Info-Klieg light Info-torch/Info-Klieg light P2P n library|phone|gaming P2P n library|phone|gaming

11 Trends in the silicon fabric Convergence of transduction, communication and computation - heterogeneous systems with sensors and actuators High performance computation at modest power consumption Pre-designed IP blocks with different timing characteristics The dominance of programmable fabrics - both soft- and hard-programmable The complexity of the designs will demand novel architectures and design styles

12 The Die Area reachable in 1 clock cycle (1.2 GHz) At 0.1um (1 Billion transistors) only 16% of the chip is reachable in 1 clock cycle Dominance of interconnect delays over computational ones Network of Temporal Regions

13 Micronets - An alternative vision of Systems Architecture Micronet or Network-on-Chip : a network of entities which operate concurrently and communicate asynchronously Fractal model of system design: network of sub-systems, down to network of transistors Control is layered and distributed locally - behaviour can be decomposed to run on architectural clusters with the optimal mix of computational elements A clean separation between computation and communication, and, behaviour and timing - leads to a compositional design style

14 Behaviour-Architecture Co-design Integration Platforms composed of networks (micronets) of heterogeneous computational entities that operate in a multi-threaded fashion. Integration Platforms composed of networks (micronets) of heterogeneous computational entities that operate in a multi-threaded fashion. Applications composed of software blocks: some pre-defined, such as communication protocols; others, more specific to the application. Applications composed of software blocks: some pre-defined, such as communication protocols; others, more specific to the application. Co-design (Step 1) : recognise concurrent operations and optimise communication at different levels of granularity in the application and map them to the platform Co-design (Step 1) : recognise concurrent operations and optimise communication at different levels of granularity in the application and map them to the platform Co-design (Step 2) : explore the trade-off between programmability (both soft- and hard-), and performance (MOPS/mWatt) of the application running on the platform Co-design (Step 2) : explore the trade-off between programmability (both soft- and hard-), and performance (MOPS/mWatt) of the application running on the platform

15 The COMPASS Design Environment Visualisation of energy and performance effects of compiler optimisations Visualisation of energy and performance effects of compiler optimisations Distributed simulation platform on a 16-node Beowulf cluster Distributed simulation platform on a 16-node Beowulf cluster Java or C applications Java or C applications SSA intermediate representation SSA intermediate representation Soft- and Hard- programmability Soft- and Hard- programmability

16 Design framework for programmable multi-threaded systems

17 A micronet-based multi-threaded architecture

18 void Micronet(chan tinst Inst, chan tpc Pc, chan tregval RegDump, chan Word MemDump) { //Define channels chan tinst ALUinst, MUinst; chan tpc ALUpc; chan tack ALUCUack, MUCUack; chan tregreq RegRequest; chan tregreturn Xout, Yout; chan tregval ALUXin, ALUYin, MUXin, MUYin; chan twriteback toReg, ALUWBout, MUWBout; chan bool KillBus; //Spawn linked Functional Units in Parallel //+ clock 32 par{ //Buffers for register requests //+ clock 32 ControlUnit(Inst, Pc, ALUinst, MUinst, ALUCUack, MUCUack, ALUpc, RegRequest, KillBus ); //+ clock 50 RegisterBank(RegRequest, //Requests //Lock writeback registers Xout, Yout, //To the bus toReg, RegDump); //Writeback //X bus //+ clock 32 BusSplit(Xout, ALUXin, MUXin); //Y bus //+ clock 32 BusSplit(Yout, ALUYin, MUYin); //+ clock 50 ALU(ALUinst, ALUXin, ALUYin, ALUCUack, ALUpc, ALUWBout); //+ clock 32 MU(MUinst, MUXin, MUYin, MUCUack, MUWBout, MemDump); //Writeback bus //+ clock 32 BusMerge(ALUWBout, MUWBout, toReg, KillBus); } Automatic Synthesis of Micronet Architecture from Specification

19 Power/Speed estimations on the M/T architecture Overall TPU 0 TPU 1

20 Power - Speed Tradeoff for Programs executing on Micronet Architectures

21 Example of an Internet Appliance Bluetooth-based system in VCC Two physical objects: the WAPmobile, and a WAP `phone The behaviour of an internet- and Bluetooth-enabled Basestation, and a Bluetooth-enabled robot is simulated in VCC The WAP phone controls the robot in real-time via the VCC behavioural models

22 Proven Research Expertise in Systems Architecture Programmable Architecture Design Programmable Architecture Design Micronet-based asynchronous architectures Micronet-based asynchronous architectures Java and C compilation for multi-threaded embedded systems Java and C compilation for multi-threaded embedded systems Applications include Bluetooth- and based ones Applications include Bluetooth- and based ones Vertically-integrated environment (COMPASS) for energy- conscious, high-performance embedded system design Vertically-integrated environment (COMPASS) for energy- conscious, high-performance embedded system design Industrial research partners Industrial research partners Well-endowed laboratory, including a 16-node Beowulf cluster for simulations and state-of-the-art EDA tools Well-endowed laboratory, including a 16-node Beowulf cluster for simulations and state-of-the-art EDA tools

23 Model for Collaboration Feature set Feature set ‘Beyond the envelope’ research ‘Beyond the envelope’ research Pre-competitive : several industrial partners Pre-competitive : several industrial partners industrial support : funding, equipment, body swap,…. industrial support : funding, equipment, body swap,…. Successful Examples Successful Examples Silicon Structures (Caltech ) Silicon Structures (Caltech ) Berkeley Wireless Research Center ( ) Berkeley Wireless Research Center ( ) MIT Media Lab ( ) MIT Media Lab ( )

24 Road Map Creation of the “Edinburgh InfoLab” to research architectures for future P2P systems Creation of the “Edinburgh InfoLab” to research architectures for future P2P systems 5 founding industrial partners/subscribers 5 founding industrial partners/subscribers 30 PhD students in the steady state 30 PhD students in the steady state Partners’ contributions: Two 4-year PhD studentships per year, cumulatively for 3 years Partners’ contributions: Two 4-year PhD studentships per year, cumulatively for 3 years Interested? Interested? More details at More details at

25 Thank You


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