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1 William Stallings Computer Organization and Architecture Chapter 6 Input/Output.

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Presentation on theme: "1 William Stallings Computer Organization and Architecture Chapter 6 Input/Output."— Presentation transcript:

1 1 William Stallings Computer Organization and Architecture Chapter 6 Input/Output

2 2 Input/Output Problems zWide variety of peripherals yDelivering different amounts of data yAt different speeds yIn different formats zAll slower than CPU and RAM zNeed I/O modules

3 3 Input/Output Module zInterface to CPU and Memory zInterface to one or more peripherals zGENERIC MODEL OF I/O DIAGRAM 6.1

4 4 External Devices zHuman readable yScreen, printer, keyboard zMachine readable yMonitoring and control zCommunication yModem yNetwork Interface Card (NIC)

5 5 I/O Module Function zControl & Timing zCPU Communication zDevice Communication zData Buffering zError Detection

6 6 I/O Steps zCPU checks I/O module device status zI/O module returns status zIf ready, CPU requests data transfer zI/O module gets data from device zI/O module transfers data to CPU zVariations for output, DMA, etc.

7 7 I/O Module Diagram Data Register Status/Control Register External Device Interface Logic External Device Interface Logic Input Output Logic Data Lines Address Lines Data Lines Data Status Control Data Status Control Systems Bus Interface External Device Interface

8 8 I/O Module Decisions zHide or reveal device properties to CPU zSupport multiple or single device zControl device functions or leave for CPU zAlso O/S decisions ye.g. Unix treats everything it can as a file

9 9 Input Output Techniques zProgrammed zInterrupt driven zDirect Memory Access (DMA)

10 10 Programmed I/O zCPU has direct control over I/O ySensing status yRead/write commands yTransferring data zCPU waits for I/O module to complete operation zWastes CPU time

11 11 Programmed I/O - detail zCPU requests I/O operation zI/O module performs operation zI/O module sets status bits zCPU checks status bits periodically zI/O module does not inform CPU directly zI/O module does not interrupt CPU zCPU may wait or come back later

12 12 I/O Commands zCPU issues address yIdentifies module (& device if >1 per module) zCPU issues command yControl - telling module what to do xe.g. spin up disk yTest - check status xe.g. power? Error? yRead/Write xModule transfers data via buffer from/to device

13 13 Addressing I/O Devices zUnder programmed I/O data transfer is very like memory access (CPU viewpoint) zEach device given unique identifier zCPU commands contain identifier (address)

14 14 I/O Mapping zMemory mapped I/O yDevices and memory share an address space yI/O looks just like memory read/write yNo special commands for I/O xLarge selection of memory access commands available zIsolated I/O ySeparate address spaces yNeed I/O or memory select lines ySpecial commands for I/O xLimited set

15 15 Interrupt Driven I/O zOvercomes CPU waiting zNo repeated CPU checking of device zI/O module interrupts when ready

16 16 Interrupt Driven I/O Basic Operation zCPU issues read command zI/O module gets data from peripheral whilst CPU does other work zI/O module interrupts CPU zCPU requests data zI/O module transfers data

17 17 CPU Viewpoint zIssue read command zDo other work zCheck for interrupt at end of each instruction cycle zIf interrupted:- ySave context (registers) yProcess interrupt xFetch data & store zSee Operating Systems notes

18 18 Design Issues zHow do you identify the module issuing the interrupt? zHow do you deal with multiple interrupts? yi.e. an interrupt handler being interrupted

19 19 Identifying Interrupting Module (1) zDifferent line for each module yPC yLimits number of devices zSoftware poll yCPU asks each module in turn ySlow

20 20 Identifying Interrupting Module (2) zDaisy Chain or Hardware poll yInterrupt Acknowledge sent down a chain yModule responsible places vector on bus yCPU uses vector to identify handler routine zBus Master yModule must claim the bus before it can raise interrupt ye.g. PCI & SCSI

21 21 Multiple Interrupts zEach interrupt line has a priority zHigher priority lines can interrupt lower priority lines zIf bus mastering only current master can interrupt

22 22 Example - PC Bus z80x86 has one interrupt line z8086 based systems use one 8259A interrupt controller z8259A has 8 interrupt lines

23 23 Sequence of Events z8259A accepts interrupts z8259A determines priority z8259A signals 8086 (raises INTR line) zCPU Acknowledges z8259A puts correct vector on data bus zCPU processes interrupt

24 24 PC Interrupt Layout 8086 INTR 8259A IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

25 25 ISA Bus Interrupt System zISA bus chains two 8259As together zLink is via interrupt 2 zGives 15 lines y16 lines less one for link zIRQ 9 is used to re-route anything trying to use IRQ 2 yBackwards compatibility zIncorporated in chip set

26 26 ISA Interrupt Layout 80x86 INTR 8259A IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 8259A IRQ0 (8) IRQ1 (9) IRQ2 (10) IRQ3 (11) IRQ4 (12) IRQ5 (13) IRQ6 (14) IRQ7 (15) (IRQ 2)

27 27 Foreground Reading zhttp://www.pcguide.com/ref/mbsys/res/irq/func.htm zIn fact look at

28 28 Direct Memory Access zInterrupt driven and programmed I/O require active CPU intervention yTransfer rate is limited yCPU is tied up zDMA is the answer

29 29 DMA Function zAdditional Module (hardware) on bus zDMA controller takes over from CPU for I/O

30 30 DMA Operation zCPU tells DMA controller:- yRead/Write yDevice address yStarting address of memory block for data yAmount of data to be transferred zCPU carries on with other work zDMA controller deals with transfer zDMA controller sends interrupt when finished

31 31 DMA Transfer Cycle Stealing zDMA controller takes over bus for a cycle zTransfer of one word of data zNot an interrupt yCPU does not switch context zCPU suspended just before it accesses bus yi.e. before an operand or data fetch or a data write zSlows down CPU but not as much as CPU doing transfer

32 32 Aside zWhat effect does caching memory have on DMA? zHint: how much are the system buses available?

33 33 DMA Configurations (1) zSingle Bus, Detached DMA controller zEach transfer uses bus twice yI/O to DMA then DMA to memory zCPU is suspended twice CPU DMA Controller I/O Device I/O Device Main Memory

34 34 DMA Configurations (2) zSingle Bus, Integrated DMA controller zController may support >1 device zEach transfer uses bus once yDMA to memory zCPU is suspended once CPU DMA Controller I/O Device I/O Device Main Memory DMA Controller I/O Device

35 35 DMA Configurations (3) zSeparate I/O Bus zBus supports all DMA enabled devices zEach transfer uses bus once yDMA to memory zCPU is suspended once CPU DMA Controller I/O Device I/O Device Main Memory I/O Device I/O Device

36 36 I/O Channels zI/O devices getting more sophisticated ze.g. 3D graphics cards zCPU instructs I/O controller to do transfer zI/O controller does entire transfer zImproves speed yTakes load off CPU yDedicated processor is faster

37 37 Interfacing zConnecting devices together zBit of wire? zDedicated processor/memory/buses? zE.g. SCSI, FireWire

38 38 Small Computer Systems Interface (SCSI) zParallel interface z8, 16, 32 bit data lines zDaisy chained zDevices are independent zDevices can communicate with each other as well as host

39 39 SCSI - 1 zEarly 1980s z8 bit z5MHz zData rate 5MBytes.s -1 zSeven devices yEight including host interface

40 40 SCSI - 2 z1991 z16 and 32 bit z10MHz zData rate 20 or 40 Mbytes.s -1 z(Check out Ultra/Wide SCSI)

41 41 SCSI Signaling (1) zBetween initiator and target yUsually host & device zBus free? (c.f. Ethernet) zArbitration - take control of bus (c.f. PCI) zSelect target zReselection yAllows reconnection after suspension ye.g. if request takes time to execute, bus can be released

42 42 SCSI Signaling (2) zCommand - target requesting from initiator zData request zStatus request zMessage request (both ways)

43 43 SCSI Bus Phases Arbitration Bus free (Re)Selection Command, Data, Status, Message Reset

44 44 SCSI Timing Diagram

45 45 Configuring SCSI zBus must be terminated at each end yUsually one end is host adapter yPlug in terminator or switch(es) zSCSI Id must be set yJumpers or switches yUnique on chain y0 (zero) for boot device yHigher number is higher priority in arbitration

46 46 IEEE 1394 FireWire zHigh performance serial bus zFast zLow cost zEasy to implement zAlso being used in digital cameras, VCRs and TV

47 47 FireWire Configuration zDaisy chain zUp to 63 devices on single port yReally 64 of which one is the interface itself zUp to 1022 buses can be connected with bridges zAutomatic configuration zNo bus terminators zMay be tree structure

48 48 FireWire v SCSI

49 49 FireWire 3 Layer Stack zPhysical yTransmission medium, electrical and signaling characteristics zLink yTransmission of data in packets zTransaction yRequest-response protocol

50 50 FireWire - Physical Layer zData rates from 25 to 400Mbps zTwo forms of arbitration yBased on tree structure yRoot acts as arbiter yFirst come first served yNatural priority controls simultaneous requests xi.e. who is nearest to root yFair arbitration yUrgent arbitration

51 51 FireWire - Link Layer zTwo transmission types yAsynchronous xVariable amount of data and several bytes of transaction data transferred as a packet xTo explicit address xAcknowledgement returned yIsochronous xVariable amount of data in sequence of fixed size packets at regular intervals xSimplified addressing xNo acknowledgement

52 52 FireWire Subactions

53 53 Foreground Reading zCheck out Universal Serial Bus (USB) zCompare with other communication standards e.g. Ethernet


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