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1 IKI20210 Pengantar Organisasi Komputer Kuliah Minggu ke-5c: Prosesor 11 Oktober 2002 Bobby Nazief Johny Moningka

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Presentation on theme: "1 IKI20210 Pengantar Organisasi Komputer Kuliah Minggu ke-5c: Prosesor 11 Oktober 2002 Bobby Nazief Johny Moningka"— Presentation transcript:

1 1 IKI20210 Pengantar Organisasi Komputer Kuliah Minggu ke-5c: Prosesor 11 Oktober 2002 Bobby Nazief Johny Moningka bahan kuliah: Sumber: 1. Hamacher. Computer Organization, ed Materi kuliah CS152, th. 1997, UCB.

2 2 Pengendalian Eksekusi Instruksi: Microprogrammed Control

3 3 Microprogramming °Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global Microprogramming: -- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note: IBM 360 Series first to distinguish between architecture & organization Same instruction set across wide range of implementations, each with different cost/performance

4 4 Microinstructions STEPCONTROL SIGNALS 1.PC out, MAR in, Read, Clear Y, Carry-in to ALU, Add, Z in 2.Z out, PC in, WMFC 3.MDR out, IR in 4.R3 out, MAR in, Read 5.R1 out, Y in, WMFC 6.MDR out, Add, Z in 7.Z out, R1 in, End IR in PC in PC out MAR in MDR out Y in R1 in R1 out R3 out Z in Z out Clear Y Carry-in Add Read WMFC End

5 5 Organisasi Microprogrammed Control Unit IR Starting Address Generator ClockμPC Control Store Control Word

6 6 Organisasi μProgrammed Control Unit: Branching IR Starting Address Generator ClockμPC Control Store Control Word Status Flags Condition Codes

7 7 Format Microinstruction °Figure 3.19

8 8 Microprogram Sequencing °Figure 3.22

9 9 “Macroinstruction” Interpretation Main Memory execution unit control memory CPU ADD SUB AND DATA User program plus Data this can change! AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) one of these is mapped into one of these

10 10 Control: Hardware vs. Microprogrammed °Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial RepresentationFinite State Diagram Microprogram Sequencing ControlExplicit Next State Microprogram counter Function + Dispatch ROMs Logic RepresentationLogic EquationsTruth Tables Implementation TechniquePLAROM “hardwired control”“microprogrammed control”

11 11 Peningkatan Kinerja Prosesor

12 12 CPU time= Seconds= Instructions x Cycles x Seconds Program Program Instruction Cycle CPU time= Seconds= Instructions x Cycles x Seconds Program Program Instruction Cycle Faktor-faktor Penentu Kinerja Prosesor instr countCPIclock rate Program X Compiler X X Instr. Set X X Organization X X Technology X

13 13 Organisasi Prosesor (Multiple-bus) MDR MAR PC TEMP Register File IR Instruction Decoder ALU A B C Data lines Address lines Memory Bus Add R1,R2,R3 ;R1  R2+R3

14 14 Bandingkan dengan Organisasi Single-bus Add R1,R2,R3 ;R1  R2+R3 Y Z MDR MAR PC TEMP R3 R1 IR Instruction Decoder ALU R2

15 15 Beberapa Teknik Peningkatan Kinerja Prosesor °Pre-fetching: instruksi berikutnya (i+1) di-fetch pada waktu pengeksekusian instruksi (i) Perlu teknik “Branch Prediction” °Pipelining: eksekusi instruksi dipecah kedalam tahap-tahap yang dapat dilakukan secara “overlap” Fetch Instruksi Decode Instruksi Baca Operand (dari register asal) Lakukan Operasi Tulis Hasil (ke register tujuan) °On-chip Cache: mempercepat akses data dari/ke memori

16 16 Arsitektur Intel P6 (Pentium Pro)

17 17 Contoh: Komputer Berbasis SPARCstation20 °TI SuperSPARC tm TMS390Z50 in Sun SPARCstation20 Floating-point Unit Integer Unit Inst Cache Ref MMU Data Cache Store Buffer Bus Interface SuperSPARC L2 $ CC MBus Module MBus L64852 MBus control M-S Adapter SBus DRAM Controller SBus DMA SCSI Ethernet STDIO serial kbd mouse audio RTC Boot PROM Floppy SBus Cards


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