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Ni.com FPGAs for HIL and Engine Simulation. 2 ni.com Field-Programmable Gate Array (FPGA) Configurable Logic Blocks (CLBs) Implement logic using flip-flops.

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Presentation on theme: "Ni.com FPGAs for HIL and Engine Simulation. 2 ni.com Field-Programmable Gate Array (FPGA) Configurable Logic Blocks (CLBs) Implement logic using flip-flops."— Presentation transcript:

1 ni.com FPGAs for HIL and Engine Simulation

2 2 ni.com Field-Programmable Gate Array (FPGA) Configurable Logic Blocks (CLBs) Implement logic using flip-flops and LUTs Multipliers and DSPs Implement signal processing using multiplier and multiplier-accumulate circuitry Memory Blocks Store data sets or values in user defined RAM Programmable Interconnects Route signals through the FPGA matrix I/O Blocks Directly access digital and analog I/O

3 3 ni.com FPGAs - Why Are They Useful? Hard determinism – Realistic simulation timing, local intelligence Off-load processing – Achieve real-time performance with more complex simulations Custom Hardware – Create custom H/W instruments Reconfigurable hardware personalities – Adapt to multiple UUT types and changing UUT interfaces Industry standard technology – Off the shelf chips used for specific applications get COTS benefits like Moore’s Law

4 4 ni.com FPGAs in HIL Test Systems IO UUT Signal Conditioning µP Test Application

5 5 ni.com µP IO UUT Signal Conditioning FPGA Personality Test Application FPGAs in HIL Test Systems

6 6 ni.com FPGAs in HIL Test Systems µP IO UUT Signal Conditioning FPGA Personality Test Application NI Reconfigurable I/O (RIO) Platform Hardware I/O Interfaces Test Application Interfaces

7 7 ni.com Mechanical Systems – Engine Sensor Simulation µP I/O UUT FPGA (Engine Simulation) FPGA (Engine Simulation) Crank RPMs

8 8 ni.com Free Engine Simulation Toolkit Fully featured for Engine Control Unit (ECU) testing FPGA-based sensor simulation and measurement for ultra-fast pin-to-pin response time & lifetime upgradability Seamless integration with NI FPGA hardware and NI VeriStand Scalable design for simple to complex ECU testing Suitable for open loop or closed loop Open source architecture customizable with LabVIEW FPGA Supports any NI FPGA device Deploy with NI VeriStand 2013 or later Design with LabVIEW 2013 or later

9 Digital Pattern Generation Analog Data Replay ECU Event Timing Capture Knock Sensor Simulation Directional Sensor Simulation ECU Event Waveform Capture Digital Pattern Generation Analog Data Replay ECU Event Timing Capture Knock Sensor Simulation Directional Sensor Simulation ECU Event Waveform Capture Engine Simulation Toolkit Building Blocks Angle Processing Unit (APU) FPGA CPU Digital Pattern Generation (i.e. Hall) Digital Pattern Generation (i.e. Hall) Analog Replay (i.e. VR) ECU Event Timing Capture (Inject & Ignite) ECU Event Timing Capture (Inject & Ignite) Knock Sensor Simulation Directional Sensor Simulation ECU Event Waveform Capture Speed, Crank Angle, Cycle Angle

10 10 ni.com Engine Simulation Toolkit Roadmap ItemOld AES Library Angle Processing Unit (APU) 2 and 4 stroke engines Digital Pattern Generation N-M Teeth Generation Custom Edges Generation Analog Replay Play back any file by angle ECU Event Measurement Digital input timing capture of single event per cycle Knock Sensor N/A Directional Speed Sensor N/A FPGA space utilization Baseline

11 11 ni.com Engine Simulation Toolkit Roadmap ItemOld AES LibraryEngine Simulation Toolkit Angle Processing Unit (APU) 2 and 4 stroke enginesImproved usability Digital Pattern Generation N-M Teeth Generation Custom Edges Generation Improved usability Analog Replay Play back any file by angleImproved usability ECU Event Measurement Digital input timing capture of single event per cycle Windowing, multi-event per cycle, error detection, & improved usability Knock Sensor N/A Pseudorandom, amplitude & probability per cylinder. Directional Speed Sensor N/A Different forward/reverse digital pulse width triggered at tooth centers FPGA space utilization Baseline3x Reduction

12 12 ni.com ItemOld AES LibraryEngine Simulation Toolkit Q Angle Processing Unit (APU) 2 and 4 stroke enginesImproved usability Digital Pattern Generation N-M Teeth Generation Custom Edges Generation Improved usability Analog Replay Play back any file by angleImproved usability ECU Event Measurement Digital input timing capture of single event per cycle Windowing, multi-event per cycle, error detection, & improved usability Analog input thresholding and waveform capture Knock Sensor N/A Pseudorandom, amplitude & probability per cylinder. Directional Speed Sensor N/A Different forward/reverse digital pulse width triggered at tooth centers FPGA space utilization Baseline3x Reduction Engine Simulation Toolkit Roadmap

13 13 ni.com Space and performance comparison 7854R PXIe 8130 PXIe 1082 AES Library 1 APU 1 N-M generation 4 Fully Custom generation 1 Analog Replay 12 Event Capture Engine Simulation Toolkit 1 APU 5 Digital Pattern Generation 1 Analog Replay 12 Event Capture Slices6,703 of 17,280 (38.8%)3,159 of 17,280 (18.3%) Registers14,882 of 69,120 (21.5%)5,912 of 69,120 (8.6%) LUTs19,702 of 69,120 (28.5%)8,239 of 69,120 (11.9%) DSP24 of 64 (37.5%)2 of 64 (3.1%) BRAM21 of 128 (37.5%)13 of 128 (10.2%) 40 Mhz Max Compile time37 minutes21.7 minutes RT Loop Duration 305 to 335 uS138 to 186 uS w/ RIO to 165 uS w/ RIO 15.0

14 14 ni.com Reconfigurable I/O Interfaces µP I/O FPGA V6 ECU V8 ECU Multiple UUT types Evolution of UUT interface

15 15 ni.com NI VeriStand System Explorer

16 ni.com Analog Replay

17 17 ni.com Analog Replay Configuration

18 18 ni.com Analog Replay: Voltage Scaling Configuration

19 19 ni.com Example FPGA: APU + 1 Analog Replay Load Look Up Table APU Play Look Up Table

20 20 ni.com Example FPGA : APU + 2 Analog Replay

21 ni.com Digital Pattern Generation

22 22 ni.com Digital Pattern Generation of Two Cams and a Crank

23 23 ni.com Digital Pattern Generation Design

24 24 ni.com Digital Pattern Generation supports complex patterns easily

25 25 ni.com Example FPGA: 2 Digital Pattern Generations

26 ni.com Knock Sensor Simulation

27 27 ni.com Knock Sensor Simulation Configuration

28 28 ni.com Example FPGA: Knock Sensor Simulation Loop

29 29 ni.com Knock Sensor with 4 Cylinders (Probably had been set to 100% with 4 different amplitudes)

30 ni.com Directional Speed Sensor Simulation

31 31 ni.com Directional Speed Sensor Generates pulses of different widths, depending on forward (Tf) or reverse (Tr) rotation, when passing tooth centers Pulse slightly delayed from center by variable microseconds (Td) Crank Directional sensor: forward Directional sensor: reverse

32 32 ni.com Directional Speed Sensor

33 33 ni.com Example FPGA: 1 Directional Speed Sensor Load Tooth Centers Look Up Table From APU

34 ni.com ECU Event Capture

35 35 ni.com Example FPGA : Typical MPI Injection Measurement (1 x Cylinder) Event measurement block settings: Angle Max (degrees) Angle Min (degrees) Active High (Boolean) Time based ‘stuck active’ timeout (milliseconds) Event capture block outputs: Event Present (Boolean) Start Angle (degrees) End Angle (degrees) Duration (milliseconds) Digital Input Event measurement block outputs: Stuck active (Boolean) Window all active (Boolean) Window orphan start edge (Boolean) Window orphan end edge (Boolean)

36 36 ni.com Example FPGA : Typical GDI or Diesel Injection Measurement (1 x Cylinder)

37 37 ni.com Example FPGA : Typical GDI or Diesel Injection Measurement (2 x Cylinder)

38 38 ni.com Example FPGA : Customize Windowing Per Event

39 39 ni.com ECU Event Capture Configuration

40 40 ni.com ECU Event Capture Configuration

41 41 ni.com Generation and measurement of two events neither wrapping 0 and window does not wrap 0

42 42 ni.com Generation of one event wrapping zero and one not wrapping zero; window wraps zero and measures both

43 43 ni.com Start of a full cycle event within window, causing an orphan start edge and a stuck active flag

44 44 ni.com End of full cycle event within next window, causing an orphan end edge

45 45 ni.com Future* FPGA : Typical GDI or Diesel Injection Timing & Waveform Measurement Analog InputThresholding Timing Measurement and Capture Waveform capture *Q4 2014

46 46 ni.com Case Study Application Creating a flexible HIL test system with I/O interfaces that require custom timing and synchronization schemes not easily implementable with traditional hardware. NI Products LabVIEW FPGA Module, PXI, and Reconfigurable I/O (RIO) hardware "With LabVIEW FPGA and RIO hardware we were able to quickly and efficiently design custom analog and digital interfaces for our HIL test system.” – Roy Kranz, Wineman Technology Inc. Key Benefit Gaining the ability to efficiently create custom hardware interfaces that can be reconfigured after deployment to adapt to different ECU types and changes to ECU interfaces.

47 47 ni.com Summary FPGA-based I/O interfaces are used to expand the capabilities and performance of HIL test systems. Hard determinism – Realistic simulation timing and local intelligence with 25 ns resolution Off-load processing – Achieve real-time performance with more complex simulations Custom Hardware – Create custom H/W instruments Industry standard technology – Off the shelf chips used for specific applications get COTS benefits Reconfigurable hardware personalities – Test multiple UUT types and adapt to changes in UUT interfaces without changing hardware


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