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MICRO-KERNELS New Generation Innovation. The contents Traditional OS view & its problems. Micro-kernel : introduction to concept. First generation micro-kernels.

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Presentation on theme: "MICRO-KERNELS New Generation Innovation. The contents Traditional OS view & its problems. Micro-kernel : introduction to concept. First generation micro-kernels."— Presentation transcript:

1 MICRO-KERNELS New Generation Innovation

2 The contents Traditional OS view & its problems. Micro-kernel : introduction to concept. First generation micro-kernels. Obvious advantages. Some Implementation problems. Second generation micro-kernels. L4 Kernel. Exo-Kernel. SPIN OS.

3 The contents (contd…)

4 Traditional OS view Prerequisite component : TCB Kernel is OS part of TCB. Kernel is monolithic. (includes sched, fs, n/w, mm, dd etc..) Kernel abstracts & protects system resources. (PM  VM, DISK  FILES, CPU  processes)

5 Advantages of this kernel Portable interface to underlying machine. Large, generic, default functionality base. (Applications need not worry about device drivers or memory management policies ) Provides protection. (kernel controls use of all resources.)

6 Serious disadvantages Huge kernel size. ONLY privileged ones can access and manage system resources. (kernel itself, or servers.) Applications are “forced” to use implementation of these privileged ones. This generic implementation is bound to be imperfect for specific application needs. Why ? Because of typical performance/cost tradeoffs.

7 What to do ? 1 st generation micro-kernels. Remove un-wanted components. Implement all services as external servers. (fs, mm, dd, n/w etc …) All servers run in user mode.

8 What are the benefits ? Smaller kernel. (hand-held devices ?) OS is more modular, flexible, extensible and customizable. More than one implementation possible of various services. (can co-exist). May even run concurrently, if needed. Easy crash recovery (only servers crash)

9 Minimal** implementation primitives required. Assumptions Support for un-trustworthy applications Page based virtual memory implementation by h/w. Issues for such a system : Protection scheme. Guarantee of Independence. Interrupt handling. IPC

10 Implementation Two concepts solves all above problems – the concept of Address spaces & threads. Traditional address space : mapping associating virtual page  physical page. New : Initially, only 1 global address space, representing the physical memory. New address spaces can be recursively constructed outside the kernel.

11 Address space construction For this support, 3 operations provided in the micro-kernel. GRANT, MAP, FLUSH. Using these kernel provided primitives, memory management and paging schemes can be implemented outside kernel.

12 Definitions of Primitives GRANT Owner can grant “its” pages to anyone else, provided receiver agrees to take it. Granted page removed from granter’s addr space. MAP Owner can map “its” pages to anyone else’s address space, provided receiver agrees for it. Page can now be accessed in both addr spaces.

13 Definitions contd… FLUSH Owner can flush any of “its” pages. Flushed pages remain accessible to owner. But once flushed, the page is removed from any other address space (non-owner), where it may possibly have been mapped. Note that owner do NOT need explicit permission from other “mappers” before flushing. Idea is that anyway page belongs to self only, and users of this page “had already accepted this”.

14 Where are these reqd.? MAP & FLUSH used for implementing memory managers and pagers on top of micro-kernel. GRANT only used in special circumstances When page mappings should be passed through a controlling sub-system without burdening the controller’s address space. (See figure below for explanations.)

15 Explaining primitives User A User N Pager - F Pager f1 (fs) Pager – f2 (fs) Standard pager grant map disk

16 Threads concept Micro-kernel support the notion of threads at the lowest level of abstraction, within the kernel. A thread t is an activity executing inside an address-space as. t is characterized by registers, stack-ptr, state information :: (which as it belongs to)

17 How this satisfies everything ? Protection & Independence are obvious due to very structure of separate AS concept. IPC can be realized by transferring messages between kernel “threads”. Note that this forms the basis of communication and is used for implementing operations like map and grant. Interrupts are treated as IPC messages. Hardware is regarded as set of threads.

18 Questions / thoughts ? How can this model help provide “controlled” access? think of ACLs. !! Provide “access rights” concept on pages. Map/Grant can “copy”/”move” source’s rights. Flushing can “revoke” permissions.

19 What can be built on top ? Memory manager (stacked ?) Pager – can implement virtual mem., resident memory for device drivers etc. Device drivers. They will directly access hardware I/O ports which are mapped into “its” address space. Messages are recvd from h/w (interrupts) through IPC. Secondary cache / TLB handlers. R-IPC (RPC) UNIX server ( system calls.)

20 1 st generation problems Performance was terrible. IPC costs (200 #sec vs. 40 #sec) (All user level servers would be accessed by RPC mechanism.) High MCPI costs (memory cycle per inst) Even upto.25 CPI (additional). !! Non-Portability. WHY ?

21 MCPI problems due to … Increased cache misses due to ; – Worse locality properties of the combined micro-kernel OS code. – System self-interference, incorrectly invalidating cache lines, due to more modularity of the OS. – More inter-module copying due to the higher modularity of the OS.

22 Why Non-Portability ? Problems with Portable kernels :- – Can not take advantage of specific hardware – Can not take precautions to circumvent or avoid perfromance problems of specific hardware – Additional layer ( abstraction of hardware) costs performance. WE SHOULD ACCEPT THAT micro- kernel is going to be h/w dependent.

23 Example : 486 Vs Pentium 486Pentium TLB entries, ways 3232i + 64d Cache size Line, thru 8K 16B, through 8Ki + 8Kd 32B, back Fast instr. Segmt reg. 1 cycle 9 cycles 0.5-1 cycle 3 cycles.

24 Differences : Pentium micro-kernel will use segment registers for implementing user address space 486 will have to use conventional hardware- address-space switch because of expensive segment register operations. This is Due to points 2 &3 in table above.

25 Conclusions Micro-kernel design offers great flexibility and innovation in way world percieves OS. Micro-kernels must be developed per- processor, but performance achieved is probably worth the effort. More work needed in this area. STEP TOWARDS 2 nd generation micro- kernels.

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