2 Doing what we said we would do… or Why customers come to us first... We are now offering our customers a new perspective on how to find our parts, which is by application. This initiative to expand our applications and design support area is just one of the many ways why customers will come to us first.An example of a design engineer working for a computer company who needs ON devices for Multiphase Controllers. He/she sees our computing market that we play in and selects the Desktop PC SMPS to view our devices.Emphasize the fact that the design engineer is trying to get back on schedule and needs a quick solution to his/her problem.Doing what we said we would do…orWhy customers come to us first...
3 Design Support Button…click here The design engineer sees the Desktop PC block diagram and locates the block for Multiphase Controllers. Below the block diagram is the list of all our devices for the Desktop PC, but our design engineer only wants to see our Multiphase Controllers, so he/she can now click on the Multiphase Controllers block to view just those devices.Design Support Button…click here
4 Design Support Button…click here The design engineer now sees that ON offers true design support that he/she can go to for assistance. Real time customer service. The design engineer will then click on the button to take him/her to the Virtual Application Lab at ON’s headquarters in Phoenix.Design Support Button…click here
5 Stability in High Speed LDO Regulators An overview of the design relating to low drop out (LDO) regulators.Design guidelines given for the selection of components based on performance and stability requirements.Typical questions that generally need or get asked:What are my input and output requirements?Do I have transient response and magnitude requirements?Can I use a regulator or do I need a controller?What do I need for output capacitors?If my regulator is oscillating, what do I change to stop it?My regulator response is slow, so how do I speed it up without causing it to oscillate?The following slides introduce the different componentsand block diagrams for LDO regulators.Welcome to the presentation about designing for stability and response in LDO regulators.LDO regulators are becoming the main stream for linear voltage regulators due to their speed and capability of having a small difference between the input and output voltages, thus the name low drop out.But because they are typically designed for fast response, they also can become unstable if the components used in the design are not selected properly.During this presentation, the factors governing the stability in LDO regulator designs are presented along with some basic design guidelines to follow to create a stable design. Transient response can also be optimized at the same time the stability design is being made.[pronounce LDO as letters, as in ”L-D-O"]
6 Example LDO Controller Block Diagram Block diagram showing dual LDO controller.Startup, Over current, and Shutdown functions.Band Gap reference for setting DC output voltage.Error Amplifier for controlling external N-channel FET.Second channel FET turn on for shorting input to output.This is a block diagram of a dual LDO controller. Controllers will have the output driver device separate whereas regulators have the driver internal.The LDO controller contains an input reference voltage, shown here as a band gap reference. This reference feeds into one of the inputs of an error amp with the output of the error amp driving the output driver.The output voltage is then fed back to the other input of the error amp. Sometimes a divider will be placed between the output voltage and the error amp input to produce an output voltage higher than the reference voltage.Other features are usually included such as start up, over current, over voltage lock out, thermal shutdown, and enable function.MC33567 Dual LDO Controller
7 LDO Regulator Block Diagram Error AmplifierFeedback DividerOutput Driver & LoadA(s)-+ReferenceInputSupplyOutputDriverLoadB(s)C(s)Shown here is the basic block diagram of an LDO regulator. The three main control blocks are the error amp, output driver load combination, and feedback divider. Each block has an input, output, and associated transfer function.The input to the system is the reference input voltage and the output is the supply output voltage.Details for each control block and the parameters that determine the transfer function are summarized on the following slides.
8 LDO Regulator Schematic LDO ControllerDriverLoadError AmpA schematic diagram for a typical LDO regulator is shown with the various control blocks highlighted around the components that are involved for each block.Depending on the particular devices used to build an LDO regulator, each of the components shown may be internal or external to devices. If an LDO controller is used, the driver will be external versus internal for a regulator. The voltage divider is sometimes built in if the controller or regulator is a fixed output voltage type, whereas adjustable versions will require the divider to be external.The output capacitor is shown as a resistor and capacitor in series, with the resistor being the equivalent series resistance of the capacitor being used. The load itself is modeled with an equivalent resistor.FeedbackDividerOutputCapacitorReference Input
9 Simplified Block Diagram and Transfer Function A(s)B(s)C(s)+-For stability analysis of the overall system, the transfer function from the reference input to the supply output needs to be determined. The diagram here shows a basic feedback control loop with the various block transfer functions involved.The general form of expression for the system transfer function is shown with a final form consisting of a gain factor Av, numerator N(s), and denominator D(s). The gain factor is set up by the divider and details for this will follow. The numerator determines the operating zeros of the system and the denominator determines the poles.[pronounce Av as ”a - sub v"][pronounce N(s) as ”n - of s"][pronounce D(s) as ”d - of s"]
10 Error Amplifier Detail - A(s) +- error amp open loop gain- dominant error amp pole- secondary error amp pole- error amp gain bandwidthOpen loop gain greater than 60dB (for less than 0.1% DC output error).Dominant pole usually set for device, although some devices allow adjusting via compensation pin.Gain bandwidth usually specified:Solve for gain bandwidth pole:Error amp designed to have secondary pole greater than gain bandwidth and usually NOT specified. If not, let:For stability analysis, assume frequency range:We are now going to examine the error amplifier in detail. The form of its transfer function is shown with an approximated expression used for stability analysis over the range of frequencies shown. The open loop gain is usually set within the device to produce negligible error in the dc output voltage.The open loop gain bandwidth of the error amp is a key parameter that must be known for proper design of stability in an LDO control loop. This information can be obtained from the data sheet for the device. Sometimes it is specified directly or it may be shown graphically.The other parameter of interest is the second pole of the error amp and this is usually not specified. A conservative estimate for the purpose of stability analysis is to make it equal to the gain bandwidth.[pronounce dc as letters, as in ”d-c"]
11 Feedback Divider Detail - C(s) Want to design divider for DC gain of Av and AC gain of 1.Want V1 independent on reference input, Vr.Need AC gain of 1 for frequencies greater than low frequency pole of error amp.LDO controller with fixed output voltage has divider built-in and optimized.If adding to existing internal divider, follow same guidelines.Use following design guidelines to obtain these result.Here is shown the feedback divider and its overall transfer function. It can be seen that the feedback divider output depends on the LDO output voltage and reference input voltage.It is desirable to have the transfer function C(s) be a constant factor of the LDO output voltage at dc and be unity at higher frequencies. It is also desirable to have the divider output not be a function of the reference input voltage. By doing an analysis of the transfer function and making certain restrictions on the selection of components, one can achieve these goals.The next slide shows the guidelines to follow for obtaining the desired response.[pronounce C(s) as ”c - of s"]
12 Feedback Divider Detail - C(s) - Continued Divider Design Guidelines:- output voltage (known).- reference voltage (known).- DC gain (solve for).- gain bandwidth (from error amp analysis).- error amp input capacitance (use 10pf if not specified).- first divider resistor (solve for).- second divider resistor (solve for).- divider compensation capacitor (solve for).The guidelines to use for selecting components for the feedback divider are given here as well as a brief description of what each parameter is. By using this approach, one obtains the expression for C(s) shown at the bottom.One parameter that is not always given is the input capacitance of the error amp. If this is the case, choosing a value as shown will usually work well.If you are using a device that has the divider built in, it will usually be designed to have this optimization performed. If you are attempting to add to an existing internal divider to trim the voltage on a fixed device, follow the same guidelines given above.Final solution for divider transfer function - C(s):
13 Output Driver and Load Detail - B(s) Error AmpOutputDriverTransfer function for B(s) shown mainly for reference.Too complicated to deal with directly.Will develop design guidelines combining this with other functions to develop overall closed loop transfer function.OutputCapacitorThe diagram here is representing the functional block made up of the error amp output resistance, the output driver, output capacitor, and load. The input to this section is the error amp signal and the output is the LDO output voltage.The expression for the transfer function B(s) is shown to demonstrate how each component impacts the transfer function. It is shown here for academic purposes only and does not have to be dealt with directly during design.This portion of the LDO has the most influence on determining the design stability of the system, but optimizing it can only be done by analyzing the overall system closed loop behavior. This is the next subject we will be dealing with.[pronounce B(s) as ”b - of s"]Load
14 LDO Closed Loop Transfer Function - H(s) Combining A(s), B(s), and C(s) into the expression for H(s) yields the following, which is ONLY shown for reference.The different transfer functions for each block are then substituted into the earlier expression for the overall closed loop transfer function H(s). The resulting equation illustrates the complexity involved in the overall response and is again only shown for academic reasons.The interesting thing to note is the system contains one zero and four poles. It is the location of the poles that will determine the stability and transient response for the LDO regulator.By doing an analysis of the behavior of these poles with respect to the components in the system, one can generate some guidelines that limit the poles to a critically or over damped response.[pronounce H(s) as ”h - of s"]The expression for H(s) contains 4 poles and one zero.It is far too complicated to work from directly.Stable response requires poles to be in left hand plane.Analyze pole locations in terms of circuit parameters to make poles be critically or over-damped (no gain peaking in closed loop response).
15 LDO Closed Loop Transfer Function - H(s) - Continued LDO Regulator Stability Design Guidelines:- secondary pole for open loop (solve for).- error amp second pole (known or assumed).- driver pole frequency (if driver built in, let ).- gain bandwidth (from error amp analysis).- maximum driver transconductance gain (if driver built in,then is the output impedance of the regulator).- ESR resistance of output capacitor (solve for).- output capacitor (solve for).- overall loop response time (solve for).Here are the guidelines that will generally yield a design that is stable. They are fairly straight forward to use and do not require analyzing the transfer function of the system or knowing what the poles are.A brief explanation of each of the parameters used is shown. Some insight is also given for determining some of these parameters if one is dealing with a regulator where the driver is built into the device.An expression is shown that also relates the response time of the closed loop system in terms of the parameters used for determining stability. This allows one the capability of starting with a response time requirement and working backwards to find the components necessary to produce a stable system.
16 LDO Closed Loop Stability Analysis Conclusion Following design guidelines for voltage divider and stability will yield stable LDO regulator.Design can be optimized for speed with stable operation.Little or no overshoot ringing for output transient currents.Design guidelines can be used in reverse to find error amp gain bandwidth if output capacitor and ESR given.Guidelines show designer which parameters to change to improve stability and/or loop response time for design and/or actual circuits.Guidelines help designer to select proper controller/driver for application.No need to solve for poles/zeros or graphically analyze Bode plots for unity gain phase margins.All conditional guidelines must be met for stability.Guidelines do not guarantee perfect operation due to unknown parasitics and unknowns.Still need to simulate and prototype final design.Following is a design example demonstrating use of guidelines.In summary of the guidelines, one can start out with a set of design requirements and determine the best components needed to meet these, or one can start with a set of components and determine which ones need to be changed to optimize the design.These guidelines have been successfully applied to simulations and actual circuit designs. They have also been used to analyze a design that is unstable to focus on the section of the design that needs to be corrected.It should be noted that the guidelines are just that; guides. There are several other factors such as second order parasitics and circuit board layout interference's that tend to make the design even more unstable. The guidelines presented here are conservative enough to handle most situations. This also means one may be able to obtain suitable response with components slightly outside of these limits.The guidelines are intended as a starting point but should not replace simulating and prototyping of a design to verify its performance. Following is a set of slides showing a design example with the impact changes to various components in the system can have on the overall closed loop response.
17 Example Design using Guidelines Example LDO regulator design demonstrating design guidelines.Following graphs show closed loop response for changes in circuit.Circuit at left shows components used for examples.Design guidelines valid for other circuit configurations as well.These include PFET controllers and bipolar (NPN and PNP).Output stability necessary for steady state and transient output currents.+-InternalDividerError Amp1.25V Ref1.8VOutputLoadCap1/2-MC33567LDO ControllerMTD3055NFET3.3VGnd12VAn example LDO circuit is shown here utilizing one half of a dual LDO controller that is driving an NFET power device. The controller has an internal reference of one and a quarter volts. The internal divider is set such that the output dc voltage is 1.8 volts with the divider already being optimized.The specific parameters for these two devices are shown as well. Variations in different individual components are used to generate the following information. Design guideline limits are indicated for each case with parameter values inside and outside of these limits to demonstrate the affect on the closed loop response as well as showing the validity of the guideline limits.[pronounce NFET as ”n - fet"][pronounce 1.8 as ”one point eight"]Circuit parameters:MC MHz gain bandwidth50 ohm output impedanceOptimized internal dividerMTD mhos transconductance gain2200 pf input capacitanceLoad - 0.9A (2 ohms)
19 Waveform for varying ESR of output capacitor. Rs = 30 milliohms appears optimal.(Co = 10,000uF).Changing the ESR (Rs) of the output capacitor beyond the recommended upper and lower limits tends towards instability (gain peaking).Making the ESR larger speeds up the closed loop response but may increase the magnitude of the initial transient response due to fast changes in output current.This graph represents what happens to the loop response when the equivalent series resistance, also called ESR, of the output capacitor is varied. The upper and lower design guideline limits for this component are shown for this design example. The output capacitor value was set large enough so the other guideline limits were met.When the value exceeds the limits, the closed loop response of the system starts to show gain peaking, which is the onset of instability. Even though gain peaking itself does not cause oscillation to occur, it does cause excessive ringing in the output and will increase the noise gain within the circuit. Also, when other parasitics or board layout are considered, a simple gain peak can be pushed to the point of oscillation.The other interesting point to notice is that as the ESR is increased, the bandwidth of the loop response gets larger and thus the speed of the circuit improves. This becomes apparent if one looks at the response time expression presented earlier.[pronounce ESR as letters ”e-s-r"]
20 Waveform for varying output capacitance. Co > 100uF yields same response.(Rs = 30 milliohms)For this graph, the value of the output capacitor’s capacitance is varied with the ESR of the capacitor fixed. Here there is only a lower limit on the capacitance value, with larger values yielding the same results in the loop response.Since capacitors come in different types with ESR values behaving differently for each, one needs to pick a capacitor that both meets the ESR and capacitance guideline limits. There may also be a requirement for the amplitude of the transient response, which will be explained shortly and will also impact the selection of the output capacitor.Output capacitance less than lower limit tends towards instability (gain peaking).Output capacitance greater than lower limit yield same result (choose type and value to meet ESR requirements).
21 Waveform for changing output driver - gm and Ci. MTD3055: gm = 7, Ci = 2200pfMTD3302: gm = 28, Ci = 6600pf(Co = 500uF, Rs = 30mohm)System optimized for using MTD3055.Changing output driver FET can impact loop stability (as shown for this example).If drivers need to be interchangeable, design for higher gain device (gm) and others will be stable (although loop will be slower).For this graph, we have taken the design example that has been optimized using the guidelines for one particular NFET driver and then replaced it with one that has a different set of parameters. It can be seen that a design optimized for one device may not be for another.If interchangeable drivers need to be used in a design, it is best to design for the one with higher gain. A driver with lower gain will have a longer response time, but the response will be stable. Again, one can see the influence of the driver gain on the loop response time by looking at the expression presented earlier.
22 Waveform for varying gain bandwidth of controller Designed for (Af)o = 5MHz.(MTD3055, Co=500uF, Rs=30mohm)In this graph, one can see what would happen if the gain bandwidth of the error amp were to be changed. Once again, if the parameter is changed beyond the limits that the circuit was designed for, gain peaking and eventually oscillations will occur.If one is utilizing a controller that allows compensation of the error amp, one can set the gain bandwidth for various types of output capacitors or output driver devices to obtain the best performance for the design. This type of capability allows the greatest degree of freedom for the designer to choose from a vast array of components to meet a particular design requirement.System optimized for gain bandwidth of MC33567 (5MHz).Making gain bandwidth higher tends towards instability (gain peaking).If designing with error amp compensation, can achieve stability by varying gain bandwidth.
23 Transient Response in Stable LDO regulators Transient response for changes in output currents becomes straight forward if LDO regulator closed loop response is stable.Magnitude of transient depends on rate/magnitude of change and ESR of output capacitor.Worse case is step change in output current ( ).Time for transient to return to nominal output is proportional to closed loop response time.Following is example of previous regulator design transient response for stable and “less than stable” conditions.Typical Transient ResponseWhen one looks at the transient response of a system, the closed loop response determines the response time, transient amplitude, and amount of ringing and overshoot that may occur.The more stable a design is, the less the ringing. In fact, if there is no gain peaking in the closed loop response, the amount of ringing will be negligible. If there is a large amount of gain peaking, there is be large amounts of ringing at the frequency of the gain peak.The amplitude of the initial transient is proportional to the amplitude of the transient current and the magnitude of the ESR of the output capacitor. To make this value smaller, one needs to use a smaller ESR or reduce the current change. But one must still satisfy the stability guidelines to prevent ringing and overshoot when selecting the ESR or other components in the system.The time it takes for the output to return to normal is typically five times the loop response time. This is demonstrated on the following graph.
24 Transient Response Example for Previous Design (for optimized design)(from graph)MTD3055: gm = 7, Ci = 2200pf(Co = 500uF, Rs = 30mohm)(from graph)Here, a transient response for a one amp change in output current on the previous design example is shown with variations in the gain bandwidth of the error amp.The optimized design shows a transient response typical of a critically damped system while smaller values in the gain bandwidth are stable but take longer to settle. Larger values of gain bandwidth were previously shown to exhibit gain peaking and their transient responses contain ringing.Thus, one can use the tools presented here to both optimize the stability and speed of an LDO regulator design at the same time.From graph, optimized design is critically damped.Over optimized designs slower but stable.Designs outside of guidelines tend to oscillate.Response time and transient amplitude agree with guidelines.
25 Presentation SummarySpecify design output voltage and current (steady state and transient).Follow design guidelines.Select controller best suited.Simulate and prototype circuit.Adjust components for optimal performance.To briefly summarize, design guidelines have been presented in terms of the design specifications of an LDO regulator that do not require the designer to know the poles and zero locations. There is no need to do a detailed analysis of the open loop gain and phase margins and then attempt to do a design.The guidelines give the designer some basic tools for finding components to use to meet a particular design goal. They can also be used for determining why a given design is not performing to specifications.This design approach was extended to an NFET configuration of LDO regulator, but applies to any type of LDO topology that uses a voltage feedback to an error amp controlling an output driver. A similar approach can be applied to switching power supplies, but this analysis is different enough to be covered in another presentation.Thank you.
26 MicroIntegrationTMA small-package-scale integration effort that combines multiple discrete, logic and MOS devices, which may include passive devices (resistors, capacitors, inductors).Reduces the total number of discrete & passive components thereby simplifying and or reducing:- System Cost - Procurement activity- Design Complexity - Overall size- Insertion cost - Component count- Performance inconsistencies - Solder reliability issuesTo TurnThis…Into This…
27 Customer benefits Lower manufacturing costs - Assembly line setup time - Capital equipment utilization- Equipment costsAssembled wrong part ( yield)Reduced insertion costsLower materials costs- Component costs- Board/substrate costs- Eliminate parts (eg.: shields)Improve marketplace opportunities- Performance improvement- Size reduction- Reliability improvements- Component interaction reductionReduce overhead costs- Inventory Purchase Management- Floor and shelf space- Inspection- Component Obsolescence
28 Three types of products comprise the portfolio Transient Protection ArraysFilter circuits+VccI/O 1I/O 2Drive Circuits
29 MicroIntegrationTM Markets Automotive42/14v systems, in-car entertainment systemsComputingPower Supplies, Laptop, PC/ MTB PC, Server/ MTB Server, Work Station, Main Frame, Mid-range, Storage, Disk Drives, Peripherals, Printers, Monitors, ScannersConsumerPower Supplies, Set-Top Boxes, Game Consoles, Smartcards, MP3s, DVDs, VCRs, Camcorders, Digital Cameras, Appliances, CD/ DVD Players, Handheld Game BoysWireless & PortablePower Supplies/chargers, Mobile Phones, Cordless Phones, Pagers, HH PC/PDA,Smartcards,.
49 Applications Engineer Alex LaraApplications EngineerBSEE from University of Guadalajara5 years experience in applicationsMotorola, ON SemiconductorEngineering Lab ManagerMultiple articles and application notes
50 Applications Engineering Key Activities STANDARD DESCRIPTIVE JOB TITLE FOR AN APPLICATIONS ENGINEER WITHIN THE SEMICONDUCTOR MARKET:Develop new product ideas and specifications; build hardware/software prototypes to verify new product feasibility; design and build new product evaluation and demo boards; develop SPICE macro models and perform system simulations of new products and applications; assist in evaluating and debugging new products; evaluate and build comparative matrices of Competitive products; generate product briefs, data sheets and application notes; conduct on-site design programs of new products with market leading Alpha site companies; and interface with customers and sales staff and provide technical training to Sales and FAE's.Applications Engineering Key ActivitiesDevelop new applications conceptsNew designs implementationTechnical ReportsSimulation of applications circuitsDesign-insApplications Notes DevelopmentTroubleshooting Customer Application needsSPICE simulations Development
51 ON Semiconductor Universal Serial Bus ON Semiconductor Applications EngineeringActivities for USB Port Applications
52 BackgroundUSB, or Universal Serial Bus, is a peripheral bus connectivity standard which was conceived, developed and is supported by a group of leading companies in the computer and telecommunication industries – Compaq, DEC, IBM, Intel, Microsoft, NEC and Northern Telecom. The current standard published and implemented on most of the USB devices is version 1.1, nevertheless, the good news is, USB is getting even faster, USB 2.0 promises even higher data transfer rates, up to 480 Mbps. The higher bandwidth of USB 2.0 will allow high performance peripherals, such as monitors, video conferencing cameras, next-generation printers, and faster storage devices to be easily connected to the computer via USB. The higher data rate of USB 2.0 will also open up the possibilities of new and exciting peripherals. USB 2.0 will be a significant step towards providing additional I/O bandwidth and broadening the range of peripherals that may be attached to the PC.USB 2.0 is expected to be both forward and backward compatible with USB 1.1. Existing USB peripherals will operate with no change in a USB 2.0 system. Devices such as mice, keyboards and game pads, will not require the additional performance that USB 2.0 offers and will operate as USB 1.1 devices. All USB devices are expected to co-exist in a USB 2.0 system. The higher speed of USB 2.0 will greatly broaden the range of peripherals that may be attached to the PC. This increased performance will also allow a greater number of USB devices to share the available bus bandwidth, up to the architectural limits of USB.USB 1.1 devices operate at two different levels of speed:Low speed, 1.8Mb/s equivalent to 900KHz (ENCODE, NRZI – Non Return Zero Inverter)Full speed, 12Mb/s equivalent to 6MHz (ENCODE, NRZI – Non Return Zero Inverter)USB 2.0 devices operate are compatible to operate at three different levels of speed:Low speed, 1.8Mb/s equivalent to 900KHz (ENCODE, NRZI – Non Return Zero Inverter)Full speed, 12Mb/s equivalent to 6MHz (ENCODE, NRZI – Non Return Zero Inverter)High speed, 480Mb/s equivalent to 240MHz (ENCODE, NRZI – Non Return Zero Inverter)
53 Host PC-USB Hub Connection USB ConnectivityUSB allows for multiple peripheral connectivity with one (1) Host 1 PC.Host PC-USB Hub ConnectionPDAsCellPhonesD. CamerasAdd other HUBsScannersPrinters
54 USB Opportunities Areas 1) ESD Protection and surge protectionDevices must comply with the IECComply with Telcordia (formerly Bellcore) GR1089on Surge 8x20usec waveformUSB 2.0 now requires Transmission Speeds up to480Mbits/sec (240MHz), that forces to get lowercapacitances (<5pF)USB Device/Circuit/ComponentProtection2) Power Management5V – 3.3V RegulatorsFeaturesPower switch (pending to research)USB Power Management forHost and Peripherals3) EMI Filtering / Termination – DetectionPi Filters (RC), T Filters (LC)Pull up & Pull down resistors for speed detection(Rpu, Rpd)Impedance matching resistors (Zhsdrv)USB Signal Integrity
55 USB ESD Applications Considerations for the USB ESD and TVS Protection IEC Contact and Air Discharge compliance for ESDProtection.Obtaining the lowest insertion loss in the transmission line over aspecific operating bandwidth.Lower capacitances (less than 5pF) to support USB 2.0transmission speeds up to 480Mbits/sec (240MHz).[example… ESD/TVS from connection your PDA to your computer]
56 USB ESD Applications (cont’d) Typical USB Application HOSTPCD. CamerasPDAsPrintersScannersetc.Dual USB portprotectionSingle USBport protection
57 USB ESD Applications (cont’d) Compliance with IEC 61000–4–2, ESD International StandardThis International Standard relates to the immunity requirements and test methods for electrical and electronic equipment subjected to static electricity discharges, from operators directly, and to adjacent objects. It additionally defines ranges of test levels which relate to different environmental and installation conditions and establishes test procedures. The object of this standard is to establish a common and reproducible basis for evaluating the performance of electrical and electronic equipment when subjected to electrostatic discharges. In addition, it includes electrostatic discharges which may occur from personnel to objects near vital equipment.IEC Test LevelsThis figure shows a real8KV contact waveform takenfrom the ESD generator.This figure shows how the TVS clamps the ESD condition from 8KV to 8.7V, this is the way in which protection against ESD conditions is achieved by using TVS
58 USB ESD Applications (cont’d) Low capacitance (less than 5pf) for High speed I/O Data lines (USB 2.0)“Low capacitance (< 5.0 pf)” is one of the most important characteristics that any device intended to be used in USB applications must have in order to minimize the signal attenuation at high speed data rate (480 Mbs, USB 2.0). This characteristic is critical, otherwise, the functionality of the USB system could be affected dramatically during high speed operation. Actually, the USB2.0 spec establishes that the capacitance between I/O data lines lines must no be higher than 5pf.Theoretical principle used to predict the capacitance between I/O lines for the NUP4201DR2 deviceSimplified Junctioncapacitance ModelJunction capacitance ModelReal Lab measurementsThe total devices characterized showedan average capacitance value of around4.45 pf between I/O lines whichcomplies with the USB 2.0 specification(5.0 pf maximum) and reflects the resultsobtained from the pspice model.C=4.52pf
59 USB EMI Filtering/Termination EMI Filtering for USB 2.0 Applications.For USB 2.0 applications, the usage of common mode choke inductors is very common for EMI filtering purposes since no extra capacitance is added between the I/O data lines.UpstreamDownstreamCommon mode chokeinductors
60 USB EMI Filtering/Termination EMI Filtering for USB 2.0 Applications.The equivalent PSPICE circuit for a TDK Choke model ACM P is shown below and also, its configurations for common and differential mode operation:Common ModeDifferential Mode
61 USB EMI Filtering/Termination EMI Filtering for USB 2.0 Applications.Common and Differential mode response of the TDK Choke model ACM P:Common Mode.In common mode operation, the Chokewill have very high attenuation and willnot allow the noise to go into the system. As shown in the graph (Common Mode), it starts havinghigh attenuation (-10dB or higher) when the frequency is around 50MHz.shows a high loss characteristics.Differential Mode.In differential mode operation, the choke will not have high attenuation unless the noise signal is very high frequency (5GHz or higher). As shown in the graph, it starts having high attenuation (-10dB or higher) when the frequency is around 5GHz.
62 USB EMI Filtering/Termination EMI Filtering for USB 2.0 Applications.V1= USB 2.0 signal applied(240MHz)V2 = Noise signal(5GHz)TDK ChokeFiltering response(Differential mode)
63 USB EMI Filtering/Termination EMI Filtering for USB 2.0 Applications.V1= USB 2.0 signal applied(240MHz)V2 = Noise signal(5GHz)LC Filter,Filtering response(Differential mode)
64 CONCLUSION:Applications Engineers are key in the definition and understanding of the guide lines for New Products Development.Applications Engineers are key to increase the business of the companies because most of the time they represent an added value for the customers which allows to create a relation-ship between the company and the designers, thereby, creation of new business opportunities.Applications Engineers are key to promote the companies’ products by educating the sales department, supporting trade-shows and developing demo-kits.Applications Engineers are key to win design-ins because they can help in suggesting the most proper device for any particular application and also they can show and explain the capability of the companies’ products.
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