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EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 6 Programmable.

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Presentation on theme: "EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 6 Programmable."— Presentation transcript:

1 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 6 Programmable ASIC I/O Cells Application-Specific Integrated Circuits Michael John Sebastian Smith Addison Wesley, 1997

2 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 I/O Requirements I/O cells handle driving signals off chip, Receiving and conditioning external inputs, Supplying power and ground, and Handling such things as electrostatic protection Different types of I/O requirements DC output - driving a resistive load at DC or low frequency, LEDs, relays, small motors, etc. AC output - driving a capacitive load with a high-speed logic signal off-chip, data or address bus, serial data line, etc. DC input - reading the value of a sensor, switch, or another logic chip AC input - reading the value of high-speed signals from another chip Clock input - system or synchronous bus inputs Power input - supplying power (and ground) to the I/O cells and logic core

3 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 CMOS Output Buffer Figure 6.2(a) A CMOS complementary output buffer. (b) Pull-down transistor M2 sinks a current I OL through a pull-up resistor R 1. (c) Pull-up transistor M1 sources current -I OH through a pull- down resistor R 2. (d) Output characteristics. CMOS output buffer has finite (non-zero) output resistance Therefore, it can only drive the output voltage rail-to-rail for a zero output current Typical output currents that can be driven by a standard digital I/O pad are in the range of 50mA to 200mA

4 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Motor Control (Robotic Arm) Application Figure 6.1A robot arm. (a) Three small DC motors drive the arm. (b) Switches control each motor.

5 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 I/O Circuit for High Current Motor Control Figure 6.3A circuit to drive a small electric motor (0.5A) using ASIC I/O buffers.

6 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Totem-Pole Output Figure 6.4Output buffer characteristics. (a) A CMOS totem-pole output stage (b) Totem-pole output characteristics. (c) Clamp diodes. (d) The clamp diodes start to conduct as the output voltage exceeds the supply voltage bounds. Uses two n channel transistors as output drivers Advantage is that it has a higher output drive for a ‘1’ output Disadvantage is that output voltage will not be higher than VDD -V Tn

7 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 AC Output AC outputs are often used to connect to a bi-directional bus - bus transceivers This functionality requires the capability for three-state (tri- state) outputs - ‘0’, ‘1’, and high-impedance or hi-z In addition to rise and fall times, bidirectional I/O pads have timing parameters related to the hi-z state (float time): t ENZL - output hi-Z to ‘0’ time t ENLZ - output ‘0’ to hi-Z t ENZH - output hi-Z to ‘1’ t ENHZ - output ‘1’ to hi-Z I/O Pad OE Data_Out Data_In Bi-Directional I/O Pad

8 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, State Bus Example Figure 6.5A three-state bus. (a) Bus parasitic capacitance. (b) The output buffers in each chip. The ASIC CHIP1 contains a bus keeper, BK1.

9 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, State Bus Timing Figure 6.6Three-state bus timing for Figure 6.5.

10 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Characterizing AC Output Pads Figure 6.7(a) The test circuit for characterizing the ACT2 and ACT 3 I/O delay parameters. (b) Output buffer propagation delays from the data input to PAD. (c) Three-state delay with D low. (d) Three-state delay with D high.

11 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Supply (GND) Bounce Figure 6.8Supply bounce. (a) As the pull-down device M1, switches, it causes the GND net to bounce. (b) The supply bounce is dependent on the output slew rate. (c) Ground bounce can cause other output buffers to generate a logic path. (d) Bounce can also cause errors on other inputs. Ground (also VDD) net has finite parasitic resistance and inductance Switching a load through a pull-down transistor causes a 2nd order response (ground bounce or ringing) on ground net Ground bounce can cause glitching on other logic signals

12 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Transmission Lines Driving large capacitive loads at high speed gives rise to transmission line effects Transmission lines are defined by their characteristic impedance - determined by their physical characteristics Maximum energy transfer occurs when the source impedance matches the transmission line impedance V w = V o (Z o /R 0 +Z 0 ) The time it takes the signal wave to propagate down the transmission line is called the time-of-flight (t f ) Typical time-of-flight for a PCB trace is on the order of 1 ns for every 15 cm of trace (about 1/2 the speed of light) When the signal wave is launched into the transmission line, it travels to the other end and is reflected back to the source Transmission line effects become important if the rise time of the driver is less than 2t f

13 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Transmission Line Example Figure 6.9Transmission lines. (a) A printed-circuit board (PCB) trace is a transmission line. (b) A driver launches an incident wave which is reflected at the end of the line. (c) A connection starts to look like a transmission line when the signal rise time is about equal to twice the delay.

14 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Terminating a Transmission Line Methods to terminate a transmission line: Open circuit or capacitive termination - bus termination is the input capacitance of the receivers Parallel resistive termination - requires substantial DC current - used in bipolar logic Thévenin termination - reduces DC current on the drivers, but adds resistance across the source Series termination - total series resistance (source and termination) equals the line impedance Parallel termination - requires a third power supply Parallel termination with series capacitance - eliminates DC current but introduces other problems Some high-speed busses actually use the reflection facilitate the data transmission (PCI bus) Other techniques include current-mode signaling or differential signals

15 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Terminating a Transmission Line (cont.) Figure 6.10Transmission line termination. (a) Open-circuit or capacitive termination. (b) Parallel resistive termination. (c) Thévenin termination. (d) Series termination at the source. (e) Parallel termination using a voltage bias. (f) Parallel termination with a series capacitor.

16 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 DC Input - Switch Bounce Figure 6.11A switch input. (a) A pushbutton switch connected to an input buffer with a pull-up resistor. (b) As the switch bounces several pulses may be generated. A pull-up or pull-down resistor is generally required on input buffers to keep input from floating to indeterminate logic levels If the input is from a mechanical switch, the contacts may bounce, producing several transitions through the switching threshold Some technique for debouncing mechanical switch inputs is usually necessary

17 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Debouncing Using an SR Flip-Flop NC NO 0  1  0 1  0  1 SPDT momentary switch or relay

18 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Debouncing Using Hysteresis Figure 6.12DC input. (a) A Schmitt-trigger inverter. (b) A noisy input signal. (c) Output from an inverter with no hysteresis. (d) Hysteresis helps prevent glitches. (e) A typical FPGA input buffer with a hysteresis of 200mV centered around a threshold of 1.4 V.

19 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 DC Operation: Voltage Transfer Characteristic Figures from material provided with Digital Integrated Circuits, A Design Perspective, by Jan Rabaey, Prentice Hall, 1996

20 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Mapping between analog and digital signals Figures from material provided with Digital Integrated Circuits, A Design Perspective, by Jan Rabaey, Prentice Hall, 1996

21 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Definition of Noise Margins Figures from material provided with Digital Integrated Circuits, A Design Perspective, by Jan Rabaey, Prentice Hall, 1996

22 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Noise Margins - Another Representation Figure 6.13Noise margins. (a) Transfer characteristics of a CMOS inverter with the lowest switching threshold. (b) The highest switching threshold(c) A graphical representation of CMOS thresholds. (d) Logic thresholds at the inputs and outputs of a logic gate or an ASIC. (e) The switching thresholds viewed as a plug and socket. (f) CMOS plugs fit CMOS sockets and the clearances are the noise margins.

23 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Noise Margins - Interfacing TTL and CMOS Figure 6.14TTL and CMOS logic thresholds. (a) TTL logic thresholds. (b) Typical CMOS logic thresholds. (c) A TTL plug will not fit into a CMOS socket. (d) Raising V OHmin solves the problem.

24 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Noise Margins - Mixed Voltage Systems (e.g. 3.3V and 5V) Figure 6.15Mixed-voltage systems. (a) TTL levels. (b) Low-voltage CMOS levels. (c) A mixed-voltage ASIC. (d) A problem when connecting two chips with different supply voltages - caused by the input clamp diodes.

25 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Positive Feedback: Bi-Stability Figures from material provided with Digital Integrated Circuits, A Design Perspective, by Jan Rabaey, Prentice Hall, 1996

26 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Gain should be larger than 1 in the transition region Meta-Stability Figures from material provided with Digital Integrated Circuits, A Design Perspective, by Jan Rabaey, Prentice Hall, 1996

27 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Metastability Example Figure 6.16Metastability. (a) Data coming from one system is an asynchronous input to another. (b) A flip-flop has a very narrow decision window bounded by the setup and hold times. If the data input changes inside this decision window, the output may be metastable - neither ‘1’ or ‘0’.

28 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Probability of Upset An upset is when a flip-flop output should have been a ‘0’ and was a ‘1’ or visa-versa Probability of upset is: where t r is the resolution time and T 0 and  c are constants of the flip-flop implementation Mean time between upsets (MTBU - similar to mean time between failures) is: where f clock is the clock frequency and f data is the data frequency

29 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Probability of Upset Example Assume t r = 5 ns,  c =0.1 ns, and T 0 = 0.1s: Assume f clock = 100 MHz and f data = 1 MHz: if we have a bus with 64inputs, each using a flip-flop as above, the MTBU of the system is three months

30 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 MTBF as a Function of Resolution Time Figure 6.17Mean time between failures (MTBF) as a function of resolution time.

31 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Clock Input Most FPGAs and PLDs provide a dedicated clock input(s) Clock input needs to be low latency t PG, but also low skew t skew Low skew is ensured by using a dedicated, balanced clock tree, but this tends to increase clock latency Example: Actel ACT1 FPGAs have a clock latency that can be as high as 15ns if the clock drives over 300 loads (flip-flops), but the skew is stated to be in the sub nanosecond range Large clock latency causes hold time restrictions on data inputs - data gets to the flip-flops faster than clock and must remain there until clock arrives to flip-flops... Clock I/O Pad Balanced Clock Tree t PG t skew

32 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Clock Input Example Figure 6.18Clock input. (a) Timing model with values for Xilinx XC (b) A simplified view of clock distribution. (c) Timing diagram. Xilinx eliminates the variable internal delay t PG by specifying a pin-to-pin setup time t PSUFmin = 2ns.

33 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Programmable Input Delay to Eliminate Hold Time on Data Inputs Figure 6.19Programmable input delay. (a) Pin-to-pin timing model with values from an XC (b) Timing diagrams with and without programmable delay.

34 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Effect of Clock Latency on Registered Outputs Figure 6.20Registered output. (a) Timing model with values for an XC programmed with the fast slew rate option. (b) Timing diagram.

35 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Power Input All devices require inputs for VDD and Gnd during operation and programming voltage, VPP, during programming Larger devices with greater logic capacity require more power pins to supply the necessary power while maintaining a reasonable per-pin current limit This reduces the number of signal pins possible for larger devices Some types of FPGAs (e.g. Xilinx) have their own power-on reset sequence to reset flip-flops, initialize and load SRAM, etc.

36 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Example FPGA I/O Block Figure 6.21The Xilinx XC4000 family Input/output block (IOB).

37 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Timing Model with I/O Block Figure 6.22The Xilinx LCA (logic cell array) timing model. The paths show different uses of CLBs and IOBs.

38 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Example FPGA I/O Block (cont.) Figure 6.23A simplified block diagram of the Altera I/O Control Block (IOC) used in the MAX 5000 and MAX 7000 series.

39 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Example FPGA I/O Block (cont.) Figure 6.24A simplified block diagram of the Altera I/O Element (IOE) used in the Flex 8000 and 10k series.


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