Presentation on theme: "# 1 Finding the root cause of ESD problems Dr. David Pommerenke With contributions from all members of the EMC laboratory University Missouri Rolla – EMC."— Presentation transcript:
# 1 Finding the root cause of ESD problems Dr. David Pommerenke With contributions from all members of the EMC laboratory University Missouri Rolla – EMC laboratory email@example.com
# 2 ESD is combines many tests in one test ESD failure analysis Susceptibility scanning Voltage in traces during ESD testing Content
# 3 Definitions Hard-error: Any error that leads to a physical failure of the IC. (Excessive leakage current, loss of functionality) Soft-error: Any error that can be cured by resetting the system (logical errors: bit error, false reset)
# 4 Physical parameters that may lead to an ESD failure ESD combines many different tests into one test standard. From electrostatics, via breakdown physics to a 1 GHz 20kV/m pulse.
# 5 It failed, what now? Is it a soft or a hard failure? At which test point did it fail? At which voltage did it fail? Was it in contact or air discharge mode? How repeatable is the failure? It has failed! - What to do now? Question: What do you do to debug ESD problems?
# 6 How to fix it? Exact circuit understanding Pro: The most cost efficient solution. Learn how to design in the future. Contra: Need to understand software Need to understand circuits Requires specialized equipment May require special firmware Shielding Pro: No system understanding needed. If it works, the fast! Contra: Often more expensive solution Adds material But how to do it?
# 7 20mm 50mm 200mm @ 8kV, restart @ 10kV restart @ 15kV restart EUT display Local probing around the EUT A first start of finding the root cause may be: Locating sensitivity on the outside might help to correlate to the affected IC or trace, but: Outside location may only be a result of breach in shielding Outside location is too broad to correlate to details inside: Let’s go inside!
# 8 Different coupling mechanisms require different probes Injection can be done: To the enclosure To cables To connectors To boards To board traces To lead-frames traces - dm - cm - mm - cm 2 - 5 mil (using microscope) - 1 mil (using microscope)
# 9 Probes used for injection
# 10 Different coupling mechanisms require different probes Direct injection between to “grounds”. In selecting the right injection method one has to try to emulate the same excitation mechanism as occurs during the standardized test or at the customer site. Anticipating the right method is often guided by carefully observing the differences of failure signature at different test points.
# 11 Disturbance sources: TLP and narrow pulse The measurement of the high voltage transmission line pulse generator output pulse, about 500 ps rise (20- 80%) Less than 200 ps pulse Narrow pulse generator
# 12 Automated Susceptibility Scanning system of UMR Brief explanation The system moves injection probes to predefined locations, injects pulses and observes the system response. In most cases, pulses are “ESD- like”, e.g., having rise times 0.1 - 2 ns. Injection is done using different injection probes for testing direct coupling, E and H-field coupling. If needed, the voltages at the input of the IC are measured during the ESD event.
# 13 Control Computer Scope signal probing Pulse injection Probe position data, motion control TLP triggering signal Motion Control TLP Power S/W System monitor (parallel port) Automated Susceptibility Scanning system of UMR Critical is the error feedback: A test code needs to be operating on the EUT. The test code signals to the control PC if a malfunction has occurred. If so, the level of injected noise (by source setting, not by induced voltage) is recorded and the EUT is reset.
# 14 Test flow diagram
# 15 Example: Identifying sensitive nets Besides direct coupling to an IC, four sensitive nets are identified Only 4 nets are sensitive, but there sensitivity is 10X as strong as any other net 180190200210220230240250 240 250 260 270 280 290 300 310 180190200210220230240250 240 250 260 270 280 290 300 310 180190200210220230240250 240 250 260 270 280 290 300 310 180190200210220230240250 240 250 260 270 280 290 300 310 Net 1 Net 2 Net 3 Net 4 50100150200250 300 350 400 450 Net 1 Net 2 Net 3 Net 4
# 16 180190200210220230240250 240 250 260 270 280 290 300 310 Probe Polarization : ← Scanned in next stage The same area is scanned using different polarization of the H-field probe. The difference between the “left” and the “right” polarization is the polarity of the induced noise voltage. The sensitive traces are identified by circuit diagram. If needed a finer scan is performed. Example: Identifying sensitive nets
# 17 1mm 1.5mm 178180182184186188190192 194 238 240 242 244 246 248 250 252 254 256 A critical part of the board in the previous scanned area has been fine-scanned using very small magnetic field probe to identify the correct trace The scan resolution was set to 0.5mm x 0.5mm The small probe couples less energy into the trace, but in a highly localized area Example: Identifying sensitive nets
# 18 180 190200210220230240250 240 250 260 270 280 290 300 310 180 190200210220230240250 240 250 260 270 280 290 300 310 180 190200210220230240250 240 250 260 270 280 290 300 310 180190200210220230240 250 240 250 260 270 280 290 300 310 Net 1 Net 2 Net 3 50100150200250 300 350 400 450 Net 1 Net 2 Net 3 After comparing the identified sensitive nets with PCB layout, three nets have been identified to be sensitive to ESD The sensitivity of those nets have been quantified in terms of applied voltage in the HV generator Induced current direction on the each sensitive net has been identified Modification to a sensitive net
# 19 TXRX 100ohm 330pF Filter Location Modification to a sensitive net Simple Low Pass
# 21 707580859095100105 275 280 285 290 295 300 305 310 Scanned Area Medium Magnetic Probe The top side of the PCB is scanned using the medium size magnetic probe with four different polarization Some sensitive areas on the IC are identified Direct coupling to ICs
# 22 Direct coupling to ICs Signal couples directly into the IC IC reacts to narrow pulses much narrower than the intended signals 300ps For such an ICs, no PCB or shielding solution is economical. Scanning can identify such situations and help to verify improvements in the IC design, packaging (e.g., flip-chip) or the control software. In our experience, direct coupling to ICs is growing problem: Fast IC process technology is used more and more in badly shielded products. Coupling to PCBs is reduced by burried layers and traces Dense PCBs have hardly any traces visible (BGA packages)
# 23 New is better, well …. Shown are the voltage settings of a pulse generator at which an upset occurs if A narrow pulse (less than 300 ps width at 50% amplitude) is causing an upset of the IC. Note: the new IC performed worse! Worsening ESD soft-error performance is a significant risk if new processes are introduced, or if I/O structures are modified.
# 24 Voltages on traces
# 25 Semi rigid coax cable, connected to 20GS/sec 6 GHz bandwidth scope 470 Ohm GND VIA (close to the Trace) How measure in-circuit while pulsing? The trace is loaded by 470 + 50 Ohm. The small loop area ensures little dB/dt coupling and good frequency response of the probing method.
# 26 Three traces have been isolated by terminating/filtering circuits Double pulse has been eliminated The reset line still reacts to this narrow pulse (the system crashed) It has been shown that the IC of interest is causing the crash, reacting to a very narrow pulse Inner layer trace connects to another IC connects to another IC 012345 0.8 1 1.2 1.4 Time [ns] Voltage[V] 75ohm 100pF 56pF 75ohm 56pF IC of interest Coaxial Probe attached here Pulse injection here 1000 Very Narrow pulse on slow status line (< 150ps) leads to crash Voltages on a status line
# 27 Clock_N Clock_P (Ch 2 on scope) Clock_N (Ch 1 on scope) 200ps pulse injection here! Pulse has been applied repeatedly, increasing the voltage until system crashes Waveforms are recorded (20 GHz / 6 Gsample/sec). Differential clock
# 28 ESD Event on differential clock crash Very sensitive to noise during the transition
# 29 ESD Event on differential clock No crash! crash Crash threshold : approx. 0.2V + - Clock_N Clock_P Differential input has an offset
# 30 The result is repeatable. Increasing difference should not lead to a system crash. Why? Noise increased differential voltage
# 31 ESD on differential clock – Common Mode disturbance No crashIf the common mode voltage is relatively low, the differential input will suppress the common mode signal. 2x330
# 32 no crash No crash, although the differential signal is already strongly disturbed Common mode: Not crashed
# 33 120V from the HV generator was injected on both Clock_P and Clock_N Crashed Common mode: Crashed Differential Mode is about as robust as single ended signaling. Design details matter: (conversion, common mode termination etc.) crash
# 34 How an IC can react to pulses Voltage surpasses threshold for a sufficiently long time Linear network, bond wire inductance and input capacitance, ring or peak the pulse, leading to a softerror. Voltage triggers non-linear effect on the input buffer Voltage causes ESD protection to forward bias, causes substrate injection or internal power fluctuations, leading to crash Current leads to latch-up, or latch-up like situation.
# 35 Immunity problems caused by global coupling vs. local coupling to one trace. Correlation system level – board level. IC level immunity test methods and robustness guidelines for IC design are not well developed yet. IC level immunity standards. Software for improving immunity. Latch-up and ESD protection circuit recovery, how many of the observed soft errors are caused by latch-up? Open Questions
# 36 Conclusion Using local injection the disturbed traced can be identified. The sensitivity of I/O ports can be quantified. These data can be used to analyze the function of circuits designed to reduce ESD sensitivity. In-circuit measurements can be done while doing local injection, as the amount of common mode signal is vastly reduced. This is a developing field, many questions are still out there, just waiting to be solved.
# 37 IC ESD System level ESD Consequence Standard Voltage DUT Operating? Application method Tested properties When does it occur? Destructive CDM / HBM / MM Typically < 3000 IC, sub system System is not powered Direct to the IC PINs IC protection circuits Manufacturing, handling Destructive and Upset IEC 61000-4-2 Typically < 15 000 System System is operating Enclosure, PINs System design Qualification tests, Customer site IC and system level ESD testing
# 38 Probe Polarization Induced Current on the net The board has been scanned with four different probe polarization (up, down, left, right) to take account of the induced current on the board The medium size magnetic field probe was used with 1.5mm x 1.5mm scan resolution ESD sensitive net can be identified roughly, but the resolution is not so fine enough to pin point a single trace. Example: Identifying sensitive nets