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Built-In Self-Test for Field Programmable Gate Arrays funded by National Security Agency Chuck Stroud Electrical & Computer Engineering Auburn University.

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Presentation on theme: "Built-In Self-Test for Field Programmable Gate Arrays funded by National Security Agency Chuck Stroud Electrical & Computer Engineering Auburn University."— Presentation transcript:

1 Built-In Self-Test for Field Programmable Gate Arrays funded by National Security Agency Chuck Stroud Electrical & Computer Engineering Auburn University

2 Outline of Presentation OverviewOverview  Built-In Self-Test (BIST)  Field Programmable Gate Arrays (FPGAs) BIST for FPGAsBIST for FPGAs  Logic resources  Routing resources Demonstration of FPGA logic BIST & DiagnosisDemonstration of FPGA logic BIST & Diagnosis

3 The Need for Test 2000 International Technology Roadmap for Semiconductors (by the Semiconductor Industry Association - SEMATECH ) predicts by 2014: Test machines will cost > $20MTest machines will cost > $20M It will cost more to test a transistor than to manufacture itIt will cost more to test a transistor than to manufacture it Built-In Self-Test (BIST) is a likely solutionBuilt-In Self-Test (BIST) is a likely solution  Analog BIST is needed for mixed-signal systems  Fault diagnosis is needed with BIST  Tools are needed for automating BIST

4 What is BIST? Basic idea: Add circuitry to IC or PCB to facilitate testing itselfBasic idea: Add circuitry to IC or PCB to facilitate testing itself  Only power and clock needed during BIST sequence  Pass/Fail result reported at end of BIST sequence  No need for external test equipment Necessary components:Necessary components:  Test Pattern Generator (TPG)  Output Response Analyzer (ORA)  For system level use:  Test controller  Input isolation Penalties: area overhead, performancePenalties: area overhead, performance Benefits: low testing time & costBenefits: low testing time & cost TPG ORA CircuitUnderTest TestControl MUXSystemInputsSystemOutputs Pass/Fail BIST Start

5 Overview of FPGAs Configuration MemoryConfiguration Memory Programmable Logic Blocks (PLBs)Programmable Logic Blocks (PLBs) Programmable Input/Output CellsProgrammable Input/Output Cells Programmable InterconnectProgrammable Interconnect Typical Complexity = 5M - 100M transistors

6 Basic FPGA Operation Load Configuration Memory Defines system functionDefines system function  Input/Output Cells  Logic in PLBs  Connections between PLBs & I/O cells Changing configuration memory => changes system function Can change at anytimeCan change at anytime  Even while system function is in operation  Run-time reconfiguration (RTR)

7 Programmable Logic Blocks PLBs can perform any logic functionPLBs can perform any logic function  Look-Up Tables (LUTs)  Combinational logic  Memory (RAM)  Flip-flops  Sequential logic  Special logic  Add, subtract, multiply  Count up and/or down  Dual port RAM Must be tested in all modes of operationMust be tested in all modes of operation #PLBs/FPGA: 100 to 50,000#PLBs/FPGA: 100 to 50,000 LUT/ RAM FF LUT/ RAM FF LUT/ RAM FF LUT/ RAM FF PLB architecture

8 Programmable Interconnect Wire segments & Programmable Interconnect Points (PIPs)  cross-point PIPs – connect/disconnect wire segments  To turn corners  break-point PIPs – connect/disconnect wire segments  To make long and short signal routes  multiplexer (MUX) PIPs select 1 of many wires for output  Used at PLB inputs  Primary interconnect media for new FPGAs configurationmemoryelement wire A wire B cross-point PIP wire A wire B wire A wire B break-point PIP wire A wire B output multiplexer PIP wire C

9 BIST for FPGAs Basic idea: reprogram FPGA to test itselfBasic idea: reprogram FPGA to test itself BIST logic disappears after testBIST logic disappears after test  No area overhead or performance penalties Applicable to all levels of testingApplicable to all levels of testing  A generic test for a generic component  Independent of system function Good diagnostic resolutionGood diagnostic resolution  Logic: Look-Up Table (LUT) or flip-flop  Routing: wire segment or switch  Reconfigure system function for fault-tolerance Cost: memory to store BIST configurationsCost: memory to store BIST configurations

10 BIST Architecture for PLBs TPGs BUTs ORAs BUTs ORAs BUTs ORAs BUTs TPGs BUTs ORAs BUTs ORAs BUTs ORAs BUTs TPGTPGBUT BUT ORA BUT BUT ORA BUT BUT ORA BUT BUT ORA Configure row (or columns) of PLBs as: Test Pattern Generators (TPGs) Output Response Analyzers (ORAs) Blocks Under Test (BUTs) Reverse rolls after testing 1 st set of BUTs

11 Diagnostic Procedure Step 1: Record ORA results Step 2: Mark known good BUTs Step 3: Mark implied good BUTs MULTIple faulty CELL LOcator MULTICELLO ? ?11 000? Step 4: Mark known faulty BUTs Step 5: Look for inconsistences => implies possible interconnect faults Step 6: If every PLB has been identified as fault-free or faulty, the group of faulty PLBs has been uniquely diagnosed => otherwise mark as unknown

12 Routing BIST Architecture Wires Under Test (WUTs)Wires Under Test (WUTs)  Wire segments connected via PIPs & PLBs to form WUTs  Opposite values on busses not under test (PIPs stuck-on)  All WUTs are 2-tested to detect equivalent faults TPGs & ORAs formed as in logic BISTTPGs & ORAs formed as in logic BIST  Exhaustive test patterns detect shorts, opens, & stuck-at faults  ORA compares two sets of WUTs (A WUTs & B WUTs) PLB TP G ORA A WUTs B WUTs

13 ORA TPG STAR Routing BIST Architecture Uses small Self-Test AReas (STARs) to test routing resources Good diagnostic resolutionGood diagnostic resolution  To STAR Higher speed testingHigher speed testing  Fewer series PIPs delays Run STARs in parallel V-STARs test vertical routingV-STARs test vertical routing H-STARs test horizontal routingH-STARs test horizontal routing Uses small Self-Test AReas (STARs) to test routing resources Good diagnostic resolutionGood diagnostic resolution  To STAR Higher speed testingHigher speed testing  Fewer series PIPs delays Run STARs in parallel V-STARs test vertical routingV-STARs test vertical routing H-STARs test horizontal routingH-STARs test horizontal routing ORA TPG STAR ORA TPG STAR ORA TPG STAR ORA TPG STAR ORA TPG STAR

14 Diagnostic Configurations Partition into smaller STARsPartition into smaller STARs  Identify faulty region of WUT TPG ORA TPG ORA TPG ORA Singlewire TPG ORA TPG ORA ORA ORA ORA Re-route portions of netRe-route portions of net  Identify faulty wire segment or PIP Add ORAs & change directionsAdd ORAs & change directions  Identify fault region of WUT TPGORA ORAORA TPGORA ORAORA ORAORA ORAORA

15 Test Results for Faulty FPGAs Failures from Chip 1  At least 1 fault  maybe at intersection of STARs V-STAR column position H-STAR row position Failures from Chip 2  At least 2 faults  maybe at intersection of STARs Diagnostic results  A short at row 10 column 8 Diagnostic results  A short at row 1 column 12  Short in 3 wires of 4-wire bus  row 5 columns 6-8

16 System or BIST config FPGA Fault Injection Emulator Faulty FPGA are difficult to findFaulty FPGA are difficult to find  1 FPGA with faulty PLB & 2 FPGAs with faulty routing We created a Fault Injection EmulatorWe created a Fault Injection Emulator  Intercepts & modifies configuration bits prior to download  Fault Emulator can create multiple faults in:  PLBs: LUTs, flip-flops, etc.  Interconnect: PIPs stuck-on & stuck-off Stuck-at values Fault mask Download file faults

17 BIST Demonstration Graphic User InterfaceGraphic User Interface  Shows what is happening inside FPGA during test  Provides interface to fault injection emulation Fault Injection EmulatorFault Injection Emulator  Inserts faults into configuration data file  Emulated faults are downloaded with BIST phases Logic BISTLogic BIST  MULTICELLO diagnostic algorithm incorporated Current demo for Xilinx 4010XL FPGACurrent demo for Xilinx 4010XL FPGA  20x20 PLB array with 100K PIPs & 25K wire segments  BIST phases automatically generated for any 4000 series FPGA by programs we have developed


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