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A. Kluge January 25, 2013. Aug 27, 2012 Outline NA62 NA62 Specifications Specifications Architecture Architecture A. Kluge2.

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Presentation on theme: "A. Kluge January 25, 2013. Aug 27, 2012 Outline NA62 NA62 Specifications Specifications Architecture Architecture A. Kluge2."— Presentation transcript:

1 A. Kluge January 25, 2013

2 Aug 27, 2012 Outline NA62 NA62 Specifications Specifications Architecture Architecture A. Kluge2

3 Aug 27, 2012 NA62 - Introduction A. Kluge

4 Aug 27, 2012 Vacuum tank Mag2Mag3 Mag4Mag1 GTK1 GTK3 GTK2 Cedar Experimental setup- NA62 selects particles with 75 GeV/c sees kaons only Achromat 250 m beam: hadrons, only 6% kaons-> only 20% of charged kaon decay in the vacuum tank -> out of which only decays are of interest (pion-neutrino-antineutrino) straw chambersRICH hit correlation via matching of arrival times – 100 ps RICH identifies pions straw chambers measure position GTK sees all particles A. Kluge

5 Aug 27, 2012 Experimental setup 300 µm 100 ps time binning of arrival time 800 MHz particle rate A. Kluge 200 ps per station

6 Aug 27, 2012 Experimental setup 300 µm 100 ps time resolution arrival time thin, 200µm sensor µm chip (<0.5% of X 0 ), operated in vacuum A. Kluge

7 Aug 27, 2012 Beam & detector configuration A. Kluge

8 Aug 27, 2012 Beam profile 60 mm 27 mm A. Kluge

9 Aug 27, 2012 ASIC covering beam 60 mm 27 mm 13.5 mm mm 12 mm 45 rows times 40 columns per chip = 1800 pixels per chip A. Kluge 7

10 Aug 27, 2012 A. Kluge Configuration for beam 27-60

11 Aug 27, 2012 Giga Tracker setup Sensor&bonds: 0.24% X 0 (200 µm Silicon)Sensor&bonds: 0.24% X 0 (200 µm Silicon) RO chip: 0.11% X 0 (100 µm Silicon)RO chip: 0.11% X 0 (100 µm Silicon) Structure: 0.12% X 0 (120 µm silicon)Structure: 0.12% X 0 (120 µm silicon) Total: 0.47% X 0 uniformTotal: 0.47% X 0 uniform A. Kluge

12 Aug 27, 2012 The electronics specification 12

13 Aug 27, 2012 General: System Specifications Number of pixels per chip1800 = 45 x 40 Size of pixels300 µm x 300 µm Active area per chip12 mm x 13.5 mm = 162 mm 2 Chip design TDC binning100 ps Thickness of sensor200 µm Type of sensorp in n Thickness of read-out chip100 µm Dynamic input range5000 – electrons 13

14 Aug 27, 2012 General: System Specifications Design particle rate per chip130 MHz Rate of center pixel140 kHz Rate of center column~ 3.3 MHz or 0.82 MHz/mm 2 Average rate per pixel73 kHz Maximum dead time1 % (2 % in beam center) Data transfer rate per chip6 Gbit/s Total dose in 1 year~ 6 * 10 4 Gy Neutron flux in 100 days2 x MeV neutron equivalent cm -2 Material budget/thickness0.5 % X 0 per station 14

15 Aug 27, 2012 Energy release GTK per hit mean energy: 72.4 keV (~20.1 k e-h  ~3.2 fC) mean energy: 72.4 keV (~20.1 k e-h  ~3.2 fC) most probable energy: 53.7 keV (~14.9 k e-h  ~2.4 fC) most probable energy: 53.7 keV (~14.9 k e-h  ~2.4 fC) minimum energy: ~29 keV (~8.1 k e-h  ~1.3 fC) minimum energy: ~29 keV (~8.1 k e-h  ~1.3 fC) with 300 V sensor bias: charge collection within ~ 3 ns expected with 300 V sensor bias: charge collection within ~ 3 ns expected M. Fiorini 15

16 Aug 27, 2012 End-of-column architecture 16

17 Aug 27, 2012 EOC column principle No digital signals are distributed to pixel matrix No digital signals are distributed to pixel matrix except configuration and test pulse except configuration and test pulse time-to-digital converter TDC buffering & read-out processor amplifier & discriminator/ time-walk- compensator reference clock 17

18 Aug 27, 2012 time walk 18

19 Aug 27, 2012 Time-over-threshold t A t1t1 t0t0 A1A1 t TOT t2t2 19

20 Aug 27, 2012 The time-to-digital conversion Delay locked loop based TDC 20

21 Aug 27, 2012 DLL based TDC DAC1 Pixel cell TDC 012m-2m-1 Clk = t clk Phase detector & charge pump Ref CLK PDCP UP DOWN DLL CLK V CTRL 21

22 Aug 27, 2012 front-end processing chain & grouping of pixels A. Kluge22 pre-amplifier TOT discriminator transmission line driver Pixel cell 0 Pixel cell 9 Pixel cell 18 Pixel cell 36 Pixel cell 27 5 transmission line receivers 5 transmission lines 1 out of 9 pixel groups in a column hitArbiter TDC bank

23 Aug 27, 2012 grouping of pixels Readout and supply 23

24 Aug 27, 2012 Pixel segmentation 24

25 Aug 27, x 40 pixel TDCpix 25

26 Aug 27, 2012 A. Kluge26

27 Aug 27, 2012 A. Kluge27

28 Aug 27, 2012 A. Kluge28

29 Aug 27, 2012 A. Kluge29

30 Aug 27, 2012 TDCpix demonstrator A. Kluge30

31 Aug 27, 2012 Layout –EOC 130µm mm 2.8 mm 31

32 Aug 27, 2012 Layout –EOC 130µm Analogue test structures Data grouping & pixel address Receiver 2x23 Receiver 2x23 pads 2 x EOC test pads 1 folded column of 45 pixels test pixels mm 2.8 mm test pixels 32

33 Aug 27, 2012 Layout –EOC 130µm Analogue test structures Data grouping & pixel address pads sensor 4.14 x 5.37 mm 2 EOC test pads 1 folded column of 45 pixels mm 2.8 mm 33

34 Aug 27, 2012 GTK demonstrator ASIC 34

35 Aug 27, 2012 GTK demonstrator ASIC 35

36 Aug 27, 2012 TDCpix demonstrator: test pulse & laser test A. Kluge36

37 Aug 27, 2012 TDCpix demonstrator: beam test A. Kluge37

38 Aug 27, 2012 Backup slides A. Kluge38

39 Aug 27, 2012 A. Kluge39

40 Aug 27, 2012 Clock modes A. Kluge40 serial PLL2.4 lowClkSyn c serial PLL2.4 highClkSync serial PLL3.2 ext 320 lowClkSync ext 320 highClkSync ext 480 lowClkSync ext 480 highClkSync pllOverride # code H110H0H100H0H110H1H100H11011H0 clkInDigital clkPLL clkSync clkFIFOread clkMultiSerial clkConfig

41 Aug 27, 2012 Clk distribution: serial 3.2 Gbit/s A. Kluge41

42 Aug 27, 2012 PLL & clock divider A. Kluge42

43 Aug 27, 2012 A. Kluge43


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