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1 Analog to Digital Conversion ADC Essentials A/D Conversion Techniques Interfacing the ADC to the IBM PC DAS (Data Acquisition Systems) How to select.

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Presentation on theme: "1 Analog to Digital Conversion ADC Essentials A/D Conversion Techniques Interfacing the ADC to the IBM PC DAS (Data Acquisition Systems) How to select."— Presentation transcript:

1 1 Analog to Digital Conversion ADC Essentials A/D Conversion Techniques Interfacing the ADC to the IBM PC DAS (Data Acquisition Systems) How to select and use an ADC A low cost DAS for the IBM PC

2 Chap 02 Why ADC ? n Digital Signal Processing is more popular u Easy to implement, modify, … u Low cost n Data from real world are typically Analog n Needs conversion system u from raw measurements to digital data u Consists of F Amplifier, Filters F Sample and Hold Circuit, Multiplexer F ADC

3 Chap 03 ADC Essentials n Basic I/O Relationship u ADC is Rationing System F x = Analog input / Reference Fraction: 0 ~ 1 n n bits ADC u Number of discrete output level : 2 n u Quantum F LSB size F Q = LSB = FS / 2 n n Quantization Error u  1/2 LSB u Reduced by increasing n

4 Chap 04 Converter Errors n Offset Error n Gain Error n Can be eliminated by initial adjustments n Integral Linearity Error n Differential Linearity Error n Nonlinear Error u Hard to remove

5 Chap 05 Terminologies n Converter Resolution u The smallest change required in the analog input of an ADC to change its output code by one level n Converter Accuracy u The difference between the actual input voltage and the full-scale weighted equivalent of the binary output code u Maximum sum of all converter errors including quantization error n Conversion Time u Required time (tc) before the converter can provide valid output data n Converter Throughput Rate u The number of times the input signal can be sampled maintaining full accuracy u Inverse of the total time required for one successful conversion u Inverse of Conversion time if No S/H(Sample and Hold) circuit is used

6 Chap 06 More on Conversion Time n Input voltage change during the conversion process introduces an undesirable uncertainty n Full conversion accuracy is realized only if this uncertainty is kept low below the converter’s resolution u Rate of Change x tc  resolution u n Example u 8-bit ADC u Conversion Time: 100  sec u Sinusoidal input F F Rate of change F Let FS = 2A u Limited to Low frequency of 12.4 Hz F Few Applications

7 Chap 07 S/H increase Performance n S/H (Sample and Hold) u Analog circuits that quickly samples the input signal on command and then holds it relatively constant while the ADC performs conversion u Aperture time (ta) F Time delay occurs in S/H circuits between the time the hold command is received and the instant the actual transition to the hold mode takes place F Typically, few nsec n Example u 20 nsec aperture time F F Reasonably good for 100  sec converter

8 Chap 08 Analog Input Signal n Typically, Differential or Single-ended input signal of a single polarity u Typical Input Range F 0 ~ 10V and 0 ~ 5V u If Actual input signal does not span Full Input range F Some of the converter output code never used F Waste of converter dynamic range F Greater relative effects of the converter errors on output n Matching input signal and input range u Prescaling input signal using OP Amp F In a final stage of preconditioning circuit u By proportionally scaling down the reference signal F If reference signal is adjustable

9 Chap 09 Converting bipolar to unipolar n Using unipolar converter when input signal is bipolar u Scaling down the input u Adding an offset n Bipolar Converter u If polarity information in output is desired u Bipolar input range F Typically, 0 ~  5V u Bipolar Output F 2’s Complement F Offset Binary F Sign Magnitude F … n Input signal is scaled and an offset is added scaled Add offset

10 Chap 010 Outputs and Analog Reference Signal n I/O of typical ADC n ADC output u Number of bits F 8 and 12 bits are typical F 10, 14, 16 bits also available u Typically natural binary F BCD (3½ BCD) For digital panel meter, and digital multimeter n Errors in reference signal u From F Initial Adjustment F Drift with time and temperature u Cause F Gain error in Transfer characteristics n To realize full accuracy of ADC u Precise and stable reference is crucial F Typically, precision IC voltage reference is used 5ppm/  C ~ 100ppm/  C

11 Chap 011 Control Signals n Start u From CPU u Initiate the conversion process n BUSY / EOC u To CPU u Conversion is in progress F 0=Busy: In progress F 1=EOC: End of Conversion n HBE / LBE u From CPU u To read Output word after EOC F HBE High Byte Enable F LBE Low Byte Enable

12 Chap 012 A/D Conversion Techniques n Counter or Tracking ADC n Successive Approximation ADC u Most Commonly Used n Dual Slop Integrating ADC n Voltage to Frequency ADC n Parallel or Flash ADC u Fast Conversion n Software Implementation n Shaft Encoder

13 Chap 013 Counter Type ADC n Block diagram n Waveform n Operation u Reset and Start Counter u DAC convert Digital output of Counter to Analog signal u Compare Analog input and Output of DAC F Vi < V DAC Continue counting F Vi = V DAC Stop counting u Digital Output = Output of Counter n Disadvantage u Conversion time is varied F 2 n Clock Period for Full Scale input

14 Chap 014 Tracking Type ADC n Tracking or Servo Type u Using Up/Down Counter to track input signal continuously F For slow varying input n Can be used as S/H circuit u By stopping desired instant u Digital Output u Long Hold Time n Disabling UP (Down) control, Converter generate u Minimum (Maximum) value reached by input signal over a given period

15 Chap 015 Successive Approximation ADC n Most Commonly used in medium to high speed Converters n Based on approximating the input signal with binary code and then successively revising this approximation until best approximation is achieved n SAR(Successive Approximation Register) holds the current binary value n Block Diagram

16 Chap 016 Successive Approximation ADC n Circuit waveform n Logic Flow n Conversion Time u n clock for n-bit ADC u Fixed conversion time n Serial Output is easily generated u Bit decision are made in serial order

17 Chap 017 Dual Slope Integrating ADC n Operation u Integrate u Reset and integrate u Thus u  n Applications u DPM(Digital Panel Meter), DMM(Digital Multimeter), … n Excellent Noise Rejection u High frequency noise cancelled out by integration u Proper T 1 eliminates line noise u Easy to obtain good resolution n Low Speed u If T 1 = 60Hz, converter throughput rate < 30 samples/s

18 Chap 018 Voltage to Frequency ADC n VFC (Voltage to Frequency Converter) u Convert analog input voltage to train of pulses n Counter u Generates Digital output by counting pulses over a fixed interval of time n Low Speed n Good Noise Immunity n High resolution u For slow varying signal u With long conversion time n Applicable to remote data sensing in noisy environments u Digital transmission over a long distance

19 Chap 019 Parallel or Flash ADC n Very High speed conversion u Up to 100MHz for 8 bit resolution u Video, Radar, Digital Oscilloscope n Single Step Conversion u 2 n –1 comparator u Precision Resistive Network u Encoder n Resolution is limited u Large number of comparator in IC n Homework #5-1 u 어떻게 동시에 비교가 되는지를 설명하라.

20 Chap 020 Software Implementation n Implementation with software using microprocessor u Counting u Shifting u Inverting u Code Conversion u … n Limited Practical Use u Availability of Good performance with very reasonable Cost

21 Chap 021 Shaft Encoder n Elctromechanical ADC u Convert shaft angle to digital output n Encoding u Optical or Magnetic Sensor n Applications u Machine tools, Industrial robotics, Numerical control n Binary Encoder u Misalignment of mechanism causes large error F Ex: 011  111 (180deg) n Gray Encoder u Misalignment causes 1 LSB error

22 Chap 022 Interfacing the ADC to the IBM PC n Interface Operations u Most-recent-data Scheme F At end of conversion it updates an output FIFO F Automatically start new conversion F CPU read FIFO to acquire most recent data u Start-and-wait Scheme F CPU initiate conversion every time it needs new data F CPU check EOC until conversion is finished u Using CPU Interrupt F CPU initiate conversion every time it needs new data F CPU can proceed to do other thing F ADC interrupt CPU when conversion is complete F CPU goes to ISR u See Chapter 3, For more information about 8259A

23 Chap 023 Interface Software n Memory Mapped Transfers u ADC is assigned in Memory Space F MRD, MWR signal F MOV instruction u More complex decoding logic n I/O Mapped Transfers u ADC is in I/O Space F IOR, IOW signal F IN, OUT instruction u More Simple decoding logic n DMA (Direct Memory Access) u CPU release system bus by the request of DMA u DMA controller carried out data transfer by generating the required addresses and control signals u The system bus control reverts back to CPU when data transfer is finished n DMA is useful u High Speed u High volume data transfer F Disk Drive interface

24 Chap 024 Interface Hardware n Parallel Data Format u Three state output buffer in ADC u To Interface ADC F CPU + Decoding logic To generate Chip Select signal To generate Start Signal To Check EOC signal n Serial Data Format u Asynchronous Serial transmission to send data over long distance to a monitoring station F UART is commonly used n Interfacing 10 or 12 bit ADC u Transfer data in chunks of 8 bits one after another

25 Chap 025 DAS (Data Acquisition System) n DAS performs the complete function of converting the raw outputs from one or more sensors into equivalent digital signals usable for further processing, control, or displaying applications n Applications u Simple monitoring of a single analog variable u Control and Monitoring of hundreds of parameters in a nuclear plant

26 Chap 026 Single Channel System n Transducer u Generate signal of low amplitude, mixed with undesirable noise n Amplifier, Filters u Amplify u Remove noise u Linearize n S/H (Sample and Hold) u Reduce uncertainty error in the converted output when input changes are fast compared to the conversion time u In Multi-channel system F To hold a sample from one channel while multiplexer proceed to sample next one F Simultaneous sampling of two signal

27 Chap 027 Sample and Hold Circuits n Care in selecting hold capacitor Ch u Low Value F Reduces acquisition time F Increase Droop u High Value F Minimize Droop F Increase acquisition time u Choose capacitor to get a best acquisition time while keeping the droop per conversion below 1 LSB

28 Chap 028 Commercially Available S/H

29 Chap 029 Multi-channel System n Analog multiplexer and a ADC u Low cost n Local ADCs and digital multiplexer u Higher sampling rate

30 Chap 030 How to select and use an ADC n Range of commercially available ADCs n Guidelines for using ADCs u Use the full input range of the ADC u Use a good source of reference signal u Look out for fast input signal changes u Keep analog and digital grounds separate u Minimize interference and loading problem

31 Chap 031 Commercially available monolithic ADCs

32 Chap 032 Commercially available hybrid ADCs

33 Chap 033 A low cost DAS for the IBM PC n Multi-channel system u Less than $100 u ADC0816 from National Semiconductor u Constant, repetitive rate F 1000 samples/s n Generating clock u For starting ADC conversion u For causing interrupt u Make a pulse stream from TCLK with short pulses of duration = ½ x BCLK/4 F TCLK from 8253 Timer/Counter Wide pulse

34 Chap 034 ADC circuit for PC prototype board SCSLCT (Start Conversion SeLeCT) : Latched trough port 30CH SCSLCT = H Selection of 30AH (/E10) start conversion SCSLCT = L TCLK’ start conversion INTSLCT (INTerrupt SeLeCT) : Latched trough port 30CH INTSLCT = H EOC cause IRQ2 INTSLCT = L No Interrupt CPU read Status register (Port 309H) to check EOC

35 Chap 035 Status Register n For polling TCLK and EOC signal n Port 309H (/E9) n Polling of EOC results in a low level after the data from ADC have been read

36 Chap 036 Throughput rate calculation 4.77MHz / 8 = 596KHz

37 Chap 037 Accuracy Calculation n Better than 1% accuracy is ensured n Actual accuracy with smooth input signal at room temperature will be better than 0.5%

38 Chap 038 Basic Program for Controlling ADC Sampling rate < 200 samples/s Because OUT and IN instruction in Basic takes 5ms

39 Chap 039 C Programming for Controlling ADC n Sampling from ADC channel 1 at 5ms interval and sending each sampled data point to the DAC

40 Chap 040 Homework #5-2 n Prototype board 의 회로 도를 참고하여 앞의 C program 이 수행되는 과정을 해석하라 u 예를 들면 Outp(CNTRL,5) 가 수행되면 회로도 에서 어떤 신호가 구동되는지 등 ….

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