# Embedded Systems Laboratory and Electrical Engineering Department Informatics Institute and Engineering School Federal University of Rio Grande do Sul.

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Embedded Systems Laboratory and Electrical Engineering Department Informatics Institute and Engineering School Federal University of Rio Grande do Sul Porto Alegre – RS – Brazil DFT 2006 Washington, DC, USA SET Fault Tolerant Combinational Circuits Based on Majority Logic Álisson Michels Lorenzo Petroli Carlos Lisbôa Fernanda Kastendsmidt Luigi Carro

Carlos Lisbôa DFT 2006 - October, 4-6, 2006 2 What is Wrong with TMR ? TMR does not protect against two faults affecting different modules Module 2 correct output Module 1 Module 3 wrong output VOTERVOTER VOTERVOTER correct output ? Module 1 Module 2 Module 3 correct output When a single fault occurs in the voter circuit, the voter output may be wrong

Carlos Lisbôa DFT 2006 - October, 4-6, 2006 3 Fault-tolerant analog voter transient pulse model: double exponential injection of faults no effect on voter output

Carlos Lisbôa DFT 2006 - October, 4-6, 2006 4 Use of majority gates in AOI logic majority(a, b, 0) = a.b + a.0 + b.0 = a.b (AND gate) AND gate OR gate majority(a, b, 1) = a.b + a.1 + b.1 = a.b + a + b = a + b (OR gate) inverter the analog comparator can be used as a fault-tolerant inverter

Carlos Lisbôa DFT 2006 - October, 4-6, 2006 5 Sample implementation: full adder Classic TMR implementation: -3 standard AOI full adder modules -1 digital voter per output bit Proposed solution: -single full adder module -majority gates used to implement AND/OR functions -analog comparators used to implement majority gates and inverters

Carlos Lisbôa DFT 2006 - October, 4-6, 2006 6 Area Comparison (32 nm technology) The proposed solution brings a 36% reduction in area, when compared to the classic TMR implementation

Carlos Lisbôa DFT 2006 - October, 4-6, 2006 7 For more details, come and see the poster ! Contact: calisboa@inf.ufrgs.br Thank You !

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