1. Digital System Design Verilog ® HDL Behavioral Modeling (3) Maziar Goudarzi

2. Objectives of This Topic Verilog® Scheduling Semantics – Internal sequence of operations of a Verilog simulator 2011DSD2

3. Verilog® Scheduling Semantics Verilog is a parallel programming language Important to understand – What execution order is guaranteed – What execution order is indeterminate Language semantics are defined for simulation – Other uses (e.g. synthesis) are abstracted from this definition 2011DSD3 Reference: IEEE Standard 1364-2005, IEEE Standard for Verilog®

4. Verilog® Scheduling Semantics Definitions: – Update operation/event: every change in value of a net or variable in the circuit being simulated, as well as the named event. Processes are sensitive to update events – Evaluation operation: The evaluation of a process (initial/always block) is known as evaluation operation When an update event is executed, all the processes that are sensitive to that event, are evaluated in an arbitrary order. 2011DSD4 NOTE: Verilog standard calls these Update Event and Evaluate Event. We use Operation word instead of Event to avoid confusion with event (change of value)

5. Verilog® Scheduling Semantics Definitions (cont’d) – Time, or Simulation time: The time value maintained by the simulator to model the actual time it would take for the circuit being simulated – Operation queue: Operations occur at different times. They are kept on an operation queue ordered by simulation time – Scheduling an operation: Putting an operation on an operation queue 2011DSD5

6. Verilog® Scheduling Semantics Operation queues in Verilog – 5 queues. – Operations are added to any of them, but removed only from the active queue 1.Active operations Q 2.Inactive operations Q 3.Non-blocking operations Q 4.Monitor operations Q 5.Future operations Q Definitions: Simulation cycle: Processing of all active operations 2011DSD6

7. Verilog® Events in Priority Order 1.Active operations: occur at the current simulation time. Can be processed in any order. – Example: ordinary assignments: a=b; 2.Inactive operations: occur at the current simulation time. Processed after all operations 1 above. – Example: Zero-delay assignments: #0 a=b; 3.Non-blocking assign update operations: evaluated during some previous simulation time, but shall be assigned at this simulation time after all 1 and 2 above. – Example: Non-blocking assignments: a<=b 2011DSD7

8. Verilog® Events in Priority Order 4.Monitor operations: Processed after all above. – Example: $monitor and $strobe system tasks – Re-enabled in every successive time step – Unique: cannot create other events 5.Future operations: occur at some future simulation time. – Further divided into future inactive events and future non-blocking assignment update events. 2011DSD8

9. Verilog® Simulation Reference Model while (there are operations) { if (no active operations) { if (there are inactive operations) { activate all inactive operations; } else if (there are nonblocking assign update operations){ activate all nonblocking assign update operations; } else if (there are monitor operations) { activate all monitor operations; } else { advance T to the time of next operation; activate all inactive operations for time T; } } // end of “if (no active events)” // continued on next page... 2011DSD9

10. Verilog® Simulation Reference Model // Rest of “while (there are operations) {“ E = any active operation; if (E is an update operation) { update the modified object; add evaluation operations for sensitive processes to operation queue; } else { /* shall be an evaluation operation */ evaluate the process; add update operations to the operations queue; } } // “while (there are operations) {“ 2011DSD10

11. Determinism Order of appearance in the begin-end block is preserved – Execution of statements within one begin-end block may be suspended, but never the order is changed Nonblocking assignments shall be performed in the order the statements were executed. initial begin a <= 0; a <= 1; end 2011DSD11

12. Nondeterminism Active operations are processed in undefined order Statements in different initial/always blocks may intermix during execution 2011DSD12

13. Have you learned this topic? Verilog simulation semantics – How Verilog manages the simulation – What is expected to happen/not-happen during simulation 2011DSD13