Presentation on theme: "Challenges and Opportunities for System Software in the Multi-Core Era or The Sky is Falling, The Sky is Falling!"— Presentation transcript:
Challenges and Opportunities for System Software in the Multi-Core Era or The Sky is Falling, The Sky is Falling!
Challenge: scaling Scaling software –Virtual Machine Monitors (easy) –Operating Systems (hard) –Applications (hardest) Scaling hardware –Memory bandwidth –I/O bandwidth Prediction: mainstream will remain < 100 cores for next 5 years. Lack of applications, Amdahl’s law and power efficiency constraints.
Challenge: scheduling Too expensive to context switch –gang scheduling many cores inefficient –disruptive to application Complex resource hierarchy –cache, memory, I/O Opportunity: VMM and OS schedulers will have to understand and schedule complex hierarchies Prediction: partitioning cores rather than time sharing will be the norm
Challenge: isolation Fault isolation and recovery –Large transistor count cores will fail Performance isolation –Shared resources, e.g., caches, I/O bandwidth Opportunity: –Build fault containment mechanisms into the system architecture –Provide resource reservation controls –System software must handle and recover from faults, enforce performance isolation –Virtualization makes physical machines stateless and interchangeable
Challenge: distance Off-chip resources get farther and farther –Latency-bound applications suffer –I/O becomes even more heavy-weight Opportunity –Bring communication closer to the cores –Rethink I/O architectures Prediction –We will see on-chip I/O controllers and buses
Opportunity: assists Extra cores can be used for –I/O processing –self monitoring Specialized cores –computation (conventional and stream) –communication (TCP processing) –graphics processing (GPU elements) System software to take advantage of these resources
Opportunity: virtualization Killer app for multi-core –Easier to scale job-level parallelism Power efficiency –Scale each application to maximize performance per watt Hide complex hardware topology