Presentation on theme: "Reconfigurable Computing CS294-6 Fall 1998 Dr. Andre DeHon."— Presentation transcript:
Reconfigurable Computing CS294-6 Fall 1998 Dr. Andre DeHon
This Class is About Reconfigurable Computing Computer Architecture Coping with Change
Outline What’s wrong with the status quo (Admin break: handouts) Reconfigurable Computing: What and Why (break) What this class is about
Big Idea The Biggest Idea here is perhaps the simplest: When we have 1000x the resources, we design computer differently. (Good architecture depends on costs.)
Fountainhead Pathenon Quote “Look,” said Roark. “The famous flutings on the famous columns---what are they there for? To hide the joints in wood---when columns were made of wood, only these aren’t, they’re marble. The triglyphs, what are they? Wood. Wooden beams, the way they had to be laid when people began to build wooden shacks. Your Greeks took marble and they made copies of their wooden structures out of it, because others had done it that way. Then your masters of the Renaissance came along and made copies in plaster of copies in marble of copies in wood. Now here we are making copies in steel and concrete of copies in plaster of copies in marble of copies in wood. Why?
What About Computer Architecture? Are we making copies in submicron CMOS VLSI of copies in NMOS of copies in TTL of early vacuum tube computer designs? Mainframe->Mini->super microprocessors ? CDC->Cray1->i860->Vector microprocessors?
1983 Computer Architecture VLSI is “new” to the computer architect you have 15M in 4 m NMOS want to run “all” programs What do you build? 2
What can we build in 15M 12Kb SRAM (1.2K bit) 1500 Gate-Array Gates (10K /gate) 30 4-LUTs (500K /4LUT) 32b ALU+RF+control 2 2 2 2
Challenging our Assumptions General-purpose computing machines don’t have to look like processors. 1000x increase in single-chip silicon capacity changes the underlying design costs.
Early RC Successes Fastest RSA implementation is on a reconfigurable machine (DEC PAM) Splash2 (SRC) performs DNA Sequence matching 300x Cray2 speed, and 200x a 16K CM2 Many modern processors and ASICs are verified using FPGA emulation systems For many signal processing/filtering operations, single chip FPGAs outperform DSPs by 10-100x.
What is Configurable Computing? Short answer: Computing via post-fabrication, spatially programmed connection of processing elements.
Defining Terms Computes one function (e.g. FP- multiply, divider, DCT) Function defined at fabrication time Computes “any” computable function (e.g. Processor, DSPs, FPGAs) Function defined after fabrication Fixed Function: Programmable:
“Any” Computation? (Universality) Any computation which can “fit” on the programmable substrate Limitations: hold entire computation and intermediate data Recall size/fit constraint
Benefits of Programmable Non-permanent customization and application development after fabrication economies of scale (amortize large, fixed design costs) time-to-market (evolving requirements and standards, new ideas)
Distinction in Instruction Binding Time Fabrication time --> Fixed function devices Beginning of product use --> Actel/Quicklogic FPGAs Beginning of usage epoch --> Reconfigurable FPGAs Every cycle --> traditional RISC processors
Spatial vs. Temporal Computing Spatial Temporal
Configurable Drawbacks Each compute/interconnect resource dedicated to single function Must dedicate resources for every computational subtask Infrequently needed portions of a computation sit idle --> inefficient use of resources
Where CC interesting? Regular applications -- need same operation repeatedly High concurrency -- large number of operations can occur simultaneously Fine-grained data -- small operand data widths
Implications? Post-fabrication programmable computing space >> processor arch. With 10G dies now and 1T on the horizon, a much wider space of computing architectures opens up. Major feature: more spatial processing, less multiplexing/sharing of resources. 22
This Class Good Architecture is driven by media costs Technology advances --> Costs change What makes sense now, in the near future Theme: watch for/make note of where cost assumptions drive architecture Be prepared to re-evaluate/review your solutions
Another Quote An organization must have some means of combating the process by which people become prisoners of their procedures. The rule book becomes fatter as the ideas become fewer. Almost every well established organization is a coral reef of procedures that were laid down to achieve some long-forgotten objective. -- John W. Gardner Some would argue computer architecture is falling prey to this phenomenon.
Who Course for? Programmable Architects (FPGA, processor, etc.) ASIC/ASP architects System designers who may use any of above
What’s it about? Architectures for late-bound computing systems Emphasis on spatial computing Re-exam what goes into these architectures and why Build up tools, techniques, and intuition for the architect and system designer
Topics Instructions Interconnect Compute elements Retiming Specialization Control Allocation Costs Comparisons Modeling Mapping Architecture Components Related Issues
Class Requirements Participation (reading, class discussion) [20%] Weekly exercises [60%] Project Summary [20%] No tests/final
Exercises 4 common/intro 7 “project” -- explore architecture issues from class for a particular application kernel Grade best 9 of 11 Please try all Use HSRA as starting point architecture
Intro Exercises Spatial Compute -- high throughput multiply Special/Spatial -- FIR Cycle -- IIR Area-Time -- AT for above
Project Exercises Kernels selected from Multimedia benchmark set (likely JPEG, GSM, ADPCM, maybe rendering…) Each student has different kernel (together look at variance in application requirements) Different aspect of focus each week
Project Components Analyze sequential version Spatial implementation Interconnect requirements Retiming requirements Power implications Specialization opportunities and impact Programming
Project Report Summarize lessons for some component/feature across class project results E.g. Power, AT, Interconnect
Next Time FPGA/HSRA introduction Take a look at reading HSRA for projects