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Essentials of Testing Vishwani D. Agrawal

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1 Essentials of Testing Vishwani D. Agrawal
Agere Systems, Murray Hill, NJ 47974 Michael L. Bushnell ECE Dept., Rutgers University Piscataway, NJ 08854 Presented at the VLSI Test Symposium 2001 April 29, 2001 Essentials of Test: Agrawal & Bushnell

2 Part I INTRODUCTION TO TESTING
April 29, 2001 Essentials of Test: Agrawal & Bushnell

3 VLSI Realization Process
Customer’s need Determine requirements Write specifications Design synthesis and Verification Test development Fabrication Manufacturing test Chips to customer April 29, 2001 Essentials of Test: Agrawal & Bushnell

4 Essentials of Test: Agrawal & Bushnell
Definitions Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect. April 29, 2001 Essentials of Test: Agrawal & Bushnell

5 Essentials of Test: Agrawal & Bushnell
Real Tests Based on analyzable fault models, which may not map on real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level. April 29, 2001 Essentials of Test: Agrawal & Bushnell

6 Essentials of Test: Agrawal & Bushnell
Costs of Testing Design for testability (DFT) Chip area overhead and yield reduction Performance overhead Software processes of test Test generation and fault simulation Test programming and debugging Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost April 29, 2001 Essentials of Test: Agrawal & Bushnell

7 Present and Future* Feature size (micron) Transistors/sq. cm M M Pin count Clock rate (MHz) Power (Watts) * SIA Roadmap, IEEE Spectrum, July 1999 April 29, 2001 Essentials of Test: Agrawal & Bushnell

8 Cost of Manufacturing Testing in 2000AD
GHz, analog instruments,1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second April 29, 2001 Essentials of Test: Agrawal & Bushnell

9 Essentials of Test: Agrawal & Bushnell
Course Outline Part I: Basic concepts and definitions Test process and ATE Test economics and product quality Fault modeling Part II: Logic and fault simulation Combinational circuit ATPG Sequential circuit ATPG Memory test Analog test Delay test and IDDQ test Part III: Scan design BIST Boundary scan and analog test bus System test and core-based design April 29, 2001 Essentials of Test: Agrawal & Bushnell

10 VLSI Testing Process and Equipment
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11 Essentials of Test: Agrawal & Bushnell
Testing Principle April 29, 2001 Essentials of Test: Agrawal & Bushnell

12 Automatic Test Equipment Components
Consists of: Powerful computer Powerful 32-bit Digital Signal Processor (DSP) for analog testing Test Program (written in high-level language) running on the computer Probe Head (actually touches the bare or packaged chip to perform fault detection experiments) Probe Card or Membrane Probe (contains electronics to measure signals on chip pin or pad) April 29, 2001 Essentials of Test: Agrawal & Bushnell

13 Characterization Test
Worst-case test Choose test that passes/fails chips Select statistically significant sample of chips Repeat test for every combination of 2+ environmental variables Plot results in Schmoo plot Diagnose and correct design errors Continue throughout production life of chips to improve design and process to increase yield April 29, 2001 Essentials of Test: Agrawal & Bushnell

14 Essentials of Test: Agrawal & Bushnell
Schmoo Plot April 29, 2001 Essentials of Test: Agrawal & Bushnell

15 Essentials of Test: Agrawal & Bushnell
Manufacturing Test Determines whether manufactured chip meets specs Must cover high % of modeled faults Must minimize test time (to control cost) No fault diagnosis Tests every device on chip Test at speed of application or speed guaranteed by supplier April 29, 2001 Essentials of Test: Agrawal & Bushnell

16 Essentials of Test: Agrawal & Bushnell
Burn-in or Stress Test Process: Subject chips to high temperature & over-voltage supply, while running production tests Catches: Infant mortality cases – these are damaged chips that will fail in the first 2 days of operation – causes bad devices to actually fail before chips are shipped to customers Freak failures – devices having same failure mechanisms as reliable devices April 29, 2001 Essentials of Test: Agrawal & Bushnell

17 Types of Manufacturing Tests
Wafer sort or probe test – done before wafer is scribed and cut into chips Includes test site characterization – specific test devices are checked with specific patterns to measure: Gate threshold Polysilicon field threshold Poly sheet resistance, etc. Packaged device tests April 29, 2001 Essentials of Test: Agrawal & Bushnell

18 Essentials of Test: Agrawal & Bushnell
Sub-types of Tests Parametric – measures electrical properties of pin electronics – delay, voltages, currents, etc. – fast and cheap Functional – used to cover very high % of modeled faults – test every transistor and wire in digital circuits – long and expensive – main topic of tutorial April 29, 2001 Essentials of Test: Agrawal & Bushnell

19 Two Different Meanings of Functional Test
ATE and Manufacturing World – any vectors applied to cover high % of faults during manufacturing test Automatic Test-Pattern Generation World – testing with verification vectors, which determine whether hardware matches its specification – typically have low fault coverage (< 70 %) April 29, 2001 Essentials of Test: Agrawal & Bushnell

20 Test Specifications & Plan
Functional Characteristics Type of Device Under Test (DUT) Physical Constraints – Package, pin numbers, etc. Environmental Characteristics – supply, temperature, humidity, etc. Reliability – acceptance quality level (defects/million), failure rate, etc. Test plan generated from specifications Type of test equipment to use Types of tests Fault coverage requirement April 29, 2001 Essentials of Test: Agrawal & Bushnell

21 Essentials of Test: Agrawal & Bushnell
ADVANTEST Model T6682 ATE April 29, 2001 Essentials of Test: Agrawal & Bushnell

22 Essentials of Test: Agrawal & Bushnell
LTX FUSION HF ATE April 29, 2001 Essentials of Test: Agrawal & Bushnell

23 Essentials of Test: Agrawal & Bushnell
Summary Parametric tests – determine whether pin electronics system meets digital logic voltage, current, and delay time specs Functional tests – determine whether internal logic/analog sub-systems behave correctly ATE Cost Problems Pin inductance (expensive probing) Multi-GHz frequencies High pin count (1024) ATE Cost Reduction Multi-Site Testing DFT methods like Built-In Self-Test April 29, 2001 Essentials of Test: Agrawal & Bushnell

24 Test Economics and Product Quality
April 29, 2001 Essentials of Test: Agrawal & Bushnell

25 Economics of Design for Testability (DFT)
Consider life-cycle cost; DFT on chip may impact the costs at board and system levels. Weigh costs against benefits Cost examples: reduced yield due to area overhead, yield loss due to non-functional tests Benefit examples: Reduced ATE cost due to self-test, inexpensive alternatives to burn-in test April 29, 2001 Essentials of Test: Agrawal & Bushnell

26 Benefits and Costs of DFT
Design and test + / - Fabri- cation + Manuf. Test - Level Chips Boards System Maintenance test Diagnosis and repair Service interruption + Cost increase - Cost saving +/- Cost increase may balance cost reduction April 29, 2001 Essentials of Test: Agrawal & Bushnell

27 VLSI Chip Yield A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. Cost of a chip: Cost of fabricating and testing a wafer Yield x Number of chip sites on the wafer April 29, 2001 Essentials of Test: Agrawal & Bushnell

28 Defect Level or Reject Ratio
Defect level (DL) is the ratio of faulty chips among the chips that pass tests. DL is measured as parts per million (ppm). DL is a measure of the effectiveness of tests. DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable. April 29, 2001 Essentials of Test: Agrawal & Bushnell

29 Essentials of Test: Agrawal & Bushnell
Determination of DL From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL. From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL. April 29, 2001 Essentials of Test: Agrawal & Bushnell

30 Modified Yield Equation
Three parameters: Fault density, f = average number of stuck-at faults per unit chip area Fault clustering parameter, b Stuck-at fault coverage, T The modified yield equation: Y (T ) = (1 + TAf / b) - b Assuming that tests with 100% fault coverage (T =1.0) remove all faulty chips, Y = Y (1) = (1 + Af / b) - b April 29, 2001 Essentials of Test: Agrawal & Bushnell

31 Essentials of Test: Agrawal & Bushnell
Defect Level Y (T ) - Y (1) DL (T ) = Y (T ) ( b + TAf ) b = ( b + Af ) b Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, b is the fault clustering parameter. Af and b are determined by test data analysis. April 29, 2001 Essentials of Test: Agrawal & Bushnell

32 Example: SEMATECH Chip
Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont 116,000 equivalent (2-input NAND) gates 304-pin package, 249 I/O Clock: 40MHz, some parts 50MHz 0.45m CMOS, 3.3V, 9.4mm x 8.8mm area Full scan, 99.79% fault coverage Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock Data obtained courtesy of Phil Nigh (IBM) April 29, 2001 Essentials of Test: Agrawal & Bushnell

33 Test Coverage from Fault Simulator
Stuck-at fault coverage Vector number April 29, 2001 Essentials of Test: Agrawal & Bushnell

34 Essentials of Test: Agrawal & Bushnell
Measured Chip Fallout Measured chip fallout Vector number April 29, 2001 Essentials of Test: Agrawal & Bushnell

35 Essentials of Test: Agrawal & Bushnell
Model Fitting Chip fallout vs. fault coverage Y (1) = Chip fallout and computed 1-Y (T ) Measured chip fallout Y (T ) for Af = 2.1 and b = 0.083 Stuck-at fault coverage, T April 29, 2001 Essentials of Test: Agrawal & Bushnell

36 Essentials of Test: Agrawal & Bushnell
Computed DL 237,700 ppm (Y = 76.23%) Defect level in ppm Stuck-at fault coverage (%) April 29, 2001 Essentials of Test: Agrawal & Bushnell

37 Essentials of Test: Agrawal & Bushnell
Summary VLSI yield depends on two process parameters, defect density (d ) and clustering parameter (a) Yield drops as chip area increases; low yield means high cost Fault coverage measures the test quality Defect level (DL) or reject ratio is a measure of chip quality DL can be determined by an analysis of test data For high quality: DL < 500 ppm, fault coverage ~ 99% April 29, 2001 Essentials of Test: Agrawal & Bushnell

38 Essentials of Test: Agrawal & Bushnell
Fault Modeling April 29, 2001 Essentials of Test: Agrawal & Bushnell

39 Essentials of Test: Agrawal & Bushnell
Why Model Faults? I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments April 29, 2001 Essentials of Test: Agrawal & Bushnell

40 Some Real Defects in Chips
Processing defects Missing contact windows Parasitic transistors Oxide breakdown . . . Material defects Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) Time-dependent failures Dielectric breakdown Electromigration Packaging failures Contact degradation Seal leaks Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981. April 29, 2001 Essentials of Test: Agrawal & Bushnell

41 Observed PCB Defects Defect classes Occurrence frequency (%) Shorts 51
Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Occurrence frequency (%) 51 1 6 13 8 5 Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985. April 29, 2001 Essentials of Test: Agrawal & Bushnell

42 Essentials of Test: Agrawal & Bushnell
Common Fault Models Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults For more examples, see Section 4.4 (p ) of the book. April 29, 2001 Essentials of Test: Agrawal & Bushnell

43 Essentials of Test: Agrawal & Bushnell
Single Stuck-at Fault Three properties define a single stuck-at fault Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value c j 0(1) s-a-0 a d 1(0) g 1 h z i 1 b e 1 k f Test vector for h s-a-0 fault April 29, 2001 Essentials of Test: Agrawal & Bushnell

44 Essentials of Test: Agrawal & Bushnell
Fault Equivalence Number of fault sites in a Boolean gate circuit = #PI + #gates + #(fanout branches). Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. Fault collapsing: All single faults of a logic circuits can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset. April 29, 2001 Essentials of Test: Agrawal & Bushnell

45 Essentials of Test: Agrawal & Bushnell
Equivalence Rules sa0 sa0 sa0 sa1 sa0 sa1 sa1 sa1 WIRE AND OR sa0 sa1 NOT sa1 sa0 sa0 sa1 sa0 sa1 sa0 sa1 sa0 NAND NOR sa1 sa0 sa0 sa1 sa1 sa0 sa1 FANOUT April 29, 2001 Essentials of Test: Agrawal & Bushnell

46 Essentials of Test: Agrawal & Bushnell
Equivalence Example sa0 sa1 Faults in red removed by equivalence collapsing sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = = 0.625 32 April 29, 2001 Essentials of Test: Agrawal & Bushnell

47 Essentials of Test: Agrawal & Bushnell
Fault Dominance If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1. Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list. When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. See the next example. In a tree circuit (without fanouts) PI faults form a dominance collaped fault set. If two faults dominate each other then they are equivalent. April 29, 2001 Essentials of Test: Agrawal & Bushnell

48 Essentials of Test: Agrawal & Bushnell
Dominance Example All tests of F2 F1 s-a-1 001 000 101 100 s-a-1 F2 011 Only test of F1 s-a-1 s-a-1 s-a-1 s-a-0 A dominance collapsed fault set April 29, 2001 Essentials of Test: Agrawal & Bushnell

49 Essentials of Test: Agrawal & Bushnell
Checkpoints Primary inputs and fanout branches of a combinational circuit are called checkpoints. Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ) = 10 April 29, 2001 Essentials of Test: Agrawal & Bushnell

50 Classes of Stuck-at Faults
Following classes of single stuck-at faults are identified by fault simulators: Potentially-detectable fault -- Test produces an unknown (X) state at PO; detection is probabilistic, usually with 50% probability. Initialization fault -- Fault prevents initialization of the faulty circuit; can be detected as a potentially-detectable fault. Hyperactive fault -- Fault induces much internal signal activity without reaching PO. Redundant fault -- No test exists for the fault. Untestable fault -- Test generator is unable to find a test. April 29, 2001 Essentials of Test: Agrawal & Bushnell

51 Essentials of Test: Agrawal & Bushnell
Summary Fault models are analyzable approximations of defects and are essential for a test methodology. For digital logic single stuck-at fault model offers best advantage of tools and experience. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. Stuck-short and delay faults and technology-dependent faults require special tests. Memory and analog circuits need other specialized fault models and tests. April 29, 2001 Essentials of Test: Agrawal & Bushnell

52 Part II TEST METHODS Logic Simulation
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53 Essentials of Test: Agrawal & Bushnell
Simulation Defined Definition: Simulation refers to modeling of a design, its function and performance. A software simulator is a computer program; an emulator is a hardware simulator. Simulation is used for design verification: Validate assumptions Verify logic Verify performance (timing) Types of simulation: Logic or switch level Timing Circuit Fault April 29, 2001 Essentials of Test: Agrawal & Bushnell

54 Simulation for Verification
Specification Synthesis Response analysis Design changes Design (netlist) Computed responses True-value simulation Input stimuli April 29, 2001 Essentials of Test: Agrawal & Bushnell

55 Modeling for Simulation
Modules, blocks or components described by Input/output (I/O) function Delays associated with I/O signals Examples: binary adder, Boolean gates, FET, resistors and capacitors Interconnects represent ideal signal carriers, or ideal electrical conductors Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy. April 29, 2001 Essentials of Test: Agrawal & Bushnell

56 Essentials of Test: Agrawal & Bushnell
Example: A Full-Adder a b c d e f HA HA; inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e); FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry); HA1 HA2 A B C D E F Sum Carry April 29, 2001 Essentials of Test: Agrawal & Bushnell

57 Logic Model of MOS Circuit
VDD pMOS FETs a Da Dc c a Ca b Db c Cc b Da and Db are interconnect or propagation delays Dc is inertial delay of gate Cb nMOS FETs Ca , Cb and Cc are parasitic capacitances April 29, 2001 Essentials of Test: Agrawal & Bushnell

58 Options for Inertial Delay (simulation of a NAND gate)
Transient region a Inputs b c (CMOS) c (zero delay) c (unit delay) Logic simulation X c (multiple delay) rise=5, fall=5 Unknown (X) c (minmax delay) min =2, max =5 Time units 5 April 29, 2001 Essentials of Test: Agrawal & Bushnell

59 Essentials of Test: Agrawal & Bushnell
Signal States Two-states (0, 1) can be used for purely combinational logic with zero-delay. Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization. Four-states (0, 1, X, Z) are essential for MOS devices. See example below. Analog signals are used for exact timing of digital logic and for analog circuits. Z (hold previous value) April 29, 2001 Essentials of Test: Agrawal & Bushnell

60 Essentials of Test: Agrawal & Bushnell
Modeling Levels Modeling level Function, behavior, RTL Logic Switch Timing Circuit Circuit description Programming language-like HDL Connectivity of Boolean gates, flip-flops and transistors Transistor size and connectivity, node capacitances Transistor technology data, connectivity, Tech. Data, active/ passive component connectivity Signal values 0, 1 0, 1, X and Z and X Analog voltage voltage, current Timing Clock boundary Zero-delay unit-delay, multiple- delay Fine-grain timing Continuous time Application Architectural and functional verification Logic and test Timing Digital timing and analog circuit April 29, 2001 Essentials of Test: Agrawal & Bushnell

61 True-Value Simulation Algorithms
Compiled-code simulation Applicable to zero-delay combinational logic Also used for cycle-accurate synchronous sequential circuits for logic verification Efficient for highly active circuits, but inefficient for low-activity circuits High-level (e.g., C language) models can be used Event-driven simulation Only gates or modules with input events are evaluated (event means a signal change) Delays can be accurately simulated for timing verification Efficient for low-activity circuits Can be extended for fault simulation April 29, 2001 Essentials of Test: Agrawal & Bushnell

62 Compiled-Code Algorithm
Step 1: Levelize combinational logic and encode in a compilable programming language Step 2: Initialize internal state variables (flip-flops) Step 3: For each input vector Set primary input variables Repeat (until steady-state or max. iterations) Execute compiled code Report or save computed variables April 29, 2001 Essentials of Test: Agrawal & Bushnell

63 Event-Driven Algorithm (Example)
Scheduled events c = 0 d = 1, e = 0 g = 0 f = 1 g = 1 Activity list d, e f, g g a =1 e =1 t = 0 1 2 3 4 5 6 7 8 2 c = g =1 2 2 d = 0 4 f =0 b =1 Time stack g 4 8 Time, t April 29, 2001 Essentials of Test: Agrawal & Bushnell

64 Efficiency of Event-driven Simulator
Simulates events (value changes) only Speed up over compiled-code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change Steady 0 0 to 1 event Large logic block without activity Steady 0 (no event) April 29, 2001 Essentials of Test: Agrawal & Bushnell

65 Essentials of Test: Agrawal & Bushnell
Summary Logic or true-value simulators are essential tools for design verification. Verification vectors and expected responses are generated (often manually) from specifications. A logic simulator can be implemented using either compiled-code or event-driven method. Per vector complexity of a logic simulator is approximately linear in circuit size. Modeling level determines the evaluation procedures used in the simulator. April 29, 2001 Essentials of Test: Agrawal & Bushnell

66 Essentials of Test: Agrawal & Bushnell
Fault Simulation April 29, 2001 Essentials of Test: Agrawal & Bushnell

67 Problem and Motivation
Fault simulation Problem: Given A circuit A sequence of test vectors A fault model Determine Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults Motivation Determine test quality and in turn product quality Find undetected fault targets to improve tests April 29, 2001 Essentials of Test: Agrawal & Bushnell

68 Fault simulator in a VLSI Design Process
Verification input stimuli Verified design netlist Fault simulator Test vectors Modeled fault list Remove tested faults Test compactor Delete vectors Fault coverage ? Low Test generator Add vectors Adequate Stop April 29, 2001 Essentials of Test: Agrawal & Bushnell

69 Fault Simulation Scenario
Circuit model: mixed-level Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals High-level models (memory, etc.) with pin faults Signal states: logic Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits Four states (0, 1, X, Z) for sequential MOS circuits Timing: Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback April 29, 2001 Essentials of Test: Agrawal & Bushnell

70 Fault Simulation Scenario (continued)
Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use Equivalence fault collapsing of single stuck-at faults Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis Fault sampling -- a random sample of faults is simulated when the circuit is large April 29, 2001 Essentials of Test: Agrawal & Bushnell

71 Fault Simulation Algorithms
Serial Parallel Deductive Concurrent Differential April 29, 2001 Essentials of Test: Agrawal & Bushnell

72 Essentials of Test: Agrawal & Bushnell
Serial Algorithm Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list: Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses with saved responses If response differs, report fault detection and suspend simulation of remaining vectors Advantages: Easy to implement; needs only a true-value simulator, less memory Most faults, including analog faults, can be simulated April 29, 2001 Essentials of Test: Agrawal & Bushnell

73 Serial Algorithm (Cont.)
Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits Alternative: Simulate many faults together Test vectors Fault-free circuit Comparator f1 detected? Circuit with fault f1 Comparator f2 detected? Circuit with fault f2 Comparator fn detected? Circuit with fault fn April 29, 2001 Essentials of Test: Agrawal & Bushnell

74 Parallel Fault Simulation
Compiled-code method; best with two-states (0,1) Exploits inherent bit-parallelism of logic operations on computer words Storage: one word per line for two-state simulation Multi-pass simulation: Each pass simulates w-1 new faults, where w is the machine word length Speed up over serial method ~ w-1 Not suitable for circuits with timing-critical and non-Boolean logic April 29, 2001 Essentials of Test: Agrawal & Bushnell

75 Parallel Fault Sim. Example
Bit 0: fault-free circuit Bit 1: circuit with c s-a-0 Bit 2: circuit with f s-a-1 c s-a-0 detected a b e c s-a-0 g d f s-a-1 April 29, 2001 Essentials of Test: Agrawal & Bushnell

76 Deductive Fault Simulation
One-pass simulation Each line k contains a list Lk of faults detectable on k Following true-value simulation of each vector, fault lists of all gate output lines are updated using set-theoretic rules, signal values, and gate input fault lists PO fault lists provide detection data Limitations: Set-theoretic rules difficult to derive for non-Boolean gates Gate delays are difficult to use April 29, 2001 Essentials of Test: Agrawal & Bushnell

77 Concurrent Fault Simulation
Event-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault-free circuit. A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any. All events of fault-free and all faulty circuits are implicitly simulated. Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility.) Faster than other methods, but uses most memory. April 29, 2001 Essentials of Test: Agrawal & Bushnell

78 Essentials of Test: Agrawal & Bushnell
Conc. Fault Sim. Example a0 b0 c0 e0 1 1 1 1 1 a 1 1 1 e b 1 c 1 1 g 1 a0 b0 c0 e0 d f 1 1 1 1 b0 d0 f1 g0 1 f1 d0 1 1 April 29, 2001 Essentials of Test: Agrawal & Bushnell

79 Essentials of Test: Agrawal & Bushnell
Fault Sampling A randomly selected subset (sample) of faults is simulated. Measured coverage in the sample is used to estimate fault coverage in the entire circuit. Advantage: Saving in computing resources (CPU time and memory.) Disadvantage: Limited data on undetected faults. April 29, 2001 Essentials of Test: Agrawal & Bushnell

80 Essentials of Test: Agrawal & Bushnell
Random Sampling Model Detected fault Undetected fault All faults with a fixed but unknown coverage Random picking Np = total number of faults (population size) C = fault coverage (unknown) Ns = sample size Ns << Np c = sample coverage (a random variable) April 29, 2001 Essentials of Test: Agrawal & Bushnell

81 Probability Density of Sample Coverage, c
(x--C )2 s 2 p (x ) = Prob(x < c < x +dx ) = e s (2 p) 1/2 C (1 - C) Variance, s 2 = Ns Sampling error s s p (x ) Mean = C x C -3s x C +3s 1.0 C Sample coverage April 29, 2001 Essentials of Test: Agrawal & Bushnell

82 Essentials of Test: Agrawal & Bushnell
Sampling Error Bounds C (1 - C ) | x - C | = 3 [ ] 1/2 Ns Solving the quadratic equation for C, we get the 3-sigma (99.7% confidence) estimate: 4.5 C 3s = x [ Ns x (1 - x )]1/2 Ns Where Ns is sample size and x is the measured fault coverage in the sample. Example: A circuit with 39,096 faults has an actual fault coverage of 87.1%. The measured coverage in a random sample of 1,000 faults is 88.7%. The above formula gives an estimate of 88.7% 3%. CPU time for sample simulation was about 10% of that for all faults. April 29, 2001 Essentials of Test: Agrawal & Bushnell

83 Essentials of Test: Agrawal & Bushnell
Summary Fault simulator is an essential tool for test development. Concurrent fault simulation algorithm offers the best choice. For restricted class of circuits (combinational and synchronous sequential with only Boolean primitives), differential algorithm can provide better speed and memory efficiency (Section ) For large circuits, the accuracy of random fault sampling only depends on the sample size (1,000 to 2,000 faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator. April 29, 2001 Essentials of Test: Agrawal & Bushnell

84 Combinational Automatic Test-pattern Generation
April 29, 2001 Essentials of Test: Agrawal & Bushnell

85 Functional vs. Structural ATPG
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86 Essentials of Test: Agrawal & Bushnell
Carry Circuit April 29, 2001 Essentials of Test: Agrawal & Bushnell

87 Functional vs. Structural (Continued)
Functional ATPG – generate complete set of tests for circuit input-output combinations 129 inputs, 65 outputs: 2129 = 680,564,733,841,876,926,926,749, 214,863,536,422,912 patterns Using 1 GHz ATE, would take 2.15 x 1022 years Structural test: No redundant adder hardware, 64 bit slices Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests) Takes s on 1 GHz ATE Designer gives small set of functional tests – augment with structural tests to boost coverage to 98+ % April 29, 2001 Essentials of Test: Agrawal & Bushnell

88 Definition of Automatic Test-Pattern Generator
Operations on digital hardware: Inject fault into circuit modeled in computer Use various ways to activate and propagate fault effect through hardware to circuit output Output flips from expected to faulty signal Electron-beam (E-beam) test observes internal signals – “picture” of nodes charged to 0 and 1 in different colors Too expensive Scan design – add test hardware to all flip-flops to make them a giant shift register in test mode Can shift state in, scan state out Widely used – makes sequential test combinational Costs: 5 to 20% chip area, circuit delay, extra pin, longer test sequence April 29, 2001 Essentials of Test: Agrawal & Bushnell

89 Circuit and Binary Decision Tree
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90 Algorithm Completeness
Definition: Algorithm is complete if it ultimately can search entire binary decision tree, as needed, to generate a test Untestable fault – no test for it even after entire tree searched Combinational circuits only – untestable faults are redundant, showing the presence of unnecessary hardware April 29, 2001 Essentials of Test: Agrawal & Bushnell

91 Algebras: Roth’s 5-Valued and Muth’s 9-Valued
Good Machine 1 X Failing Machine 1 X Symbol D 1 X G0 G1 F0 F1 Meaning 1/0 0/1 0/0 1/1 X/X 0/X 1/X X/0 X/1 Roth’s Algebra Muth’s Additions April 29, 2001 Essentials of Test: Agrawal & Bushnell

92 Random-Pattern Generation
Flow chart for method Use to get tests for 60-80% of faults, then switch to D-algorithm or other ATPG for rest April 29, 2001 Essentials of Test: Agrawal & Bushnell

93 Path Sensitization Method Circuit Example
Fault Sensitization Fault Propagation Line Justification April 29, 2001 Essentials of Test: Agrawal & Bushnell

94 Path Sensitization Method Circuit Example
Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i 1 D D D D 1 D 1 1 April 29, 2001 Essentials of Test: Agrawal & Bushnell

95 Path Sensitization Method Circuit Example
Try simultaneous paths f – h – k – L and g – i – j – k – L blocked at k because D-frontier (chain of D or D) disappears 1 D D 1 1 D D D April 29, 2001 Essentials of Test: Agrawal & Bushnell

96 Path Sensitization Method Circuit Example
Final try: path g – i – j – k – L – test found! D D 1 D D D 1 1 April 29, 2001 Essentials of Test: Agrawal & Bushnell

97 Computational Complexity
Ibarra and Sahni analysis – NP-Complete (no polynomial expression found for compute time, presumed to be exponential) Worst case: no_pi inputs, 2 no_pi input combinations no_ff flip-flops, 4 no_ff initial flip-flop states (good machine 0 or 1 bad machine 0 or 1) work to forward or reverse simulate n logic gates a n Complexity: O (n x 2 no_pi x 4 no_ff) April 29, 2001 Essentials of Test: Agrawal & Bushnell

98 History of Algorithm Speedups
D-ALG PODEM FAN TOPS SOCRATES Waicukauski et al. EST TRAN Recursive learning Tafertshofer et al. Est. speedup over D-ALG (normalized to D-ALG time) 1 7 23 292 ATPG System ATPG System ATPG System ATPG System 485 25057 Year 1966 1981 1983 1987 1988 1990 1991 1993 1995 1997 April 29, 2001 Essentials of Test: Agrawal & Bushnell

99 Analog Fault Modeling Impractical for Logic ATPG
Huge # of different possible analog faults in digital circuit Exponential complexity of ATPG algorithm – a 20 flip-flop circuit can take days of computing Cannot afford to go to a lower-level model Most test-pattern generators for digital circuits cannot even model at the transistor switch level (see textbook for 5 examples of switch-level ATPG) April 29, 2001 Essentials of Test: Agrawal & Bushnell

100 Fault Cone and D-frontier
Fault Cone -- Set of hardware affected by fault D-frontier – Set of gates closest to POs with fault effect(s) at input(s) Fault Cone D-frontier April 29, 2001 Essentials of Test: Agrawal & Bushnell

101 Essentials of Test: Agrawal & Bushnell
Forward Implication Results in logic gate inputs that are significantly labeled so that output is uniquely determined AND gate forward implication table: April 29, 2001 Essentials of Test: Agrawal & Bushnell

102 Essentials of Test: Agrawal & Bushnell
Backward Implication Unique determination of all gate inputs when the gate output and some of the inputs are given April 29, 2001 Essentials of Test: Agrawal & Bushnell

103 Essentials of Test: Agrawal & Bushnell
Implication Stack Push-down stack. Records: Each signal set in circuit by ATPG Whether alternate signal value already tried Portion of binary search tree already searched April 29, 2001 Essentials of Test: Agrawal & Bushnell

104 Implication Stack after Backtrack
Unexplored Present Assignment Searched and Infeasible E 1 B B 1 1 F F F 1 1 1 April 29, 2001 Essentials of Test: Agrawal & Bushnell

105 Branch-and-Bound Search
Efficiently searches binary search tree Branching – At each tree level, selects which input variable to set to what value Bounding – Avoids exploring large tree portions by artificially restricting search decision choices Complete exploration is impractical Uses heuristics April 29, 2001 Essentials of Test: Agrawal & Bushnell

106 Sequential Automatic Test-pattern Generation
April 29, 2001 Essentials of Test: Agrawal & Bushnell

107 Essentials of Test: Agrawal & Bushnell
Sequential Circuits A sequential circuit has memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output Methods of sequential circuit ATPG Time-frame expansion methods Simulation-based methods April 29, 2001 Essentials of Test: Agrawal & Bushnell

108 Concept of Time-Frames
If the test sequence for a single stuck-at fault contains n vectors, Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Vector -n+1 Vector -1 Vector 0 Fault Unknown or given Init. state State variables Next state Time- frame -n+1 Time- frame -1 Time- frame Comb. block PO -n+1 PO -1 PO 0 April 29, 2001 Essentials of Test: Agrawal & Bushnell

109 Example for Logic Systems
FF1 B A FF2 s-a-1 April 29, 2001 Essentials of Test: Agrawal & Bushnell

110 Five-Valued Logic (Roth) 0,1, D, D, X
A s-a-1 s-a-1 D D X X X FF1 FF1 X D D FF2 FF2 B X B X Time-frame -1 Time-frame 0 April 29, 2001 Essentials of Test: Agrawal & Bushnell

111 Nine-Valued Logic (Muth) 0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X
A X s-a-1 s-a-1 0/1 X/1 X 0/X 0/X FF1 FF1 X 0/1 X/1 FF2 FF2 B X B 0/1 Time-frame -1 Time-frame 0 April 29, 2001 Essentials of Test: Agrawal & Bushnell

112 Implementation of ATPG
Select a PO for fault detection based on drivability analysis. Place a logic value, 1/0 or 0/1, depending on fault type and number of inversions. Justify the output value from PIs, considering all necessary paths and adding backward time-frames. If justification is impossible, then use drivability to select another PO and repeat justification. If the procedure fails for all reachable POs, then the fault is untestable. If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, the the fault is potentially detectable. April 29, 2001 Essentials of Test: Agrawal & Bushnell

113 Complexity of ATPG Synchronous circuit -- All flip-flops controlled by clocks; PI and PO synchronized with clock: Cycle-free circuit – No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth. Cyclic circuit – Contains feedback among flip-flops: May need 9Nff time-frames, where Nff is the number of flip-flops. Asynchronous circuit – Higher complexity! Smax Time- Frame max-1 Time- Frame max-2 S3 Time- Frame -2 S2 Time- Frame -1 S1 Time- Frame S0 max = Number of distinct vectors with 9-valued elements = 9Nff April 29, 2001 Essentials of Test: Agrawal & Bushnell

114 Essentials of Test: Agrawal & Bushnell
Cycle-Free Circuits Characterized by absence of cycles among flip-flops and a sequential depth, dseq. dseq is the maximum number of flip-flops on any path between PI and PO. Both good and faulty circuits are initializable. Test sequence length for a fault is bounded by dseq + 1. April 29, 2001 Essentials of Test: Agrawal & Bushnell

115 Cycle-Free Example Circuit s - graph
2 F3 F1 3 Level = 1 F1 F2 F3 Level = 1 2 3 s - graph dseq = 3 All faults are testable. See Example 8.6. April 29, 2001 Essentials of Test: Agrawal & Bushnell

116 Cyclic Circuit Example
Modulo-3 counter Z CNT F2 F1 s - graph F1 F2 April 29, 2001 Essentials of Test: Agrawal & Bushnell

117 Essentials of Test: Agrawal & Bushnell
Modulo-3 Counter Cyclic structure – Sequential depth is undefined. Circuit is not initializable. No tests can be generated for any stuck-at fault. After expanding the circuit to 9Nff = 81, or fewer, time-frames ATPG program calls any given target fault untestable. Circuit can only be functionally tested by multiple observations. Functional tests, when simulated, give no fault coverage. April 29, 2001 Essentials of Test: Agrawal & Bushnell

118 Adding Initializing Hardware
Initializable modulo-3 counter Z CNT F2 F1 s-a-0 s-a-1 CLR s-a-1 s-a-1 Untestable fault Potentially detectable fault s - graph F1 F2 April 29, 2001 Essentials of Test: Agrawal & Bushnell

119 Essentials of Test: Agrawal & Bushnell
Benchmark Circuits Circuit PI PO FF Gates Structure Seq. depth Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2) s1196 14 18 529 Cycle-free 4 1242 1239 3 99.8 100.0 313 10 s1238 14 18 508 Cycle-free 4 1355 1283 72 94.7 100.0 3 308 15 s1488 8 19 6 653 Cyclic -- 1486 1384 2 26 76 93.1 94.8 24 525 19941 s1494 8 19 6 647 Cyclic -- 1506 1379 2 30 97 91.6 93.4 28 559 19183 April 29, 2001 Essentials of Test: Agrawal & Bushnell

120 Simulation-based ATPG
Difficulties with time-frame method: Long initialization sequence Impossible initialization with three-valued logic (Section 5.3.4) Circuit modeling limitations Timing problems – tests can cause races/hazards High complexity Inadequacy for asynchronous circuits Advantages of simulation-based methods Advanced fault simulation technology Accurate simulation model exists for verification Variety of tests – functional, heuristic, random Used since early 1960s April 29, 2001 Essentials of Test: Agrawal & Bushnell

121 Essentials of Test: Agrawal & Bushnell
Using Fault Simulator Vector source: Functional (test-bench), Heuristic (walking 1, etc.), Weighted random, random Generate new trial vectors No Trial vectors Stopping criteria (fault coverage, CPU time limit, etc.) satisfied? Yes Fault simulator Fault list Restore circuit state Update fault list New faults detected? Yes Test vectors Stop No Append vectors April 29, 2001 Essentials of Test: Agrawal & Bushnell

122 Essentials of Test: Agrawal & Bushnell
Background Seshu and Freeman, 1962, Asynchronous circuits, parallel fault simulator, single-input changes vectors. Breuer, 1971, Random sequences, sequential circuits Agrawal and Agrawal, 1972, Random vectors followed by D-algorithm, combinational circuits. Shuler, et al., 1975, Concurrent fault simulator, random vectors, sequential circuits. Parker, 1976, Adaptive random vectors, combinational circuits. Agrawal, Cheng and Agrawal, 1989, Directed search with cost-function, concurrent fault simulator, sequential circuits. Srinivas and Patnaik, 1993, Genetic algorithms; Saab, et al., 1996; Corno, et al., 1996; Rudnick, et al., 1997; Hsiao, et al., 1997. April 29, 2001 Essentials of Test: Agrawal & Bushnell

123 Genetic Algorithms (GAs)
Theory of evolution by natural selection (Darwin, ) C. R. Darwin, On the Origin of Species by Means of Natural Selection, London: John Murray, 1859. J. H. Holland, Adaptation in Natural and Artificial Systems, Ann Arbor: University of Michigan Press, 1975. D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning, Reading, Massachusetts: Addison-Wesley, 1989. P. Mazumder and E. M. Rudnick, Genetic Algorithms for VLSI Design, Layout and Test Automation, Upper Saddle River, New Jersey, Prentice Hall PTR, 1999. Basic Idea: Population improves with each generation. Population Fitness criteria Regeneration rules April 29, 2001 Essentials of Test: Agrawal & Bushnell

124 Essentials of Test: Agrawal & Bushnell
Strategate Results s s s35932 Total faults , , ,094 Detected faults , , ,100 Fault coverage % % % Test vectors , , CPU time hrs hrs hrs. HP J MB Ref.: M. S. Hsiao, E. M. Rudnick and J. H. Patel, “Dynamic State Traversal for Sequential Circuit Test Generation,” ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 5, no. 3, July 2000. April 29, 2001 Essentials of Test: Agrawal & Bushnell

125 Essentials of Test: Agrawal & Bushnell
Summary Combinational ATPG algorithms are extended: Time-frame expansion unrolls time as combinational array Nine-valued logic system Justification via backward time Cycle-free circuits: Require at most dseq time-frames Always initializable Cyclic circuits: May need 9Nff time-frames Circuit must be initializable Partial scan can make circuit cycle-free (Chapter 14) Asynchronous circuits: High complexity Low coverage and unreliable tests Simulation-based methods are more useful (Section 8.3) April 29, 2001 Essentials of Test: Agrawal & Bushnell

126 Essentials of Test: Agrawal & Bushnell
Memory Test April 29, 2001 Essentials of Test: Agrawal & Bushnell

127 Essentials of Test: Agrawal & Bushnell
Memory Cells Per Chip April 29, 2001 Essentials of Test: Agrawal & Bushnell

128 Test Time in Seconds (Memory Size n Bits)
Size Number of Test Algorithm Operations n 1 Mb 4 Mb 16 Mb 64 Mb 256 Mb 1 Gb 2 Gb n 0.06 0.25 1.01 4.03 16.11 64.43 128.9 n X log2n 1.26 5.54 24.16 104.7 451.0 1932.8 3994.4 n3/2 64.5 515.4 1.2 hr 9.2 hr 73.3 hr 586.4 hr hr n2 18.3 hr 293.2 hr hr hr hr hr hr April 29, 2001 Essentials of Test: Agrawal & Bushnell

129 Essentials of Test: Agrawal & Bushnell
Fault Types Fault types: Permanent -- System is broken and stays broken the same way indefinitely Transient -- Fault temporarily affects the system behavior, and then the system reverts to the good machine -- time dependency, caused by environmental condition Intermittent -- Sometimes causes a failure, sometimes does not April 29, 2001 Essentials of Test: Agrawal & Bushnell

130 Essentials of Test: Agrawal & Bushnell
March Test Notation r -- Read a memory location w -- Write a memory location r0 -- Read a 0 from a memory location r1 -- Read a 1 from a memory location w0 -- Write a 0 to a memory location w1 -- Write a 1 to a memory location -- Write a 1 to a cell containing 0 -- Write a 0 to a cell containing 1 April 29, 2001 Essentials of Test: Agrawal & Bushnell

131 March Test Notation (Continued)
-- Complement the cell contents -- Increasing memory addressing -- Decreasing memory addressing -- Either increasing or decreasing April 29, 2001 Essentials of Test: Agrawal & Bushnell

132 Essentials of Test: Agrawal & Bushnell
MATS+ March Test M0: { March element (w0) } for cell := 0 to n - 1 (or any other order) do write 0 to A [cell]; M1: { March element (r0, w1) } for cell := 0 to n - 1 do read A [cell]; { Expected value = 0} write 1 to A [cell]; M2: {March element (r1, w0) } for cell := n – 1 down to 0 do read A [cell]; { Expected value = 1 } April 29, 2001 Essentials of Test: Agrawal & Bushnell

133 Reduced Functional Faults
Stuck-at fault Transition fault Coupling fault Neighborhood Pattern Sensitive fault SAF TF CF NPSF April 29, 2001 Essentials of Test: Agrawal & Bushnell

134 Essentials of Test: Agrawal & Bushnell
Transition Faults Cell fails to make or transition Condition: Each cell must undergo a transition and a transition, and be read after such, before undergoing any further transitions. < /0>, < /1> < /0> transition fault April 29, 2001 Essentials of Test: Agrawal & Bushnell

135 Essentials of Test: Agrawal & Bushnell
Coupling Faults Coupling Fault (CF): Transition in bit j causes unwanted change in bit i 2-Coupling Fault: Involves 2 cells, special case of k-Coupling Fault Must restrict k cells to make practical Inversion and Idempotent CFs -- special cases of 2-Coupling Faults Bridging and State Coupling Faults involve any # of cells, caused by logic level Dynamic Coupling Fault (CFdyn) -- Read or write on j forces i to 0 or 1 April 29, 2001 Essentials of Test: Agrawal & Bushnell

136 Idempotent Coupling Faults (CFid)
or transition in j sets cell i to 0 or 1 Condition: For all coupled faults, each should be read after a series of possible CFids may have happened, such that the sensitized CFids do not mask each other. Asymmetric: coupled cell only does or Symmetric: coupled cell does both due to fault < ; 0>, < ; 1>, < ; 0>, < ; 1> April 29, 2001 Essentials of Test: Agrawal & Bushnell

137 Essentials of Test: Agrawal & Bushnell
Bridging Faults Short circuit between 2+ cells or lines 0 or 1 state of coupling cell, rather than coupling cell transition, causes coupled cell change Bidirectional fault -- i affects j, j affects i AND Bridging Faults (ABF): < 0,0 / 0,0 >, <0,1 / 0,0 >, <1,0 / 0,0>, <1,1 / 1,1> OR Bridging Faults (OBF): < 0,0 / 0,0 >, <0,1 / 1,1 >, <1,0 / 1,1>, <1,1 / 1,1> April 29, 2001 Essentials of Test: Agrawal & Bushnell

138 Address Decoder Faults
Address decoding error assumptions: Decoder does not become sequential Same behavior during both read & write Multiple ADFs must be tested for Decoders have CMOS stuck-open faults April 29, 2001 Essentials of Test: Agrawal & Bushnell

139 Fault Modeling Example 1
SA0 SAF AF+SAF SCF<0;0> SA0 SCF<1;1> SA0 TF< /0> TF< /1> April 29, 2001 Essentials of Test: Agrawal & Bushnell

140 Fault Modeling Example 2
SA1+SCF SA1 gg ABF ABF SCF SA0 ABF April 29, 2001 Essentials of Test: Agrawal & Bushnell

141 Essentials of Test: Agrawal & Bushnell
Fault Hierarchy April 29, 2001 Essentials of Test: Agrawal & Bushnell

142 Essentials of Test: Agrawal & Bushnell
Fault Frequency Obtained with Scanning Electron Microscope CFin and TF faults rarely occurred Cluster 1 2 3 4 5 7 -- 14 # Devices 714 169 18 9 8 5 26 -- 2 Fault class Stuck-at and Total failure Stuck-open Idempotent coupling State coupling ? Data retention April 29, 2001 Essentials of Test: Agrawal & Bushnell

143 Functional RAM Testing with March Tests
March Tests can detect AFs -- NPSF Tests Cannot Conditions for AF detection: Need ( r x, w x) In the following March tests, addressing orders can be interchanged April 29, 2001 Essentials of Test: Agrawal & Bushnell

144 Irredundant March Test Summary
Algorithm MATS MATS+ MATS++ MARCH X MARCH C— MARCH A MARCH Y MARCH B SAF All AF Some All TF All CF in All CF id All CF dyn All SCF All Linked Faults Some April 29, 2001 Essentials of Test: Agrawal & Bushnell

145 MATS+ Example Cell (2, 1) SA1 Fault
{ M0: (w0); M1: (r0, w1); M2: (r1, w0) } April 29, 2001 Essentials of Test: Agrawal & Bushnell

146 Memory Testing Summary
Multiple fault models are essential Combination of tests is essential: March – SRAM and DRAM NPSF -- DRAM DC Parametric -- Both AC Parametric -- Both Inductive Fault Analysis is now required April 29, 2001 Essentials of Test: Agrawal & Bushnell

147 Essentials of Test: Agrawal & Bushnell
Analog Test April 29, 2001 Essentials of Test: Agrawal & Bushnell

148 Mixed-Signal Testing Problem
April 29, 2001 Essentials of Test: Agrawal & Bushnell

149 Differences from Digital Testing
Size not a problem – at most 100 components Much harder analog device modeling No widely-accepted analog fault model Infinite signal range Tolerances depend on process and measurement error Tester (ATE) introduces measurement error Digital / analog substrate coupling noise Absolute component tolerances +/- 20%, relative +/- 0.1% Multiple analog fault model mandatory No unique signal flow direction April 29, 2001 Essentials of Test: Agrawal & Bushnell

150 Present-Day Analog Testing Methods
Specification-based (functional) tests Main method for analog – tractable and does not need an analog fault model Intractable for digital -- # tests is huge Structural ATPG – used for digital, just beginning to be used for analog (exists) Separate test for functionality and timing not possible in analog circuit Possible in digital circuit April 29, 2001 Essentials of Test: Agrawal & Bushnell

151 Essentials of Test: Agrawal & Bushnell
Definitions ADC – A/D converter ATE – Automatic Test Equipment DAC – D/A converter DFT – Discrete Fourier Transform DUT – Device-Under-Test FFT – Fast Fourier Transform Glitch Area -- area in DAC output of glitching pulses Jitter – Low-level electrical noise – corrupts LSB’s, especially prevalent on converter clocking circuits ks/s – Kilo-samples/sec April 29, 2001 Essentials of Test: Agrawal & Bushnell

152 Essentials of Test: Agrawal & Bushnell
More Definitions LSB -- Least Significant Bit (of converter) Measurement – Result of measuring O/P analog parameter and quantifying it Measurement Error – Introduced by measurement process Non-Deterministic Device – All analog circuit measurements are not repeatable due to DUT or tester measurement noise Phase-Locked-Loop – Clock circuit with feedback to keep desired signal phase Settling Time -- Time for DAC reconstruction filter to settle Test – Combination of analog stimulus, measurement of voltage or current, with a measurement error tolerance April 29, 2001 Essentials of Test: Agrawal & Bushnell

153 DSP Tester Concept © 1987 IEEE
April 29, 2001 Essentials of Test: Agrawal & Bushnell

154 Waveform Synthesis © 1987 IEEE
Needs sin x / x (sinc) correction – Finite sample width April 29, 2001 Essentials of Test: Agrawal & Bushnell

155 Waveform Sampling © 1987 IEEE
Sampling rate > 100 ks/s April 29, 2001 Essentials of Test: Agrawal & Bushnell

156 Essentials of Test: Agrawal & Bushnell
ATE Clock Generator WS = waveform source WM = waveform measurement April 29, 2001 Essentials of Test: Agrawal & Bushnell

157 A/D and D/A Test Parameters
A/D -- Uncertain map from input domain voltages into digital value (not so in D/A) Two converters are NOT inverses Transmission parameters affect multi-tone tests Gain, signal-to-distortion ratio, intermodulation distortion, noise power ratio, differential phase shift, envelop delay distortion Intrinsic parameters – Converter specifications Full scale range (FSR), gain, # bits, static linearity (differential and integral), maximum clock rate, code format, settling time (D/A), glitch area (D/A) April 29, 2001 Essentials of Test: Agrawal & Bushnell

158 Ideal Transfer Functions
A/D Converter D/A Converter April 29, 2001 Essentials of Test: Agrawal & Bushnell

159 Essentials of Test: Agrawal & Bushnell
Offset Error April 29, 2001 Essentials of Test: Agrawal & Bushnell

160 Essentials of Test: Agrawal & Bushnell
Gain Error April 29, 2001 Essentials of Test: Agrawal & Bushnell

161 D/A Transfer Function Non-Linearity Error
April 29, 2001 Essentials of Test: Agrawal & Bushnell

162 Essentials of Test: Agrawal & Bushnell
Flash A/D Converter April 29, 2001 Essentials of Test: Agrawal & Bushnell

163 Differential Linearity Error
Differential linearity function – How each code step differs from ideal or average step (by code number), as fraction of LSB Subtract average count for each code tally, express that in units of LSBs Repeat test waveform 100 to 150 times, use slow triangle wave to increase resolution April 29, 2001 Essentials of Test: Agrawal & Bushnell

164 Linear Histogram and DLE of 8-bit ADC © 1987 IEEE
April 29, 2001 Essentials of Test: Agrawal & Bushnell

165 D/A Differential Test Fixture © 1987 IEEE
Measure Vy – Vx difference, not absolute Vx or Vy April 29, 2001 Essentials of Test: Agrawal & Bushnell

166 Essentials of Test: Agrawal & Bushnell
Summary DSP-based tester has: Waveform Generator Waveform Digitizer High frequency clock with dividers for synchronization A/D and D/A Test Parameters Transmission Intrinsic A/D and D/A Faults: offset, gain, non-linearity errors Measured by DLE, ILE, DNL, and INL A/D Test Histograms – static linear and sinusoidal D/A Test –- Differential Test Fixture April 29, 2001 Essentials of Test: Agrawal & Bushnell

167 Essentials of Test: Agrawal & Bushnell
DSP-Based Testing Quantization Error – Introduced into measured signal by discrete sampling Quantum Voltage – Corresponds to flip of LSB of converter Single-Tone Test -- Test of DUT using only one sinusoidal tone Tone – Pure sinusoid of f, A, and phase f Transmission (Performance) Parameter -- indicates how channel with embedded analog circuit affects multi-tone test signal UTP – Unit test period: joint sampling period for analog stimulus and response April 29, 2001 Essentials of Test: Agrawal & Bushnell

168 Coherent Measurement Method
Unit Test Period is integration interval P Has integral # of stimulus periods M Has integral # of DUT output periods N Stimulus & sampling are phase locked To obtain maximum information from sampling, M and N are relatively prime Ft – tone frequency Fs – sampling rate April 29, 2001 Essentials of Test: Agrawal & Bushnell

169 Essentials of Test: Agrawal & Bushnell
CODEC Testing Example Serial ADC in digital telephone exchange Sampling rate 8000 s/s Audio frequency range 300 – 3400 Hz Ft = 1000 Hz Fs = 8000 s/s P = 50 msec M = 50 cycles N = 400 samples Problem: M and N not relatively prime All samples fall on waveform at certain phases – sample only 8/255 CODEC steps April 29, 2001 Essentials of Test: Agrawal & Bushnell

170 CODEC Testing Solution
Set Fs = 400 ks/s – impossibly fast Better – Adjust Ft slightly, signal sampled at different points Necessary relationships: Ft = M x D Fs = N x D D = 1 / UTP Ft M Fs N = April 29, 2001 Essentials of Test: Agrawal & Bushnell

171 Essentials of Test: Agrawal & Bushnell
Good CODEC Parameters Ft = 1020 Hz Fs = 8000 s/s P = UTP = 50 msec D = 20 Hz M = 51 cycles N = 400 samples M and N now relatively prime All samples fall on waveform at different phases – samples all CODEC steps April 29, 2001 Essentials of Test: Agrawal & Bushnell

172 Essentials of Test: Agrawal & Bushnell
Unit Test Period © 1987 IEEE April 29, 2001 Essentials of Test: Agrawal & Bushnell

173 Spectral Test of A/D Converter © 1987 IEEE
April 29, 2001 Essentials of Test: Agrawal & Bushnell

174 Bad A/D Converter Test © 1987 IEEE
April 29, 2001 Essentials of Test: Agrawal & Bushnell

175 Good A/D Converter Test © 1987 IEEE
April 29, 2001 Essentials of Test: Agrawal & Bushnell

176 Spectral DSP-Based Testing Components © 1987 IEEE
April 29, 2001 Essentials of Test: Agrawal & Bushnell

177 Correlation Model © 1987 IEEE
Cross-correlation – compare 2 different signals Autocorrelation – compare 1 signal with itself April 29, 2001 Essentials of Test: Agrawal & Bushnell

178 Fourier Voltmeter 1st Principle © 1987 IEEE
For signals A and B, if P is infinite, R = 0. If P is finite and contains integer # cycles of both A and B, then cross-correlation R = 0, regardless of phase or amplitude April 29, 2001 Essentials of Test: Agrawal & Bushnell

179 Fourier Voltmeter 2nd Principle © 1987 IEEE
If signals A and B of same f are 90o out of phase, and P contains an integer J # of signal cycles, then cross-correlation R = 0, regardless of amplitude or starting point April 29, 2001 Essentials of Test: Agrawal & Bushnell

180 Conceptual Discrete Fourier Voltmeter © 1987 IEEE
April 29, 2001 Essentials of Test: Agrawal & Bushnell

181 A/D Converter Spectrum © 1987 IEEE
Audio source at 1076 Hz sampled at 44.1 kHz April 29, 2001 Essentials of Test: Agrawal & Bushnell

182 Coherent Multi-Tone Testing © 1987 IEEE
April 29, 2001 Essentials of Test: Agrawal & Bushnell

183 Single-Tone Test Example © 1987 IEEE
April 29, 2001 Essentials of Test: Agrawal & Bushnell

184 Multi-Tone Test Example © 1987 IEEE
April 29, 2001 Essentials of Test: Agrawal & Bushnell

185 Total Harmonic Distortion (THD)
Measures energy appearing in harmonics (H2, H3, …) of fundamental tone H1 as % of energy in the fundamental frequency in response spectrum THD = H2 10 H3 10 H10 10 … + 10 10 H1 20 April 29, 2001 Essentials of Test: Agrawal & Bushnell

186 Essentials of Test: Agrawal & Bushnell
DSP Testing Summary Analog testing greatly increasing in importance System-on-a-chip Wireless Personal computer multi-media Automotive electronics Medicine Internet telephony CD players and audio electronics Analog testing NOT deterministic like digital Statistical testing process, electrical noise April 29, 2001 Essentials of Test: Agrawal & Bushnell

187 Essentials of Test: Agrawal & Bushnell
Delay Test April 29, 2001 Essentials of Test: Agrawal & Bushnell

188 Essentials of Test: Agrawal & Bushnell
Delay Test Definition A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing. For a combinational or synchronous sequential circuit, delay test verifies the limits of delay in combinational logic. Delay test problem for asynchronous circuits is complex and not well understood. April 29, 2001 Essentials of Test: Agrawal & Bushnell

189 Digital Circuit Timing
Input Signal changes Output Observation instant Transient region Inputs Comb. logic Synchronized With clock Outputs time Clock period April 29, 2001 Essentials of Test: Agrawal & Bushnell

190 Essentials of Test: Agrawal & Bushnell
Circuit Delays Switching or inertial delay is the interval between input change and output change of a gate: Depends on input capacitance, device (transistor) characteristics and output capacitance of gate. Also depends on input rise or fall times and states of other inputs (second-order effects). Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output. Propagation or interconnect delay is the time a transition takes to travel between gates: Depends on transmission line effects (distributed R, L, C parameters, length and loading) of routing paths. Approximation: modeled as lumped delays for gate inputs. See Section for timing models. April 29, 2001 Essentials of Test: Agrawal & Bushnell

191 Event Propagation Delays
Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew Path P1 1 3 1 2 4 6 P2 1 2 3 P3 2 5 April 29, 2001 Essentials of Test: Agrawal & Bushnell

192 Essentials of Test: Agrawal & Bushnell
Circuit Outputs Each path can potentially produce one signal transition at the output. The location of an output transition in time is determined by the delay of the path. Clock period Final value Initial value Fast transitions Slow transitions time Initial value Final value April 29, 2001 Essentials of Test: Agrawal & Bushnell

193 Essentials of Test: Agrawal & Bushnell
Robust Test A robust test guarantees the detection of a delay fault of the target path, irrespective of delay faults on other paths. A robust test is a combinational vector-pair, V1, V2, that satisfies following conditions: Produce real events (different steady-state values for V1 and V2) on all on-path signals. All on-path signals must have controlling events arriving via the target path. A robust test is also a non-robust test. Concept of robust test is general – robust tests for other fault models can be defined. April 29, 2001 Essentials of Test: Agrawal & Bushnell

194 Essentials of Test: Agrawal & Bushnell
A Five-Valued Algebra Signal States: S0, U0 (F0), S1, U1 (R1), XX. On-path signals: F0 and R1. Off-path signals: F0=U0 and R1=U1. Input 1 Input 1 AND S0 U0 S1 U1 XX S0 S0 S0 S0 S0 S0 U0 S0 U0 U0 U0 U0 S1 S0 U0 S1 U1 XX U1 S0 U0 U1 U1 XX XX S0 U0 XX XX XX S0 U0 S1 U1 XX S0 S0 U0 S1 U1 XX U0 U0 U0 S1 U1 XX S1 S1 S1 S1 S1 S1 U1 U1 U1 S1 U1 U1 XX XX XX S1 U1 XX OR Input 2 Input 2 Input S0 U0 S1 U1 XX S1 U1 S0 U0 XX Ref.: Lin-Reddy IEEETCAD-87 NOT April 29, 2001 Essentials of Test: Agrawal & Bushnell

195 Non-Robust Test Generation
Fault P2 – rising transition through path P2 has no robust test. C. Set input of AND gate to propagate R1 to output D. R1 propagates through OR gate since off-path input is U0 XX U1 R1 R1 Path P2 R1 A. Place R1 at path origin R1 R1 U1 U0 Non-robust test requires Static sensitization: S0=U0, S1=U1 XX U0 B. Propagate R1 through OR gate; interpreted as U1 on off-path signal; propagates as U0 through NOT gate Non-robust test: U1, R1, U0 April 29, 2001 Essentials of Test: Agrawal & Bushnell

196 Path-Delay Faults (PDF)
Two PDFs (rising and falling transitions) for each physical path. Total number of paths is an exponential function of gates. Critical paths, identified by static timing analysis (e.g., Primetime from Synopsys), must be tested. PDF tests are delay-independent. Robust tests are preferred, but some paths have only non-robust tests. Three types of PDFs (Gharaybeh, et al., JETTA (11), 1997): Singly-testable PDF – has a non-robust or robust test. Multiply-testable PDF – a set of singly untestable faults that has a non-robust or robust test. Also known as functionally testable PDF. Untestable PDF – a PDF that is neither singly nor multiply testable. A singly-testable PDF has at least one single-input change (SIC) non-robust test. April 29, 2001 Essentials of Test: Agrawal & Bushnell

197 Other Delay Fault Models
Segment-delay fault -- A segment of an IO path is assumed to have large delay such that all paths containing the segment become faulty. Transition fault -- A segment-delay fault with segment of unit length (single gate): Two faults per gate; slow-to-rise and slow-to-fall. Tests are similar to stuck-at fault tests. For example, a line is initialized to 0 and then tested for s-a-0 fault to detect slow-to-rise transition fault. Models spot (or gross) delay defects. Line-delay fault – A transition fault tested through the longest delay path. Two faults per line or gate. Tests are dependent on modeled delays of gates. Gate-delay fault – A gate is assumed to have a delay increase of certain amount (called fault size) while all other gates retain some nominal delays. Gate-delay faults only of certain sizes may be detectable. April 29, 2001 Essentials of Test: Agrawal & Bushnell

198 Essentials of Test: Agrawal & Bushnell
Slow-Clock Test Input latches Combinational circuit Output latches Input test clock Output test clock Test clock period Rated clock period Input test clock Output test clock V1 applied V2 applied Output latched April 29, 2001 Essentials of Test: Agrawal & Bushnell

199 Essentials of Test: Agrawal & Bushnell
Enhanced-Scan Test CK period PI Combinational circuit PO CK CK TC SCAN- OUT HOLD HL SFF Scanout result V1 settles HL SFF SCANIN HOLD Normal mode Scan mode Normal mode CK TC TC CK: system clock TC: test control HOLD: hold signal SFF: scan flip-flop HL: hold latch Scanin V1 states Scanin V2 states Result latched V1 PI applied V2 PI applied April 29, 2001 Essentials of Test: Agrawal & Bushnell

200 Essentials of Test: Agrawal & Bushnell
Normal-Scan Test V2 states generated, (A) by one-bit scan shift of V1, or (B) by V1 applied in functional mode. Result latched V1 PIs applied V2 PIs applied PI Combinational circuit PO Scanin V1 states Gen. V2 states Path tested Result scanout CK TC t SCAN- OUT Slow clock Rated CK period SFF TC (A) Scan mode Normal mode SFF Scan mode SCANIN Slow CK period CK TC TC (B) CK: system clock TC: test control SFF: scan flip-flop Scan mode Normal mode Scan mode April 29, 2001 Essentials of Test: Agrawal & Bushnell

201 Variable-Clock Sequential Test
Off-path flip-flop PI PI PI PI PI PI 1 T 1 T n-2 1 T n-1 1 T n 1 T n+1 T n+m 2 2 2 D PO PO PO PO PO PO Path activation (rated Clock) Fault effect propagation sequence (slow clock) Initialization sequence (slow clock) Note: Slow-clock makes the circuit fault-free in the presence of delay faults. April 29, 2001 Essentials of Test: Agrawal & Bushnell

202 Variable-Clock Example
ISCAS’89 benchmark s35932 (non-scan). 2,124 vectors obtained by simulator-selection from random vectors (Parodi, et al., ITC-98). PDF coverage, 26,228/394,282 ~ 6.7% Longest tested PDF, 27 gates; longest path has 29 gates. Test time ~ 4,511,376 clocks. April 29, 2001 Essentials of Test: Agrawal & Bushnell

203 Essentials of Test: Agrawal & Bushnell
At-Speed Test At-speed test means application of test vectors at the rated-clock speed. Two methods of at-speed test. External test: Vectors may test one or more functional critical (longest delay) paths and a large percentage (~100%) of transition faults. High-speed testers are expensive. Built-in self-test (BIST): Hardware-generated random vectors applied to combinational or sequential logic. Only clock is externally supplied. Non-functional paths that are longer than the functional critical path can be activated and cause a good circuit to fail. Some circuits have initialization problem. April 29, 2001 Essentials of Test: Agrawal & Bushnell

204 Timing Design & Delay Test
Timing simulation: Critical paths are identified by static (vector-less) timing analysis tools like Primetime (Synopsys). Timing or circuit-level simulation using designer-generated functional vectors verifies the design. Layout optimization: Critical path data are used in placement and routing. Delay parameter extraction, timing simulation and layout are repeated for iterative improvement. Testing: Some form of at-speed test is necessary. PDFs for critical paths and all transition faults are tested. April 29, 2001 Essentials of Test: Agrawal & Bushnell

205 Essentials of Test: Agrawal & Bushnell
Summary Path-delay fault (PDF) models distributed delay defects. It verifies the timing performance of a manufactured circuit. Transition fault models spot delay defects and is testable by modified stuck-at fault tests. Variable-clock method can test delay faults but the test time can be long. Critical paths of non-scan sequential circuits can be effectively tested by rated-clock tests. Delay test methods (including BIST) for non-scan sequential circuits using slow ATE require investigation: Suppression of non-functional path activation in BIST. Difficulty of rated-clock PDF test generation. Long sequences of variable-clock tests. April 29, 2001 Essentials of Test: Agrawal & Bushnell

206 Essentials of Test: Agrawal & Bushnell
IDDQ Test April 29, 2001 Essentials of Test: Agrawal & Bushnell

207 Basic Principle of IDDQ Testing
Measure IDDQ current through Vss bus April 29, 2001 Essentials of Test: Agrawal & Bushnell

208 Stuck-at Faults Detected by IDDQ Tests
Bridging faults with stuck-at fault behavior Levi – Bridging of a logic node to VDD or VSS – few of these Transistor gate oxide short of 1 KW to KW Floating MOSFET gate defects – do not fully turn off transistor April 29, 2001 Essentials of Test: Agrawal & Bushnell

209 Capacitive Coupling of Floating Gates
Cpb – capacitance from poly to bulk Cmp – overlapped metal wire to poly Floating gate voltage depends on capacitances and node voltages If nFET and pFET get enough gate voltage to turn them on, then IDDQ test detects this defect K is the transistor gain April 29, 2001 Essentials of Test: Agrawal & Bushnell

210 Essentials of Test: Agrawal & Bushnell
Bridging Faults S1 – S5 Caused by absolute short (< 50 W) or higher R Segura et al. evaluated testing of bridges with 3 CMOS inverter chain IDDQRb tests fault when Rb > 50 KW or Rb KW Largest deviation when Vin = 5 V bridged nodes at opposite logic values April 29, 2001 Essentials of Test: Agrawal & Bushnell

211 Essentials of Test: Agrawal & Bushnell
Delay Faults Most random CMOS defects cause a timing delay fault, not catastrophic failure Many delay faults detected by IDDQ test – late switching of logic gates keeps IDDQ elevated Delay faults not detected by IDDQ test Resistive via fault in interconnect Increased transistor threshold voltage fault April 29, 2001 Essentials of Test: Agrawal & Bushnell

212 Essentials of Test: Agrawal & Bushnell
Leakage Faults Gate oxide shorts cause leaks between gate & source or gate & drain Mao and Gulati leakage fault model: Leakage path flags: fGS, fGD, fSD, fBS, fBD, fBG G = gate, S = source, D = drain, B = bulk Assume that short does not change logic values April 29, 2001 Essentials of Test: Agrawal & Bushnell

213 Essentials of Test: Agrawal & Bushnell
Weak Faults nFET passes logic 1 as 5 V – Vtn pFET passes logic 0 as 0 V + |Vtp| Weak fault – one device in C-switch does not turn on Causes logic value degradation in C-switch April 29, 2001 Essentials of Test: Agrawal & Bushnell

214 Essentials of Test: Agrawal & Bushnell
Gate Oxide Short April 29, 2001 Essentials of Test: Agrawal & Bushnell

215 Fault Coverage Metrics
Conductance fault model (Malaiya & Su) Monitor IDDQ to detect all leakage faults Proved that stuck fault test set can be used to generate minimum leakage fault test set Short fault coverage Handles intra-gate bridges, but may not handle inter-gate bridges Pseudo-stuck-at fault coverage Voltage stuck-at fault coverage that represents internal transistor short fault coverage and hard stuck-at fault coverage April 29, 2001 Essentials of Test: Agrawal & Bushnell

216 Essentials of Test: Agrawal & Bushnell
Quietest Results Ckt. 1 2 # of Tran- Sistors 7584 42373 Leakage Faults 39295 220571 % Selected Vectors 0.5 % 0.99 % Fault Coverage 94.84 % 90.50 % # of Weak Faults 1923 1497 % Selected Vectors 0.35 % 0.21 % Fault Coverage 85.3 % 87.64 % Ckt. 1 2 April 29, 2001 Essentials of Test: Agrawal & Bushnell

217 Essentials of Test: Agrawal & Bushnell
Sematech Results Test process: Wafer Test Package Test Burn-In & Retest Characterize & Failure Analysis Data for devices failing some, but not all, tests. pass fail 14 6 52 1 36 1463 34 13 1251 7 8 Scan-based Stuck-at IDDQ (5 mA limit) Functional Scan-based delay April 29, 2001 Essentials of Test: Agrawal & Bushnell

218 Essentials of Test: Agrawal & Bushnell
Summary IDDQ tests improve reliability, find defects causing: Delay, bridging, weak faults Chips damaged by electro-static discharge No natural breakpoint for current threshold Get continuous distribution – bimodal would be better Conclusion: now need stuck-fault, IDDQ, and delay fault testing combined Still uncertain whether IDDQ tests will remain useful as chip feature sizes shrink further April 29, 2001 Essentials of Test: Agrawal & Bushnell

219 Part III DESIGN FOR TESTABILITY Scan Design
April 29, 2001 Essentials of Test: Agrawal & Bushnell

220 Essentials of Test: Agrawal & Bushnell
Definition Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits: Ad-hoc methods Structured methods: Scan Partial Scan Built-in self-test (BIST) Boundary scan DFT method for mixed-signal circuits: Analog test bus April 29, 2001 Essentials of Test: Agrawal & Bushnell

221 Essentials of Test: Agrawal & Bushnell
Ad-Hoc DFT Methods Good design practices learnt through experience are used as guidelines: Avoid asynchronous (unclocked) feedback. Make flip-flops initializable. Avoid redundant gates. Avoid large fanin gates. Provide test control for difficult-to-control signals. Avoid gated clocks. . . . Consider ATE requirements (tristates, etc.) Design reviews conducted by experts or design auditing tools. Disadvantages of ad-hoc DFT methods: Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary. April 29, 2001 Essentials of Test: Agrawal & Bushnell

222 Essentials of Test: Agrawal & Bushnell
Scan Design Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design: Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. April 29, 2001 Essentials of Test: Agrawal & Bushnell

223 Essentials of Test: Agrawal & Bushnell
Scan Design Rules Use only clocked D-type of flip-flops for all state variables. At least one PI pin must be available for test; more pins, if available, can be used. All clocks must be controlled from PIs. Clocks must not feed data inputs of flip-flops. April 29, 2001 Essentials of Test: Agrawal & Bushnell

224 Correcting a Rule Violation
All clocks must be controlled from PIs. Comb. logic D1 Q FF Comb. logic D2 CK Comb. logic Q D1 Comb. logic D2 FF CK April 29, 2001 Essentials of Test: Agrawal & Bushnell

225 Essentials of Test: Agrawal & Bushnell
Scan Flip-Flop (SFF) D Master latch Slave latch TC Q Logic overhead MUX Q SD CK D flip-flop Master open CK Slave open t Normal mode, D selected Scan mode, SD selected TC t April 29, 2001 Essentials of Test: Agrawal & Bushnell

226 Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)
Master latch Slave latch D Q MCK Q SCK D flip-flop SD MCK Normal mode Logic overhead TCK MCK TCK Scan mode TCK SCK t April 29, 2001 Essentials of Test: Agrawal & Bushnell

227 Essentials of Test: Agrawal & Bushnell
Adding Scan Structure PI PO SFF SCANOUT Combinational logic SFF SFF TC or TCK Not shown: CK or MCK/SCK feed all SFFs. SCANIN April 29, 2001 Essentials of Test: Agrawal & Bushnell

228 Essentials of Test: Agrawal & Bushnell
Comb. Test Vectors I1 I2 O1 O2 PI PO Combinational logic SCANIN TC SCANOUT S1 S2 N1 N2 Next state Present state April 29, 2001 Essentials of Test: Agrawal & Bushnell

229 Essentials of Test: Agrawal & Bushnell
Comb. Test Vectors I1 I2 Don’t care or random bits PI SCANIN S1 S2 TC O1 O2 PO SCANOUT N1 N2 Sequence length = (ncomb + 1) nsff + ncomb clock periods ncomb = number of combinational vectors nsff = number of scan flip-flops April 29, 2001 Essentials of Test: Agrawal & Bushnell

230 Essentials of Test: Agrawal & Bushnell
Testing Scan Register Scan register must be tested prior to application of scan test sequences. A shift sequence of length nsff+4 in scan mode (TC=0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output. Total scan test length: (ncomb + 2) nsff + ncomb + 4 clock periods. Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106 clocks. Multiple scan registers reduce test length. April 29, 2001 Essentials of Test: Agrawal & Bushnell

231 Essentials of Test: Agrawal & Bushnell
Scan Overheads IO pins: One pin necessary. Area overhead: Gate overhead = [4 nsff/(ng+10nff)] x 100%, where ng = comb. gates; nff = flip-flops; Example – ng = 100k gates, nff = 2k flip-flops, overhead = 6.7%. More accurate estimate must consider scan wiring and layout area. Performance overhead: Multiplexer delay added in combinational path; approx. two gate-delays. Flip-flop output loading due to one additional fanout; approx. 5-6%. April 29, 2001 Essentials of Test: Agrawal & Bushnell

232 Essentials of Test: Agrawal & Bushnell
ATPG Example: S5378 Original 2,781 179 0.0% 4,603 35/49 70.0% 70.9% 5,533 s 414 Full-scan 2,781 179 15.66% 4,603 214/228 99.1% 100.0% 5 s 585 105,662 Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency CPU time on SUN Ultra II, 200MHz processor Number of ATPG vectors Scan sequence length April 29, 2001 Essentials of Test: Agrawal & Bushnell

233 Automated Scan Design Behavior, RTL, and logic Design and verification
Rule violations Scan design rule audits Gate-level netlist Combinational ATPG Scan hardware insertion Combinational vectors Scan netlist Scan sequence and test program generation Chip layout: Scan- chain optimization, timing verification Scan chain order Design and test data for manufacturing Test program Mask data April 29, 2001 Essentials of Test: Agrawal & Bushnell

234 Essentials of Test: Agrawal & Bushnell
Summary Scan is the most popular DFT technique: Rule-based design Automated DFT hardware insertion Combinational ATPG Advantages: Design automation High fault coverage; helpful in diagnosis Hierarchical – scan-testable modules are easily combined into large scan-testable systems Moderate area (~10%) and speed (~5%) overheads Disadvantages: Large test data volume and long test time Basically a slow speed (DC) test April 29, 2001 Essentials of Test: Agrawal & Bushnell

235 Built-In Self-Testing (BIST)
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236 Essentials of Test: Agrawal & Bushnell
Economics – BIST Costs Chip area overhead for: Test controller Hardware pattern generator Hardware response compacter Testing of BIST hardware Pin overhead -- At least 1 pin needed to activate BIST operation Performance overhead – extra path delays due to BIST Yield loss – due to increased chip area or more chips In system because of BIST Reliability reduction – due to increased area Increased BIST hardware complexity – happens when BIST hardware is made testable April 29, 2001 Essentials of Test: Agrawal & Bushnell

237 Essentials of Test: Agrawal & Bushnell
BIST Benefits Faults tested: Single combinational / sequential stuck-at faults Delay faults Single stuck-at faults in BIST hardware BIST benefits Reduced testing and maintenance cost Lower test generation cost Reduced storage / maintenance of test patterns Simpler and less expensive ATE Can test many units in parallel Shorter test application times Can test at functional system speed April 29, 2001 Essentials of Test: Agrawal & Bushnell

238 Essentials of Test: Agrawal & Bushnell
BIST Process Test controller – Hardware that activates self-test simultaneously on all PCBs Each board controller activates parallel chip BIST Diagnosis effective only if very high fault coverage April 29, 2001 Essentials of Test: Agrawal & Bushnell

239 Essentials of Test: Agrawal & Bushnell
BIST Architecture Note: BIST cannot test wires and transistors: From PI pins to Input MUX From POs to output pins April 29, 2001 Essentials of Test: Agrawal & Bushnell

240 Example External XOR LFSR
Characteristic polynomial f (x) = 1 + x + x3 (read taps from right to left) April 29, 2001 Essentials of Test: Agrawal & Bushnell

241 Essentials of Test: Agrawal & Bushnell
External XOR LFSR Pattern sequence for example LFSR (earlier): Always have 1 and xn terms in polynomial Never repeat an LFSR pattern more than 1 time –Repeats same error vector, cancels fault effect X0 X1 X2 1 X0 (t + 1) X1 (t + 1) X2 (t + 1) 1 X0 (t) X1 (t) X2 (t) = April 29, 2001 Essentials of Test: Agrawal & Bushnell

242 Essentials of Test: Agrawal & Bushnell
Response Compaction Severe amounts of data in CUT response to LFSR patterns – example: Generate 5 million random patterns CUT has 200 outputs Leads to: 5 million x 200 = 1 billion bits response Uneconomical to store and check all of these responses on chip Responses must be compacted April 29, 2001 Essentials of Test: Agrawal & Bushnell

243 Essentials of Test: Agrawal & Bushnell
Definitions Aliasing – Due to information loss, signatures of good and some bad machines match Compaction – Drastically reduce # bits in original circuit response – lose information Compression – Reduce # bits in original circuit response – no information loss – fully invertible (can get back original response) Signature analysis – Compact good machine response into good machine signature. Actual signature generated during testing, and compared with good machine signature Transition Count Response Compaction – Count # transitions from and as a signature April 29, 2001 Essentials of Test: Agrawal & Bushnell

244 LFSR for Response Compaction
Use cyclic redundancy check code (CRCC) generator (LFSR) for response compacter Treat data bits from circuit POs to be compacted as a decreasing order coefficient polynomial CRCC divides the PO polynomial by its characteristic polynomial Leaves remainder of division in LFSR Must initialize LFSR to seed value (usually 0) before testing After testing – compare signature in LFSR to known good machine signature Critical: Must compute good machine signature April 29, 2001 Essentials of Test: Agrawal & Bushnell

245 Example Modular LFSR Response Compacter
LFSR seed value is “00000” April 29, 2001 Essentials of Test: Agrawal & Bushnell

246 Essentials of Test: Agrawal & Bushnell
Polynomial Division Inputs Initial State 1 X0 1 X1 1 X2 1 X3 1 X4 1 Logic Simulation: Logic simulation: Remainder = 1 + x2 + x3 0 x x x x x x x x7 . . . . . . . . April 29, 2001 Essentials of Test: Agrawal & Bushnell

247 Symbolic Polynomial Division
x2 x7 + 1 + x5 x5 + x3 x3 + x x5 + x3 + x + 1 + x2 + 1 remainder Remainder matches that from logic simulation of the response compacter! April 29, 2001 Essentials of Test: Agrawal & Bushnell

248 Multiple-Input Signature Register (MISR)
Problem with ordinary LFSR response compacter: Too much hardware if one of these is put on each primary output (PO) Solution: MISR – compacts all outputs into one LFSR Works because LFSR is linear – obeys superposition principle Superimpose all responses in one LFSR – final remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial April 29, 2001 Essentials of Test: Agrawal & Bushnell

249 Essentials of Test: Agrawal & Bushnell
Modular MISR Example X0 (t + 1) X1 (t + 1) X2 (t + 1) 1 = X0 (t) X1 (t) X2 (t) d0 (t) d1 (t) d2 (t) + April 29, 2001 Essentials of Test: Agrawal & Bushnell

250 Essentials of Test: Agrawal & Bushnell
Aliasing Theorems Theorem 15.1: Assuming that each circuit PO dij has probability p of being in error, and that all outputs dij are independent, in a k-bit MISR, Pal = 1/(2k), regardless of initial condition of MISR. Not exactly true – true in practice. Theorem 15.2: Assuming that each PO dij has probability pj of being in error, where the pj probabilities are independent, and that all outputs dij are independent, in a k-bit MISR, Pal = 1/(2k), regardless of the initial condition. April 29, 2001 Essentials of Test: Agrawal & Bushnell

251 Built-in Logic Block Observer (BILBO)
Combined functionality of D flip-flop, pattern generator, response compacter, & scan chain Reset all FFs to 0 by scanning in zeros April 29, 2001 Essentials of Test: Agrawal & Bushnell

252 Essentials of Test: Agrawal & Bushnell
Example BILBO Usage SI – Scan In SO – Scan Out Characteristic polynomial: 1 + x + … + xn CUTs A and C: BILBO1 is MISR, BILBO2 is LFSR CUT B: BILBO1 is LFSR, BILBO2 is MISR April 29, 2001 Essentials of Test: Agrawal & Bushnell

253 Circuit Initialization
Full-scan BIST – shift in scan chain seed before starting BIST Partial-scan BIST – critical to initialize all FFs before BIST starts Otherwise we clock X’s into MISR and signature is not unique and not repeatable Discover initialization problems by: Modeling all BIST hardware Setting all FFs to X’s Running logic simulation of CUT with BIST hardware April 29, 2001 Essentials of Test: Agrawal & Bushnell

254 Circuit Initialization (continued)
If MISR finishes with BIST cycle with X’s in signature, Design-for-Testability initialization hardware must be added Add MS (master set) or MR (master reset) lines on flip-flops and excite them before BIST starts Otherwise: Break all cycles of FF’s Apply a partial BIST synchronizing sequence to initialize all FF’s Turn on the MISR to compact the response April 29, 2001 Essentials of Test: Agrawal & Bushnell

255 Essentials of Test: Agrawal & Bushnell
Test Point Insertion BIST does not detect all faults: Test patterns not rich enough to test all faults Modify circuit after synthesis to improve signal controllability Observability addition – Route internal signal to extra FF in MISR or XOR into existing FF in MISR April 29, 2001 Essentials of Test: Agrawal & Bushnell

256 Essentials of Test: Agrawal & Bushnell
SRAM BIST with MISR Use MISR to compress memory outputs Control aliasing by repeating test: With different MISR feedback polynomial With RAM test patterns in reverse order March test: { (w Address); (r Address); (w Address); (r Address); (r Address); (w Address); (r Address); (r Address) } Not proven to detect coupling or address decoder faults April 29, 2001 Essentials of Test: Agrawal & Bushnell

257 Essentials of Test: Agrawal & Bushnell
BIST System with MISR April 29, 2001 Essentials of Test: Agrawal & Bushnell

258 Essentials of Test: Agrawal & Bushnell
Summary LFSR pattern generator and MISR response compacter – preferred BIST methods BIST has overheads: test controller, extra circuit delay, Input MUX, pattern generator, response compacter, DFT to initialize circuit & test the test hardware BIST benefits: At-speed testing for delay & stuck-at faults Drastic ATE cost reduction Field test capability Faster diagnosis during system test Less effort to design testing process Shorter test application times April 29, 2001 Essentials of Test: Agrawal & Bushnell

259 IEEE 1149.1 Boundary Scan Standard
April 29, 2001 Essentials of Test: Agrawal & Bushnell

260 Motivation for Standard
Bed-of-nails printed circuit board tester gone We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance Nails would hit components Reduced spacing between PCB wires Nails would short the wires PCB Tester must be replaced with built-in test delivery system -- JTAG does that Need standard System Test Port and Bus Integrate components from different vendors Test bus identical for various components One chip has test hardware for other chips April 29, 2001 Essentials of Test: Agrawal & Bushnell

261 Essentials of Test: Agrawal & Bushnell
Purpose of Standard Lets test instructions and test data be serially fed into a component-under-test (CUT) Allows reading out of test results Allows RUNBIST command as an instruction Too many shifts to shift in external tests JTAG can operate at chip, PCB, & system levels Allows control of tri-state signals during testing Lets other chips collect responses from CUT Lets system interconnect be tested separately from components Lets components be tested separately from wires April 29, 2001 Essentials of Test: Agrawal & Bushnell

262 Essentials of Test: Agrawal & Bushnell
System Test Logic April 29, 2001 Essentials of Test: Agrawal & Bushnell

263 Instruction Register Loading with JTAG
April 29, 2001 Essentials of Test: Agrawal & Bushnell

264 System View of Interconnect
April 29, 2001 Essentials of Test: Agrawal & Bushnell

265 Boundary Scan Chain View
April 29, 2001 Essentials of Test: Agrawal & Bushnell

266 Elementary Boundary Scan Cell
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267 Essentials of Test: Agrawal & Bushnell
Serial Board / MCM Scan April 29, 2001 Essentials of Test: Agrawal & Bushnell

268 Parallel Board / MCM Scan
April 29, 2001 Essentials of Test: Agrawal & Bushnell

269 Tap Controller Signals
Test Access Port (TAP) includes these signals: Test Clock Input (TCK) -- Clock for test logic Can run at different rate from system clock Test Mode Select (TMS) -- Switches system from functional to test mode Test Data Input (TDI) -- Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions Test Data Output (TDO) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers) Test Reset (TRST) -- Optional asynchronous TAP controller reset April 29, 2001 Essentials of Test: Agrawal & Bushnell

270 SAMPLE / PRELOAD Instruction -- SAMPLE
Purpose: Get snapshot of normal chip output signals Put data on bound. scan chain before next instr. April 29, 2001 Essentials of Test: Agrawal & Bushnell

271 SAMPLE / PRELOAD Instruction -- PRELOAD
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272 Essentials of Test: Agrawal & Bushnell
EXTEST Instruction Purpose: Test off-chip circuits and board-level interconnections April 29, 2001 Essentials of Test: Agrawal & Bushnell

273 Essentials of Test: Agrawal & Bushnell
INTEST Instruction Purpose: Shifts external test patterns onto component External tester shifts component responses out April 29, 2001 Essentials of Test: Agrawal & Bushnell

274 Essentials of Test: Agrawal & Bushnell
RUNBIST Instruction Purpose: Allows you to issue BIST command to component through JTAG hardware Optional instruction Lets test logic control state of output pins Can be determined by pin boundary scan cell Can be forced into high impedance state BIST result (success or failure) can be left in boundary scan cell or internal cell Shift out through boundary scan chain May leave chip pins in an indeterminate state (reset required before normal operation resumes) April 29, 2001 Essentials of Test: Agrawal & Bushnell

275 Essentials of Test: Agrawal & Bushnell
CLAMP Instruction Purpose: Forces component output signals to be driven by boundary-scan register Bypasses the boundary scan chain by using the one-bit Bypass Register Optional instruction May have to add RESET hardware to control on-chip logic so that it does not get damaged (by shorting 0’s and 1’s onto an internal bus, etc.) April 29, 2001 Essentials of Test: Agrawal & Bushnell

276 Essentials of Test: Agrawal & Bushnell
IDCODE Instruction Purpose: Connects the component device identification register serially between TDI and TDO In the Shift-DR TAP controller state Allows board-level test controller or external tester to read out component ID Required whenever a JEDEC identification register is included in the design April 29, 2001 Essentials of Test: Agrawal & Bushnell

277 Device ID Register --JEDEC Code
Part Number (16 bits) Manufacturer Identity (11 bits) ‘1’ (1 bit) Version (4 bits) MSB LSB April 29, 2001 Essentials of Test: Agrawal & Bushnell

278 Essentials of Test: Agrawal & Bushnell
USERCODE Instruction Purpose: Intended for user-programmable components (FPGA’s, EEPROMs, etc.) Allows external tester to determine user programming of component Selects the device identification register as serially connected between TDI and TDO User-programmable ID code loaded into device identification register On rising TCK edge Switches component test hardware to its system function Required when Device ID register included on user-programmable component April 29, 2001 Essentials of Test: Agrawal & Bushnell

279 Essentials of Test: Agrawal & Bushnell
HIGHZ Instruction Purpose: Puts all component output pin signals into high-impedance state Control chip logic to avoid damage in this mode May have to reset component after HIGHZ runs Optional instruction April 29, 2001 Essentials of Test: Agrawal & Bushnell

280 Essentials of Test: Agrawal & Bushnell
BYPASS Instruction Purpose: Bypasses scan chain with 1-bit register April 29, 2001 Essentials of Test: Agrawal & Bushnell

281 Essentials of Test: Agrawal & Bushnell
Summary Boundary Scan Standard has become absolutely essential -- No longer possible to test printed circuit boards with bed-of-nails tester Not possible to test multi-chip modules at all without it Supports BIST, external testing with Automatic Test Equipment, and boundary scan chain reconfiguration as BIST pattern generator and response compacter Now getting widespread usage April 29, 2001 Essentials of Test: Agrawal & Bushnell

282 Essentials of Test: Agrawal & Bushnell
IEEE Analog Test Bus April 29, 2001 Essentials of Test: Agrawal & Bushnell

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Analog Test Bus PROs: Usable with digital JTAG boundary scan Adds analog testability – both controllability and observability Eliminates large area needed for analog test points CONs: May have a 5 % measurement error C-switch sampling devices couple all probe points capacitively, even with test bus off – requires more elaborate (larger) switches Stringent limit on how far data can move through the bus before it must be digitized to retain accuracy April 29, 2001 Essentials of Test: Agrawal & Bushnell

284 Analog Test Bus Diagram
April 29, 2001 Essentials of Test: Agrawal & Bushnell

285 Analog Boundary Module
April 29, 2001 Essentials of Test: Agrawal & Bushnell

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Chaining of ICs April 29, 2001 Essentials of Test: Agrawal & Bushnell

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System Test April 29, 2001 Essentials of Test: Agrawal & Bushnell

288 A System and Its Testing
A system is an organization of components (hardware/software parts and subsystems) with capability to perform useful functions. Functional test verifies integrity of system: Checks for presence and sanity of subsystems Checks for system specifications Executes selected (critical) functions Diagnostic test isolates faulty part: For field maintenance isolates lowest replaceable unit (LRU), e.g., a board, disc drive, or I/O subsystem For shop repair isolates shop replaceable unit (SRU), e.g., a faulty chip on a board Diagnostic resolution is the number of suspected faulty units identified by test; fewer suspects mean higher resolution April 29, 2001 Essentials of Test: Agrawal & Bushnell

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Functional Test All or selected (critical) operations executed with non-exhaustive data. Tests are a subset of design verification tests (test-benches). Software test metrics used: statement, branch and path coverages; provide low (~70%) structural hardware fault coverage. Examples: Microprocessor test – all instructions with random data (David, 1998). Instruction-set fault model – wrong instruction is executed (Thatte and Abraham, IEEETC-1980). April 29, 2001 Essentials of Test: Agrawal & Bushnell

290 Gate-Level Diagnosis Karnaugh map Logic circuit b a d T2 T1 b e c a T3
(shaded squares are true outputs) Logic circuit b a d T2 T1 b e c a T3 T4 c Stuck-at fault tests: T1 = 010 T2 = 011 T3 = 100 T4 = 110 April 29, 2001 Essentials of Test: Agrawal & Bushnell

291 Gate Replacement Fault
Faulty circuit (OR replaced by AND) Karnaugh map (faulty output shown in red) b a d T2 T1 b e c a T3 T4 c Stuck-at fault tests: T1 = 010 (pass) T2 = 011 (fail) T3 = 100 (pass) T4 = 110 (fail) April 29, 2001 Essentials of Test: Agrawal & Bushnell

292 Essentials of Test: Agrawal & Bushnell
Fault Dictionary Fault Test syndrome t1 t t3 t4 No fault a0, b0, d0 a1 b1 c0 c1, d1, e1 e0 1 1 1 1 a0 : Line a stuck- at-0 ti = 0, if Ti passes = 1, if Ti fails April 29, 2001 Essentials of Test: Agrawal & Bushnell

293 Diagnosis with Dictionary
Dictionary look-up with minimum Hamming distance Fault Test syndrome Diagnosis t1 t2 t3 t4 OR AND e0 OR-bridge (a,c) b1 OR NOR c1, d1, e1, e0 April 29, 2001 Essentials of Test: Agrawal & Bushnell

294 Essentials of Test: Agrawal & Bushnell
Diagnostic Tree No fault found T3 T2 b1 c0 OR bridge (a,c) T1 Pass: t4=0 a1 T3 a1, c1, d1, e1 c1, d1, e1 T4 a0, b0, d0 Fail: t4=1 T2 a0, b0, d0, e0 e0 OR AND OR NOR April 29, 2001 Essentials of Test: Agrawal & Bushnell

295 System Test: A DFT Problem
Given the changing scenario in VLSI: Mixed-signal circuits System-on-a-chip Multi-chip modules Intellectual property (IP) cores Prepare the engineer for designing testable, i.e., manufacturable, VLSI systems. April 29, 2001 Essentials of Test: Agrawal & Bushnell

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Partitioning for Test Partition according to test methodology: Logic blocks Memory blocks Analog blocks Provide test access: Boundary scan Analog test bus Provide test-wrappers (also called collars) for cores. April 29, 2001 Essentials of Test: Agrawal & Bushnell

297 Test-Wrapper for a Core
Test-wrapper (or collar) is the logic added around a core to provide test access to the embedded core. Test-wrapper provides: For each core input terminal A normal mode – Core terminal driven by host chip An external test mode – Wrapper element observes core input terminal for interconnect test An internal test mode – Wrapper element controls state of core input terminal for testing the logic inside core For each core output terminal A normal mode – Host chip driven by core terminal An external test mode – Host chip is driven by wrapper element for interconnect test An internal test mode – Wrapper element observes core outputs for core test April 29, 2001 Essentials of Test: Agrawal & Bushnell

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A Test-Wrapper Scan chain to/from TAP from/to External Test pins Wrapper elements Core Functional core inputs core outputs Wrapper test controller April 29, 2001 Essentials of Test: Agrawal & Bushnell

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Overhead Estimate Rent’s rule: For a logic block the number of gates G and the number of terminals t are related by t = K Ga where 1 < K < 5, and a ~ 0.5. Assume that block area A is proportional to G, i.e., t is proportional to A Since test logic is added to each terminal t, Test logic added to terminals Overhead = ~ A –0.5 A April 29, 2001 Essentials of Test: Agrawal & Bushnell

300 DFT Architecture for SOC
Test source Test sink User defined test access mechanism (TAM) Func. outputs Functional outputs Functional inputs Func. inputs Module 1 Module N Test wrapper Test wrapper Instruction register control Test access port (TAP) Serial instruction data TDI SOC inputs TCK TMS TRST TDO SOC outputs April 29, 2001 Essentials of Test: Agrawal & Bushnell

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DFT Components Test source: Provides test vectors via on-chip LFSR, counter, ROM, or off-chip ATE. Test sink: Provides output verification using on-chip signature analyzer, or off-chip ATE. Test access mechanism (TAM): User-defined test data communication structure; carries test signals from source to module, and module to sink; tests module interconnects via test-wrappers; TAM may contain bus, boundary-scan and analog test bus components. Test controller: Boundary-scan test access port (TAP); receives control signals from outside; serially loads test instructions in test-wrappers. April 29, 2001 Essentials of Test: Agrawal & Bushnell

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Summary Functional test: verify system hardware, software, function and performance; pass/fail test with limited diagnosis; high (~100%) software coverage metrics; low (~70%) structural fault coverage. Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree. SOC design for testability: Partition SOC into blocks of logic, memory and analog circuitry, often on architectural boundaries. Provide external or built-in tests for blocks. Provide test access via boundary scan and/or analog test bus. Develop interconnect tests and system functional tests. Develop diagnostic procedures. April 29, 2001 Essentials of Test: Agrawal & Bushnell


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