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April 29, 2001Essentials of Test: Agrawal & Bushnell1 Essentials of Testing Vishwani D. Agrawal Agere Systems, Murray Hill, NJ 47974 Michael.

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Presentation on theme: "April 29, 2001Essentials of Test: Agrawal & Bushnell1 Essentials of Testing Vishwani D. Agrawal Agere Systems, Murray Hill, NJ 47974 Michael."— Presentation transcript:

1 April 29, 2001Essentials of Test: Agrawal & Bushnell1 Essentials of Testing Vishwani D. Agrawal Agere Systems, Murray Hill, NJ Michael L. Bushnell ECE Dept., Rutgers University Piscataway, NJ Presented at the VLSI Test Symposium 2001

2 April 29, 2001Essentials of Test: Agrawal & Bushnell2 Part I INTRODUCTION TO TESTING

3 April 29, 2001Essentials of Test: Agrawal & Bushnell3 VLSI Realization Process Determine requirements Write specifications Design synthesis and Verification Fabrication Manufacturing test Chips to customer Customer’s need Test development

4 April 29, 2001Essentials of Test: Agrawal & Bushnell4 Definitions n Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. n Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. n Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

5 April 29, 2001Essentials of Test: Agrawal & Bushnell5 Real Tests n Based on analyzable fault models, which may not map on real defects. n Incomplete coverage of modeled faults due to high complexity. n Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. n Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.

6 April 29, 2001Essentials of Test: Agrawal & Bushnell6 Costs of Testing n Design for testability (DFT)  Chip area overhead and yield reduction  Performance overhead n Software processes of test  Test generation and fault simulation  Test programming and debugging n Manufacturing test  Automatic test equipment (ATE) capital cost  Test center operational cost

7 April 29, 2001Essentials of Test: Agrawal & Bushnell7 Present and Future* Transistors/sq. cm M M Pin count Clock rate (MHz) Power (Watts) Feature size (micron) * SIA Roadmap, IEEE Spectrum, July 1999

8 April 29, 2001Essentials of Test: Agrawal & Bushnell8 Cost of Manufacturing Testing in 2000AD n GHz, analog instruments,1,024 digital pins: ATE purchase price  = $1.2M + 1,024 x $3,000 = $4.272M n Running cost (five-year linear depreciation)  = Depreciation + Maintenance + Operation  = $0.854M + $0.085M + $0.5M  = $1.439M/year n Test cost (24 hour ATE operation)  = $1.439M/(365 x 24 x 3,600)  = 4.5 cents/second

9 April 29, 2001Essentials of Test: Agrawal & Bushnell9 Course Outline n Part I:  Basic concepts and definitions  Test process and ATE  Test economics and product quality  Fault modeling n Part II:  Logic and fault simulation  Combinational circuit ATPG  Sequential circuit ATPG  Memory test  Analog test  Delay test and IDDQ test n Part III:  Scan design  BIST  Boundary scan and analog test bus  System test and core-based design

10 April 29, 2001Essentials of Test: Agrawal & Bushnell10 VLSI Testing Process and Equipment

11 April 29, 2001Essentials of Test: Agrawal & Bushnell11 Testing Principle

12 April 29, 2001Essentials of Test: Agrawal & Bushnell12 Automatic Test Equipment Components n Consists of:  Powerful computer  Powerful 32-bit Digital Signal Processor (DSP) for analog testing  Test Program (written in high-level language) running on the computer  Probe Head (actually touches the bare or packaged chip to perform fault detection experiments)  Probe Card or Membrane Probe (contains electronics to measure signals on chip pin or pad)

13 April 29, 2001Essentials of Test: Agrawal & Bushnell13 Characterization Test n Worst-case test  Choose test that passes/fails chips  Select statistically significant sample of chips  Repeat test for every combination of 2+ environmental variables  Plot results in Schmoo plot  Diagnose and correct design errors n Continue throughout production life of chips to improve design and process to increase yield

14 April 29, 2001Essentials of Test: Agrawal & Bushnell14 Schmoo Plot

15 April 29, 2001Essentials of Test: Agrawal & Bushnell15 Manufacturing Test n Determines whether manufactured chip meets specs n Must cover high % of modeled faults n Must minimize test time (to control cost) n No fault diagnosis n Tests every device on chip n Test at speed of application or speed guaranteed by supplier

16 April 29, 2001Essentials of Test: Agrawal & Bushnell16 Burn-in or Stress Test n Process:  Subject chips to high temperature & over- voltage supply, while running production tests n Catches:  Infant mortality cases – these are damaged chips that will fail in the first 2 days of operation – causes bad devices to actually fail before chips are shipped to customers  Freak failures – devices having same failure mechanisms as reliable devices

17 April 29, 2001Essentials of Test: Agrawal & Bushnell17 Types of Manufacturing Tests n Wafer sort or probe test – done before wafer is scribed and cut into chips  Includes test site characterization – specific test devices are checked with specific patterns to measure: n Gate threshold n Polysilicon field threshold n Poly sheet resistance, etc. n Packaged device tests

18 April 29, 2001Essentials of Test: Agrawal & Bushnell18 Sub-types of Tests n Parametric – measures electrical properties of pin electronics – delay, voltages, currents, etc. – fast and cheap n Functional – used to cover very high % of modeled faults – test every transistor and wire in digital circuits – long and expensive – main topic of tutorial

19 April 29, 2001Essentials of Test: Agrawal & Bushnell19 Two Different Meanings of Functional Test n ATE and Manufacturing World – any vectors applied to cover high % of faults during manufacturing test n Automatic Test-Pattern Generation World – testing with verification vectors, which determine whether hardware matches its specification – typically have low fault coverage (< 70 %)

20 April 29, 2001Essentials of Test: Agrawal & Bushnell20 Test Specifications & Plan n Test Specifications:  Functional Characteristics  Type of Device Under Test (DUT)  Physical Constraints – Package, pin numbers, etc.  Environmental Characteristics – supply, temperature, humidity, etc.  Reliability – acceptance quality level (defects/million), failure rate, etc. n Test plan generated from specifications  Type of test equipment to use  Types of tests  Fault coverage requirement

21 April 29, 2001Essentials of Test: Agrawal & Bushnell21 ADVANTEST Model T6682 ATE

22 April 29, 2001Essentials of Test: Agrawal & Bushnell22 LTX FUSION HF ATE

23 April 29, 2001Essentials of Test: Agrawal & Bushnell23 Summary n Parametric tests – determine whether pin electronics system meets digital logic voltage, current, and delay time specs n Functional tests – determine whether internal logic/analog sub-systems behave correctly n ATE Cost Problems  Pin inductance (expensive probing)  Multi-GHz frequencies  High pin count (1024) n ATE Cost Reduction  Multi-Site Testing  DFT methods like Built-In Self-Test

24 April 29, 2001Essentials of Test: Agrawal & Bushnell24 Test Economics and Product Quality

25 April 29, 2001Essentials of Test: Agrawal & Bushnell25 Economics of Design for Testability (DFT) n Consider life-cycle cost; DFT on chip may impact the costs at board and system levels. n Weigh costs against benefits n Cost examples: reduced yield due to area overhead, yield loss due to non-functional tests n Benefit examples: Reduced ATE cost due to self-test, inexpensive alternatives to burn-in test

26 April 29, 2001Essentials of Test: Agrawal & Bushnell26 Benefits and Costs of DFT Design and test + / - Fabri- cation + Manuf. Test - Level Chips Boards System Maintenance test - Diagnosis and repair - Service interruption - + Cost increase - Cost saving +/- Cost increase may balance cost reduction

27 April 29, 2001Essentials of Test: Agrawal & Bushnell27 VLSI Chip Yield n A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. n A chip with no manufacturing defect is called a good chip. n Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. n Cost of a chip: Cost of fabricating and testing a wafer Yield x Number of chip sites on the wafer

28 April 29, 2001Essentials of Test: Agrawal & Bushnell28 Defect Level or Reject Ratio n Defect level (DL) is the ratio of faulty chips among the chips that pass tests. n DL is measured as parts per million (ppm). n DL is a measure of the effectiveness of tests. n DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable.

29 April 29, 2001Essentials of Test: Agrawal & Bushnell29 Determination of DL n From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL. n From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL.

30 April 29, 2001Essentials of Test: Agrawal & Bushnell30 Modified Yield Equation n Three parameters: n Fault density, f = average number of stuck-at faults per unit chip area Fault clustering parameter,  n Stuck-at fault coverage, T n The modified yield equation: Y (T ) = (1 + TAf /  ) -  Assuming that tests with 100% fault coverage (T =1.0) remove all faulty chips, Y = Y (1) = (1 + Af /  ) - 

31 April 29, 2001Essentials of Test: Agrawal & Bushnell31 Defect Level Y (T ) - Y (1) DL (T ) = Y (T ) (  + TAf )  = (  + Af )  Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A,  is the fault clustering parameter. Af and  are determined by test data analysis.

32 April 29, 2001Essentials of Test: Agrawal & Bushnell32 Example: SEMATECH Chip n Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont n 116,000 equivalent (2-input NAND) gates n 304-pin package, 249 I/O n Clock: 40MHz, some parts 50MHz 0.45  CMOS, 3.3V, 9.4mm x 8.8mm area n Full scan, 99.79% fault coverage n Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock n Data obtained courtesy of Phil Nigh (IBM)

33 April 29, 2001Essentials of Test: Agrawal & Bushnell33 Test Coverage from Fault Simulator Stuck-at fault coverage Vector number

34 April 29, 2001Essentials of Test: Agrawal & Bushnell34 Measured Chip Fallout Vector number Measured chip fallout

35 April 29, 2001Essentials of Test: Agrawal & Bushnell35 Model Fitting Y (T ) for Af = 2.1 and  = Measured chip fallout Y (1) = Chip fallout and computed 1-Y (T ) Stuck-at fault coverage, T Chip fallout vs. fault coverage

36 April 29, 2001Essentials of Test: Agrawal & Bushnell36 Computed DL Stuck-at fault coverage (%) Defect level in ppm 237,700 ppm (Y = 76.23%)

37 April 29, 2001Essentials of Test: Agrawal & Bushnell37 Summary VLSI yield depends on two process parameters, defect density (d ) and clustering parameter (  ) n Yield drops as chip area increases; low yield means high cost n Fault coverage measures the test quality n Defect level (DL) or reject ratio is a measure of chip quality n DL can be determined by an analysis of test data n For high quality: DL < 500 ppm, fault coverage ~ 99%

38 April 29, 2001Essentials of Test: Agrawal & Bushnell38 Fault Modeling

39 April 29, 2001Essentials of Test: Agrawal & Bushnell39 Why Model Faults? n I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) n Real defects (often mechanical) too numerous and often not analyzable n A fault model identifies targets for testing n A fault model makes analysis possible n Effectiveness measurable by experiments

40 April 29, 2001Essentials of Test: Agrawal & Bushnell40 Some Real Defects in Chips n Processing defects n Missing contact windows n Parasitic transistors n Oxide breakdown n... n Material defects n Bulk defects (cracks, crystal imperfections) n Surface impurities (ion migration) n... n Time-dependent failures n Dielectric breakdown n Electromigration n... n Packaging failures n Contact degradation n Seal leaks n... Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981.

41 April 29, 2001Essentials of Test: Agrawal & Bushnell41 Observed PCB Defects Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Occurrence frequency (%) Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

42 April 29, 2001Essentials of Test: Agrawal & Bushnell42 Common Fault Models n Single stuck-at faults n Transistor open and short faults n Memory faults n PLA faults (stuck-at, cross-point, bridging) n Functional faults (processors) n Delay faults (transition, path) n Analog faults n For more examples, see Section 4.4 (p ) of the book.

43 April 29, 2001Essentials of Test: Agrawal & Bushnell43 Single Stuck-at Fault n Three properties define a single stuck-at fault n Only one line is faulty n The faulty line is permanently set to 0 or 1 n The fault can be at an input or output of a gate n Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults a b c d e f 1 0 g h i 1 s-a-0 j k z 0(1) 1(0) 1 Test vector for h s-a-0 fault Good circuit value Faulty circuit value

44 April 29, 2001Essentials of Test: Agrawal & Bushnell44 Fault Equivalence n Number of fault sites in a Boolean gate circuit = #PI + #gates + #(fanout branches). n Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. n If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. n Fault collapsing: All single faults of a logic circuits can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.

45 April 29, 2001Essentials of Test: Agrawal & Bushnell45 Equivalence Rules sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 AND NAND OR NOR WIRE NOT FANOUT

46 April 29, 2001Essentials of Test: Agrawal & Bushnell46 Equivalence Example sa0 sa1 Faults in red removed by equivalence collapsing 20 Collapse ratio = =

47 April 29, 2001Essentials of Test: Agrawal & Bushnell47 Fault Dominance n If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1. n Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list. n When dominance fault collapsing is used, it is sufficient to consider only the input faults of Boolean gates. See the next example. n In a tree circuit (without fanouts) PI faults form a dominance collaped fault set. n If two faults dominate each other then they are equivalent.

48 April 29, 2001Essentials of Test: Agrawal & Bushnell48 Dominance Example s-a-1 F1 s-a-1 F All tests of F2 Only test of F1 s-a-1 s-a-0 A dominance collapsed fault set

49 April 29, 2001Essentials of Test: Agrawal & Bushnell49 Checkpoints n Primary inputs and fanout branches of a combinational circuit are called checkpoints. n Checkpoint theorem: A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. Total fault sites = 16 Checkpoints ( ) = 10

50 April 29, 2001Essentials of Test: Agrawal & Bushnell50 Classes of Stuck-at Faults n Following classes of single stuck-at faults are identified by fault simulators: n Potentially-detectable fault -- Test produces an unknown (X) state at PO; detection is probabilistic, usually with 50% probability. n Initialization fault -- Fault prevents initialization of the faulty circuit; can be detected as a potentially- detectable fault. n Hyperactive fault -- Fault induces much internal signal activity without reaching PO. n Redundant fault -- No test exists for the fault. n Untestable fault -- Test generator is unable to find a test.

51 April 29, 2001Essentials of Test: Agrawal & Bushnell51 Summary n Fault models are analyzable approximations of defects and are essential for a test methodology. n For digital logic single stuck-at fault model offers best advantage of tools and experience. n Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. n Stuck-short and delay faults and technology- dependent faults require special tests. n Memory and analog circuits need other specialized fault models and tests.

52 April 29, 2001Essentials of Test: Agrawal & Bushnell52 Part II TEST METHODS Logic Simulation

53 April 29, 2001Essentials of Test: Agrawal & Bushnell53 Simulation Defined n Definition: Simulation refers to modeling of a design, its function and performance. n A software simulator is a computer program; an emulator is a hardware simulator. n Simulation is used for design verification: n Validate assumptions n Verify logic n Verify performance (timing) n Types of simulation: n Logic or switch level n Timing n Circuit n Fault

54 April 29, 2001Essentials of Test: Agrawal & Bushnell54 Simulation for Verification True-value simulation Specification Design (netlist) Input stimuli Computed responses Response analysis Synthesis Design changes

55 April 29, 2001Essentials of Test: Agrawal & Bushnell55 Modeling for Simulation n Modules, blocks or components described by n Input/output (I/O) function n Delays associated with I/O signals n Examples: binary adder, Boolean gates, FET, resistors and capacitors n Interconnects represent n ideal signal carriers, or n ideal electrical conductors n Netlist: a format (or language) that describes a design as an interconnection of modules. Netlist may use hierarchy.

56 April 29, 2001Essentials of Test: Agrawal & Bushnell56 Example: A Full-Adder HA; inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e); a b c d e f HA FA; inputs: A, B, C; outputs: Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry); HA1 HA2 A B C D E F Sum Carry

57 April 29, 2001Essentials of Test: Agrawal & Bushnell57 CaCa Logic Model of MOS Circuit CcCc CbCb V DD a b c pMOS FETs nMOS FETs C a, C b and C c are parasitic capacitances DcDc DaDa c a b D a and D b are interconnect or propagation delays D c is inertial delay of gate DbDb

58 April 29, 2001Essentials of Test: Agrawal & Bushnell58 Options for Inertial Delay (simulation of a NAND gate) b a c (CMOS) Time units 0 5 c (zero delay) c (unit delay) c (multiple delay) c (minmax delay) Inputs Logic simulation min =2, max =5 rise=5, fall=5 Transient region Unknown (X) X

59 April 29, 2001Essentials of Test: Agrawal & Bushnell59 Signal States n Two-states (0, 1) can be used for purely combinational logic with zero-delay. n Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization. n Four-states (0, 1, X, Z) are essential for MOS devices. See example below. n Analog signals are used for exact timing of digital logic and for analog circuits. 0 0 Z (hold previous value)

60 April 29, 2001Essentials of Test: Agrawal & Bushnell60 Modeling Levels Circuit description Programming language-like HDL Connectivity of Boolean gates, flip-flops and transistors Transistor size and connectivity, node capacitances Transistor technology data, connectivity, node capacitances Tech. Data, active/ passive component connectivity Signal values 0, 1 0, 1, X and Z 0, 1 and X Analog voltage Analog voltage, current Timing Clock boundary Zero-delay unit-delay, multiple- delay Zero-delay Fine-grain timing Continuous time Modeling level Function, behavior, RTL Logic Switch Timing Circuit Application Architectural and functional verification Logic verification and test Logic verification Timing verification Digital timing and analog circuit verification

61 April 29, 2001Essentials of Test: Agrawal & Bushnell61 True-Value Simulation Algorithms n Compiled-code simulation n Applicable to zero-delay combinational logic n Also used for cycle-accurate synchronous sequential circuits for logic verification n Efficient for highly active circuits, but inefficient for low-activity circuits n High-level (e.g., C language) models can be used n Event-driven simulation n Only gates or modules with input events are evaluated (event means a signal change) n Delays can be accurately simulated for timing verification n Efficient for low-activity circuits n Can be extended for fault simulation

62 April 29, 2001Essentials of Test: Agrawal & Bushnell62 Compiled-Code Algorithm n Step 1: Levelize combinational logic and encode in a compilable programming language n Step 2: Initialize internal state variables (flip- flops) n Step 3: For each input vector  Set primary input variables  Repeat (until steady-state or max. iterations) n Execute compiled code  Report or save computed variables

63 April 29, 2001Essentials of Test: Agrawal & Bushnell63 Event-Driven Algorithm (Example) a =1 b =1 c =1 0 d = 0 e =1 f =0 g =1 Time, t g t = Scheduled events c = 0 d = 1, e = 0 g = 0 f = 1 g = 1 Activity list d, e f, g g Time stack

64 April 29, 2001Essentials of Test: Agrawal & Bushnell64 Efficiency of Event- driven Simulator n Simulates events (value changes) only n Speed up over compiled-code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change Large logic block without activity Steady 0 0 to 1 event Steady 0 (no event)

65 April 29, 2001Essentials of Test: Agrawal & Bushnell65 Summary n Logic or true-value simulators are essential tools for design verification. n Verification vectors and expected responses are generated (often manually) from specifications. n A logic simulator can be implemented using either compiled-code or event-driven method. n Per vector complexity of a logic simulator is approximately linear in circuit size. n Modeling level determines the evaluation procedures used in the simulator.

66 April 29, 2001Essentials of Test: Agrawal & Bushnell66 Fault Simulation

67 April 29, 2001Essentials of Test: Agrawal & Bushnell67 Problem and Motivation n Fault simulation Problem: Given n A circuit n A sequence of test vectors n A fault model  Determine n Fault coverage - fraction (or percentage) of modeled faults detected by test vectors n Set of undetected faults n Motivation n Determine test quality and in turn product quality n Find undetected fault targets to improve tests

68 April 29, 2001Essentials of Test: Agrawal & Bushnell68 Fault simulator in a VLSI Design Process Verified design netlist Verification input stimuli Fault simulatorTest vectors Modeled fault list Test generator Test compactor Fault coverage ? Remove tested faults Delete vectors Add vectors Low Adequate Stop

69 April 29, 2001Essentials of Test: Agrawal & Bushnell69 Fault Simulation Scenario n Circuit model: mixed-level n Mostly logic with some switch-level for high- impedance (Z) and bidirectional signals n High-level models (memory, etc.) with pin faults n Signal states: logic n Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits n Four states (0, 1, X, Z) for sequential MOS circuits n Timing: n Zero-delay for combinational and synchronous circuits n Mostly unit-delay for circuits with feedback

70 April 29, 2001Essentials of Test: Agrawal & Bushnell70 Fault Simulation Scenario (continued) n Faults: n Mostly single stuck-at faults n Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use n Equivalence fault collapsing of single stuck-at faults n Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis n Fault sampling -- a random sample of faults is simulated when the circuit is large

71 April 29, 2001Essentials of Test: Agrawal & Bushnell71 Fault Simulation Algorithms n Serial n Parallel n Deductive n Concurrent n Differential

72 April 29, 2001Essentials of Test: Agrawal & Bushnell72 Serial Algorithm n Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list: n Modify netlist by injecting one fault n Simulate modified netlist, vector by vector, comparing responses with saved responses n If response differs, report fault detection and suspend simulation of remaining vectors n Advantages: n Easy to implement; needs only a true-value simulator, less memory n Most faults, including analog faults, can be simulated

73 April 29, 2001Essentials of Test: Agrawal & Bushnell73 Serial Algorithm (Cont.) n Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits n Alternative: Simulate many faults together Test vectors Fault-free circuit Circuit with fault f1 Circuit with fault f2 Circuit with fault fn Comparator f1 detected? Comparator f2 detected? Comparator fn detected?

74 April 29, 2001Essentials of Test: Agrawal & Bushnell74 Parallel Fault Simulation n Compiled-code method; best with two- states (0,1) n Exploits inherent bit-parallelism of logic operations on computer words n Storage: one word per line for two-state simulation n Multi-pass simulation: Each pass simulates w-1 new faults, where w is the machine word length n Speed up over serial method ~ w-1 n Not suitable for circuits with timing-critical and non-Boolean logic

75 April 29, 2001Essentials of Test: Agrawal & Bushnell75 Parallel Fault Sim. Example a b c d e f g s-a-1 s-a c s-a-0 detected Bit 0: fault-free circuit Bit 1: circuit with c s-a-0 Bit 2: circuit with f s-a-1

76 April 29, 2001Essentials of Test: Agrawal & Bushnell76 Deductive Fault Simulation n One-pass simulation n Each line k contains a list L k of faults detectable on k n Following true-value simulation of each vector, fault lists of all gate output lines are updated using set-theoretic rules, signal values, and gate input fault lists n PO fault lists provide detection data n Limitations: n Set-theoretic rules difficult to derive for non- Boolean gates n Gate delays are difficult to use

77 April 29, 2001Essentials of Test: Agrawal & Bushnell77 Concurrent Fault Simulation n Event-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault-free circuit. n A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any. n All events of fault-free and all faulty circuits are implicitly simulated. n Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility.) n Faster than other methods, but uses most memory.

78 April 29, 2001Essentials of Test: Agrawal & Bushnell78 Conc. Fault Sim. Example a b c d e f g a0a0 b0b0 c0c0 e0e0 a0a0 b0b0 b0b0 c0c0 e0e0 d0d0 d0d0 g0g0 f1f1 f1f1

79 April 29, 2001Essentials of Test: Agrawal & Bushnell79 Fault Sampling n A randomly selected subset (sample) of faults is simulated. n Measured coverage in the sample is used to estimate fault coverage in the entire circuit. n Advantage: Saving in computing resources (CPU time and memory.) n Disadvantage: Limited data on undetected faults.

80 April 29, 2001Essentials of Test: Agrawal & Bushnell80 Random Sampling Model All faults with a fixed but unknown coverage Detected fault Undetected fault Random picking N p = total number of faults (population size) C = fault coverage (unknown) N s = sample size N s << N p c = sample coverage (a random variable)

81 April 29, 2001Essentials of Test: Agrawal & Bushnell81 Probability Density of Sample Coverage, c (x--C )  2 p (x ) = Prob(x < c < x +dx ) = e  2  1/2 p (x ) C C +3  C -3  1.0 x Sample coverage C (1 - C) Variance  2 = N s Mean = C Sampling error   x

82 April 29, 2001Essentials of Test: Agrawal & Bushnell82 Sampling Error Bounds C (1 - C ) | x - C | = 3   1/2 N s Solving the quadratic equation for C, we get the 3-sigma (99.7% confidence) estimate: 4.5 C 3  = x [ N s x (1 - x )] 1/2 N s Where N s is sample size and x is the measured fault coverage in the sample. Example: A circuit with 39,096 faults has an actual fault coverage of 87.1%. The measured coverage in a random sample of 1,000 faults is 88.7%. The above formula gives an estimate of 88.7% 3%. CPU time for sample simulation was about 10% of that for all faults.  

83 April 29, 2001Essentials of Test: Agrawal & Bushnell83 Summary n Fault simulator is an essential tool for test development. n Concurrent fault simulation algorithm offers the best choice. n For restricted class of circuits (combinational and synchronous sequential with only Boolean primitives), differential algorithm can provide better speed and memory efficiency (Section ) n For large circuits, the accuracy of random fault sampling only depends on the sample size (1,000 to 2,000 faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator.

84 April 29, 2001Essentials of Test: Agrawal & Bushnell84 Combinational Automatic Test-pattern Generation

85 April 29, 2001Essentials of Test: Agrawal & Bushnell85 Functional vs. Structural ATPG

86 April 29, 2001Essentials of Test: Agrawal & Bushnell86 Carry Circuit

87 April 29, 2001Essentials of Test: Agrawal & Bushnell87 Functional vs. Structural (Continued) n Functional ATPG – generate complete set of tests for circuit input-output combinations  129 inputs, 65 outputs:  = 680,564,733,841,876,926,926,749, 214,863,536,422,912 patterns  Using 1 GHz ATE, would take 2.15 x years n Structural test:  No redundant adder hardware, 64 bit slices  Each with 27 faults (using fault equivalence)  At most 64 x 27 = 1728 faults (tests)  Takes s on 1 GHz ATE n Designer gives small set of functional tests – augment with structural tests to boost coverage to 98 + %

88 April 29, 2001Essentials of Test: Agrawal & Bushnell88 Definition of Automatic Test-Pattern Generator n Operations on digital hardware:  Inject fault into circuit modeled in computer  Use various ways to activate and propagate fault effect through hardware to circuit output  Output flips from expected to faulty signal n Electron-beam (E-beam) test observes internal signals – “picture” of nodes charged to 0 and 1 in different colors  Too expensive n Scan design – add test hardware to all flip-flops to make them a giant shift register in test mode  Can shift state in, scan state out  Widely used – makes sequential test combinational  Costs: 5 to 20% chip area, circuit delay, extra pin, longer test sequence

89 April 29, 2001Essentials of Test: Agrawal & Bushnell89 Circuit and Binary Decision Tree

90 April 29, 2001Essentials of Test: Agrawal & Bushnell90 Algorithm Completeness n Definition: Algorithm is complete if it ultimately can search entire binary decision tree, as needed, to generate a test n Untestable fault – no test for it even after entire tree searched n Combinational circuits only – untestable faults are redundant, showing the presence of unnecessary hardware

91 April 29, 2001Essentials of Test: Agrawal & Bushnell91 Algebras: Roth’s 5-Valued and Muth’s 9-Valued Symbol D 0 1 X G0 G1 F0 F1 Meaning 1/0 0/1 0/0 1/1 X/X 0/X 1/X X/0 X/1 Failing Machine X 0 1 Good Machine X 0 1 X Roth’s Algebra Muth’s Additions

92 April 29, 2001Essentials of Test: Agrawal & Bushnell92 Random-Pattern Generation n Flow chart for method n Use to get tests for % of faults, then switch to D-algorithm or other ATPG for rest

93 April 29, 2001Essentials of Test: Agrawal & Bushnell93 Path Sensitization Method Circuit Example 1 Fault Sensitization 2 Fault Propagation 3 Line Justification

94 April 29, 2001Essentials of Test: Agrawal & Bushnell94 Path Sensitization Method Circuit Example  Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i 1 0 D D D D D

95 April 29, 2001Essentials of Test: Agrawal & Bushnell95 Path Sensitization Method Circuit Example  Try simultaneous paths f – h – k – L and g – i – j – k – L blocked at k because D-frontier (chain of D or D) disappears 1 D D D D D 1 1

96 April 29, 2001Essentials of Test: Agrawal & Bushnell96 Path Sensitization Method Circuit Example  Final try: path g – i – j – k – L – test found! 0 D D D 1 D D 1 0 1

97 April 29, 2001Essentials of Test: Agrawal & Bushnell97 Computational Complexity n Ibarra and Sahni analysis – NP-Complete (no polynomial expression found for compute time, presumed to be exponential) n Worst case: no_pi inputs, 2 no_pi input combinations no_ff flip-flops, 4 no_ff initial flip-flop states (good machine 0 or 1 bad machine 0 or 1) work to forward or reverse simulate n logic gates  n n Complexity: O (n x 2 no_pi x 4 no_ff ) 

98 April 29, 2001Essentials of Test: Agrawal & Bushnell98 History of Algorithm Speedups Algorithm D-ALG PODEM FAN TOPS SOCRATES Waicukauski et al. EST TRAN Recursive learning Tafertshofer et al. Est. speedup over D-ALG (normalized to D-ALG time) ATPG System 2189 ATPG System 8765 ATPG System 3005 ATPG System Year † † † †

99 April 29, 2001Essentials of Test: Agrawal & Bushnell99 Analog Fault Modeling Impractical for Logic ATPG n Huge # of different possible analog faults in digital circuit n Exponential complexity of ATPG algorithm – a 20 flip-flop circuit can take days of computing  Cannot afford to go to a lower-level model n Most test-pattern generators for digital circuits cannot even model at the transistor switch level (see textbook for 5 examples of switch-level ATPG)

100 April 29, 2001Essentials of Test: Agrawal & Bushnell100 Fault Cone and D-frontier n Fault Cone -- Set of hardware affected by fault n D-frontier – Set of gates closest to POs with fault effect(s) at input(s) Fault Cone D-frontier

101 April 29, 2001Essentials of Test: Agrawal & Bushnell101 Forward Implication n Results in logic gate inputs that are significantly labeled so that output is uniquely determined n AND gate forward implication table:

102 April 29, 2001Essentials of Test: Agrawal & Bushnell102 Backward Implication n Unique determination of all gate inputs when the gate output and some of the inputs are given

103 April 29, 2001Essentials of Test: Agrawal & Bushnell103 Implication Stack n Push-down stack. Records:  Each signal set in circuit by ATPG  Whether alternate signal value already tried  Portion of binary search tree already searched

104 April 29, 2001Essentials of Test: Agrawal & Bushnell104 Implication Stack after Backtrack E F BB F F 1 Unexplored Present Assignment Searched and Infeasible

105 April 29, 2001Essentials of Test: Agrawal & Bushnell105 Branch-and-Bound Search n Efficiently searches binary search tree n Branching – At each tree level, selects which input variable to set to what value n Bounding – Avoids exploring large tree portions by artificially restricting search decision choices  Complete exploration is impractical  Uses heuristics

106 April 29, 2001Essentials of Test: Agrawal & Bushnell106 Sequential Automatic Test-pattern Generation

107 April 29, 2001Essentials of Test: Agrawal & Bushnell107 Sequential Circuits n A sequential circuit has memory in addition to combinational logic. n Test for a fault in a sequential circuit is a sequence of vectors, which n Initializes the circuit to a known state n Activates the fault, and n Propagates the fault effect to a primary output n Methods of sequential circuit ATPG n Time-frame expansion methods n Simulation-based methods

108 April 29, 2001Essentials of Test: Agrawal & Bushnell108 Concept of Time-Frames n If the test sequence for a single stuck-at fault contains n vectors, n Replicate combinational logic block n times n Place fault in each block n Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Comb. block Fault Time- frame 0 Time- frame Time- frame -n+1 Unknown or given Init. state Vector 0Vector -1 Vector -n+1 PO 0 PO -1 PO -n+1 State variables Next state

109 April 29, 2001Essentials of Test: Agrawal & Bushnell109 Example for Logic Systems FF2 FF1 A B s-a-1

110 April 29, 2001Essentials of Test: Agrawal & Bushnell110 Five-Valued Logic (Roth) 0,1, D, D, X A B X X X 0 s-a-1 D A B X X X 0 D FF1 FF2 D D Time-frame -1 Time-frame 0

111 April 29, 2001Essentials of Test: Agrawal & Bushnell111 Nine-Valued Logic (Muth) 0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X A B X X X 0 s-a-1 0/1 A B 0/X 0/1 X s-a-1 X/1 FF1 FF2 0/1 X/1 Time-frame -1 Time-frame 0

112 April 29, 2001Essentials of Test: Agrawal & Bushnell112 Implementation of ATPG n Select a PO for fault detection based on drivability analysis. n Place a logic value, 1/0 or 0/1, depending on fault type and number of inversions. n Justify the output value from PIs, considering all necessary paths and adding backward time-frames. n If justification is impossible, then use drivability to select another PO and repeat justification. n If the procedure fails for all reachable POs, then the fault is untestable. n If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, the the fault is potentially detectable.

113 April 29, 2001Essentials of Test: Agrawal & Bushnell113 Complexity of ATPG  Synchronous circuit -- All flip-flops controlled by clocks; PI and PO synchronized with clock:  Cycle-free circuit – No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth.  Cyclic circuit – Contains feedback among flip- flops: May need 9 Nff time-frames, where Nff is the number of flip-flops.  Asynchronous circuit – Higher complexity! Time- Frame 0 Time- Frame max-1 Time- Frame max-2 Time- Frame -2 Time- Frame S0S1 S2 S3 Smax max = Number of distinct vectors with 9-valued elements = 9 Nff

114 April 29, 2001Essentials of Test: Agrawal & Bushnell114 Cycle-Free Circuits n Characterized by absence of cycles among flip-flops and a sequential depth, dseq. n dseq is the maximum number of flip-flops on any path between PI and PO. n Both good and faulty circuits are initializable. n Test sequence length for a fault is bounded by dseq + 1.

115 April 29, 2001Essentials of Test: Agrawal & Bushnell115 Cycle-Free Example F1 F2 F3 Level = 1 2 F1 F2 F3 Level = dseq = 3 s - graph Circuit All faults are testable. See Example 8.6.

116 April 29, 2001Essentials of Test: Agrawal & Bushnell116 Cyclic Circuit Example F1 F2 CNT Z Modulo-3 counter s - graph F1 F2

117 April 29, 2001Essentials of Test: Agrawal & Bushnell117 Modulo-3 Counter n Cyclic structure – Sequential depth is undefined. n Circuit is not initializable. No tests can be generated for any stuck-at fault. n After expanding the circuit to 9 Nff = 81, or fewer, time-frames ATPG program calls any given target fault untestable. n Circuit can only be functionally tested by multiple observations. n Functional tests, when simulated, give no fault coverage.

118 April 29, 2001Essentials of Test: Agrawal & Bushnell118 Adding Initializing Hardware F1 F2 CNT Z Initializable modulo-3 counter s - graph F1 F2 CLR s-a-0 s-a-1 Untestable fault Potentially detectable fault

119 April 29, 2001Essentials of Test: Agrawal & Bushnell119 Benchmark Circuits Circuit PI PO FF Gates Structure Seq. depth Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2) s Cycle-free s Cycle-free s Cyclic s Cyclic

120 April 29, 2001Essentials of Test: Agrawal & Bushnell120 Simulation-based ATPG n Difficulties with time-frame method: n Long initialization sequence n Impossible initialization with three-valued logic (Section 5.3.4) n Circuit modeling limitations n Timing problems – tests can cause races/hazards n High complexity n Inadequacy for asynchronous circuits n Advantages of simulation-based methods n Advanced fault simulation technology n Accurate simulation model exists for verification n Variety of tests – functional, heuristic, random n Used since early 1960s

121 April 29, 2001Essentials of Test: Agrawal & Bushnell121 Using Fault Simulator Fault simulator Vector source: Functional (test-bench), Heuristic (walking 1, etc.), Weighted random, random Fault list Test vectors New faults detected? Stopping criteria (fault coverage, CPU time limit, etc.) satisfied? Stop Update fault list Append vectors Restore circuit state Generate new trial vectors Yes No Yes No Trial vectors

122 April 29, 2001Essentials of Test: Agrawal & Bushnell122 Background n Seshu and Freeman, 1962, Asynchronous circuits, parallel fault simulator, single-input changes vectors. n Breuer, 1971, Random sequences, sequential circuits n Agrawal and Agrawal, 1972, Random vectors followed by D-algorithm, combinational circuits. n Shuler, et al., 1975, Concurrent fault simulator, random vectors, sequential circuits. n Parker, 1976, Adaptive random vectors, combinational circuits. n Agrawal, Cheng and Agrawal, 1989, Directed search with cost-function, concurrent fault simulator, sequential circuits. n Srinivas and Patnaik, 1993, Genetic algorithms; Saab, et al., 1996; Corno, et al., 1996; Rudnick, et al., 1997; Hsiao, et al., 1997.

123 April 29, 2001Essentials of Test: Agrawal & Bushnell123 Genetic Algorithms (GAs) n Theory of evolution by natural selection (Darwin, ) n C. R. Darwin, On the Origin of Species by Means of Natural Selection, London: John Murray, n J. H. Holland, Adaptation in Natural and Artificial Systems, Ann Arbor: University of Michigan Press, n D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning, Reading, Massachusetts: Addison-Wesley, n P. Mazumder and E. M. Rudnick, Genetic Algorithms for VLSI Design, Layout and Test Automation, Upper Saddle River, New Jersey, Prentice Hall PTR, n Basic Idea: Population improves with each generation. n Population n Fitness criteria n Regeneration rules

124 April 29, 2001Essentials of Test: Agrawal & Bushnell124 Strategate Results s1423 s5378 s35932 Total faults 1,515 4,603 39,094 Detected faults 1,414 3,639 35,100 Fault coverage 93.3% 79.1% 89.8% Test vectors 3,943 11, CPU time 1.3 hrs hrs hrs. HP J MB Ref.: M. S. Hsiao, E. M. Rudnick and J. H. Patel, “Dynamic State Traversal for Sequential Circuit Test Generation,” ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 5, no. 3, July 2000.

125 April 29, 2001Essentials of Test: Agrawal & Bushnell125 Summary n Combinational ATPG algorithms are extended: n Time-frame expansion unrolls time as combinational array n Nine-valued logic system n Justification via backward time n Cycle-free circuits: n Require at most dseq time-frames n Always initializable n Cyclic circuits: n May need 9 Nff time-frames n Circuit must be initializable n Partial scan can make circuit cycle-free (Chapter 14) n Asynchronous circuits: n High complexity n Low coverage and unreliable tests n Simulation-based methods are more useful (Section 8.3)

126 April 29, 2001Essentials of Test: Agrawal & Bushnell126 Memory Test

127 April 29, 2001Essentials of Test: Agrawal & Bushnell127 Memory Cells Per Chip

128 April 29, 2001Essentials of Test: Agrawal & Bushnell128 Test Time in Seconds (Memory Size n Bits) n 1 Mb 4 Mb 16 Mb 64 Mb 256 Mb 1 Gb 2 Gb n n X log 2 n n 3/ hr 9.2 hr 73.3 hr hr hr n hr hr hr hr hr hr hr Size Number of Test Algorithm Operations

129 April 29, 2001Essentials of Test: Agrawal & Bushnell129 Fault Types n Fault types:  Permanent -- System is broken and stays broken the same way indefinitely  Transient -- Fault temporarily affects the system behavior, and then the system reverts to the good machine -- time dependency, caused by environmental condition  Intermittent -- Sometimes causes a failure, sometimes does not

130 April 29, 2001Essentials of Test: Agrawal & Bushnell130 March Test Notation n r -- Read a memory location n w -- Write a memory location n r0 -- Read a 0 from a memory location n r1 -- Read a 1 from a memory location n w0 -- Write a 0 to a memory location n w1 -- Write a 1 to a memory location n -- Write a 1 to a cell containing 0 n -- Write a 0 to a cell containing 1

131 April 29, 2001Essentials of Test: Agrawal & Bushnell131 March Test Notation (Continued) n -- Complement the cell contents n -- Increasing memory addressing n -- Decreasing memory addressing n -- Either increasing or decreasing

132 April 29, 2001Essentials of Test: Agrawal & Bushnell132 MATS+ March Test M0: { March element (w0) } for cell := 0 to n - 1 (or any other order) do write 0 to A [cell]; M1: { March element (r0, w1) } for cell := 0 to n - 1 do read A [cell]; { Expected value = 0} write 1 to A [cell]; M2: {March element (r1, w0) } for cell := n – 1 down to 0 do read A [cell]; { Expected value = 1 } write 0 to A [cell];

133 April 29, 2001Essentials of Test: Agrawal & Bushnell133 Reduced Functional Faults SAF TF CF NPSF Fault Stuck-at fault Transition fault Coupling fault Neighborhood Pattern Sensitive fault

134 April 29, 2001Essentials of Test: Agrawal & Bushnell134 Transition Faults n Cell fails to make 0 1 or 1 0 transition n Condition: Each cell must undergo a transition and a transition, and be read after such, before undergoing any further transitions. n, transition fault

135 April 29, 2001Essentials of Test: Agrawal & Bushnell135 Coupling Faults n Coupling Fault (CF): Transition in bit j causes unwanted change in bit i n 2-Coupling Fault: Involves 2 cells, special case of k-Coupling Fault  Must restrict k cells to make practical n Inversion and Idempotent CFs -- special cases of 2-Coupling Faults n Bridging and State Coupling Faults involve any # of cells, caused by logic level n Dynamic Coupling Fault (CFdyn) -- Read or write on j forces i to 0 or 1

136 April 29, 2001Essentials of Test: Agrawal & Bushnell136 Idempotent Coupling Faults (CFid) n or transition in j sets cell i to 0 or 1 n Condition: For all coupled faults, each should be read after a series of possible CFids may have happened, such that the sensitized CFids do not mask each other. n Asymmetric: coupled cell only does or n Symmetric: coupled cell does both due to fault n,,,

137 April 29, 2001Essentials of Test: Agrawal & Bushnell137 Bridging Faults n Short circuit between 2+ cells or lines n 0 or 1 state of coupling cell, rather than coupling cell transition, causes coupled cell change n Bidirectional fault -- i affects j, j affects i n AND Bridging Faults (ABF): ,,, n OR Bridging Faults (OBF): ,,,

138 April 29, 2001Essentials of Test: Agrawal & Bushnell138 Address Decoder Faults n Address decoding error assumptions:  Decoder does not become sequential  Same behavior during both read & write n Multiple ADFs must be tested for n Decoders have CMOS stuck-open faults

139 April 29, 2001Essentials of Test: Agrawal & Bushnell139 Fault Modeling Example 1 SCF SA0 SCF AF+SAF SAF SA0 TF

140 April 29, 2001Essentials of Test: Agrawal & Bushnell140 Fault Modeling Example 2 ABF SA0 ABF SA1 SA1+SCF SCF gg

141 April 29, 2001Essentials of Test: Agrawal & Bushnell141 Fault Hierarchy

142 April 29, 2001Essentials of Test: Agrawal & Bushnell142 Fault Frequency n Obtained with Scanning Electron Microscope n CFin and TF faults rarely occurred Cluster # Devices Fault class Stuck-at and Total failure Stuck-open Idempotent coupling State coupling ? Data retention ?

143 April 29, 2001Essentials of Test: Agrawal & Bushnell143 Functional RAM Testing with March Tests n March Tests can detect AFs -- NPSF Tests Cannot n Conditions for AF detection:  Need ( r x, w x) n In the following March tests, addressing orders can be interchanged

144 April 29, 2001Essentials of Test: Agrawal & Bushnell144 Irredundant March Test Summary Algorithm MATS MATS+ MATS++ MARCH X MARCH C— MARCH A MARCH Y MARCH B SAF All AF Some All TF All CF in All CF id All CF dyn All SCF All Linked Faults Some

145 April 29, 2001Essentials of Test: Agrawal & Bushnell145 MATS+ Example Cell (2, 1) SA1 Fault MATS+: { M0: (w0); M1: (r0, w1); M2: (r1, w0) }

146 April 29, 2001Essentials of Test: Agrawal & Bushnell146 Memory Testing Summary n Multiple fault models are essential n Combination of tests is essential:  March – SRAM and DRAM  NPSF -- DRAM  DC Parametric -- Both  AC Parametric -- Both n Inductive Fault Analysis is now required

147 April 29, 2001Essentials of Test: Agrawal & Bushnell147 Analog Test

148 April 29, 2001Essentials of Test: Agrawal & Bushnell148 Mixed-Signal Testing Problem

149 April 29, 2001Essentials of Test: Agrawal & Bushnell149 Differences from Digital Testing n Size not a problem – at most 100 components n Much harder analog device modeling  No widely-accepted analog fault model  Infinite signal range  Tolerances depend on process and measurement error  Tester (ATE) introduces measurement error  Digital / analog substrate coupling noise  Absolute component tolerances +/- 20%, relative +/- 0.1% n Multiple analog fault model mandatory  No unique signal flow direction

150 April 29, 2001Essentials of Test: Agrawal & Bushnell150 Present-Day Analog Testing Methods n Specification-based (functional) tests  Main method for analog – tractable and does not need an analog fault model  Intractable for digital -- # tests is huge n Structural ATPG – used for digital, just beginning to be used for analog (exists) n Separate test for functionality and timing not possible in analog circuit  Possible in digital circuit

151 April 29, 2001Essentials of Test: Agrawal & Bushnell151 Definitions n ADC – A/D converter n ATE – Automatic Test Equipment n DAC – D/A converter n DFT – Discrete Fourier Transform n DUT – Device-Under-Test n FFT – Fast Fourier Transform n Glitch Area -- area in DAC output of glitching pulses n Jitter – Low-level electrical noise – corrupts LSB’s, especially prevalent on converter clocking circuits n ks/s – Kilo-samples/sec

152 April 29, 2001Essentials of Test: Agrawal & Bushnell152 More Definitions n LSB -- Least Significant Bit (of converter) n Measurement – Result of measuring O/P analog parameter and quantifying it n Measurement Error – Introduced by measurement process n Non-Deterministic Device – All analog circuit measurements are not repeatable due to DUT or tester measurement noise n Phase-Locked-Loop – Clock circuit with feedback to keep desired signal phase n Settling Time -- Time for DAC reconstruction filter to settle n Test – Combination of analog stimulus, measurement of voltage or current, with a measurement error tolerance

153 April 29, 2001Essentials of Test: Agrawal & Bushnell153 DSP Tester Concept © 1987 IEEE

154 April 29, 2001Essentials of Test: Agrawal & Bushnell154 Waveform Synthesis © 1987 IEEE Needs sin x / x (sinc) correction – Finite sample width

155 April 29, 2001Essentials of Test: Agrawal & Bushnell155 Waveform Sampling © 1987 IEEE Sampling rate > 100 ks/s

156 April 29, 2001Essentials of Test: Agrawal & Bushnell156 ATE Clock Generator WS = waveform source WM = waveform measurement

157 April 29, 2001Essentials of Test: Agrawal & Bushnell157 A/D and D/A Test Parameters n A/D -- Uncertain map from input domain voltages into digital value (not so in D/A)  Two converters are NOT inverses n Transmission parameters affect multi-tone tests  Gain, signal-to-distortion ratio, intermodulation distortion, noise power ratio, differential phase shift, envelop delay distortion n Intrinsic parameters – Converter specifications  Full scale range (FSR), gain, # bits, static linearity (differential and integral), maximum clock rate, code format, settling time (D/A), glitch area (D/A)

158 April 29, 2001Essentials of Test: Agrawal & Bushnell158 Ideal Transfer Functions A/D ConverterD/A Converter

159 April 29, 2001Essentials of Test: Agrawal & Bushnell159 Offset Error

160 April 29, 2001Essentials of Test: Agrawal & Bushnell160 Gain Error

161 April 29, 2001Essentials of Test: Agrawal & Bushnell161 D/A Transfer Function Non-Linearity Error

162 April 29, 2001Essentials of Test: Agrawal & Bushnell162 Flash A/D Converter

163 April 29, 2001Essentials of Test: Agrawal & Bushnell163 Differential Linearity Error n Differential linearity function – How each code step differs from ideal or average step (by code number), as fraction of LSB n Subtract average count for each code tally, express that in units of LSBs n Repeat test waveform 100 to 150 times, use slow triangle wave to increase resolution

164 April 29, 2001Essentials of Test: Agrawal & Bushnell164 Linear Histogram and DLE of 8-bit ADC © 1987 IEEE

165 April 29, 2001Essentials of Test: Agrawal & Bushnell165 D/A Differential Test Fixture © 1987 IEEE Measure V y – V x difference, not absolute V x or V y

166 April 29, 2001Essentials of Test: Agrawal & Bushnell166 Summary n DSP-based tester has:  Waveform Generator  Waveform Digitizer  High frequency clock with dividers for synchronization n A/D and D/A Test Parameters  Transmission  Intrinsic n A/D and D/A Faults: offset, gain, non-linearity errors  Measured by DLE, ILE, DNL, and INL n A/D Test Histograms – static linear and sinusoidal n D/A Test –- Differential Test Fixture

167 April 29, 2001Essentials of Test: Agrawal & Bushnell167 DSP-Based Testing n Quantization Error – Introduced into measured signal by discrete sampling n Quantum Voltage – Corresponds to flip of LSB of converter n Single-Tone Test -- Test of DUT using only one sinusoidal tone Tone – Pure sinusoid of f, A, and phase  n Transmission (Performance) Parameter -- indicates how channel with embedded analog circuit affects multi-tone test signal  UTP – Unit test period: joint sampling period for analog stimulus and response

168 April 29, 2001Essentials of Test: Agrawal & Bushnell168 Coherent Measurement Method n Unit Test Period is integration interval P n Has integral # of stimulus periods M n Has integral # of DUT output periods N n Stimulus & sampling are phase locked n To obtain maximum information from sampling, M and N are relatively prime n F t – tone frequency n F s – sampling rate

169 April 29, 2001Essentials of Test: Agrawal & Bushnell169 CODEC Testing Example n Serial ADC in digital telephone exchange n Sampling rate 8000 s/s n Audio frequency range 300 – 3400 Hz F t = 1000 Hz F s = 8000 s/s P = 50 msec M = 50 cycles N = 400 samples n Problem: M and N not relatively prime n All samples fall on waveform at certain phases – sample only 8/255 CODEC steps

170 April 29, 2001Essentials of Test: Agrawal & Bushnell170 CODEC Testing Solution n Set F s = 400 ks/s – impossibly fast n Better – Adjust F t slightly, signal sampled at different points n Necessary relationships: F t = M x  F s = N x   = 1 / UTP F t M F s N =

171 April 29, 2001Essentials of Test: Agrawal & Bushnell171 Good CODEC Parameters F t = 1020 Hz F s = 8000 s/s P = UTP = 50 msec  = 20 Hz M = 51 cycles N = 400 samples n M and N now relatively prime n All samples fall on waveform at different phases – samples all CODEC steps

172 April 29, 2001Essentials of Test: Agrawal & Bushnell172 Unit Test Period © 1987 IEEE

173 April 29, 2001Essentials of Test: Agrawal & Bushnell173 Spectral Test of A/D Converter © 1987 IEEE

174 April 29, 2001Essentials of Test: Agrawal & Bushnell174 Bad A/D Converter Test © 1987 IEEE

175 April 29, 2001Essentials of Test: Agrawal & Bushnell175 Good A/D Converter Test © 1987 IEEE

176 April 29, 2001Essentials of Test: Agrawal & Bushnell176 Spectral DSP-Based Testing Components © 1987 IEEE

177 April 29, 2001Essentials of Test: Agrawal & Bushnell177 Correlation Model © 1987 IEEE  Cross-correlation – compare 2 different signals  Autocorrelation – compare 1 signal with itself

178 April 29, 2001Essentials of Test: Agrawal & Bushnell178 Fourier Voltmeter 1 st Principle © 1987 IEEE For signals A and B, if P is infinite, R = 0. If P is finite and contains integer # cycles of both A and B, then cross-correlation R = 0, regardless of phase or amplitude

179 April 29, 2001Essentials of Test: Agrawal & Bushnell179 Fourier Voltmeter 2 nd Principle © 1987 IEEE If signals A and B of same f are 90 o out of phase, and P contains an integer J # of signal cycles, then cross-correlation R = 0, regardless of amplitude or starting point

180 April 29, 2001Essentials of Test: Agrawal & Bushnell180 Conceptual Discrete Fourier Voltmeter © 1987 IEEE

181 April 29, 2001Essentials of Test: Agrawal & Bushnell181 A/D Converter Spectrum © 1987 IEEE Audio source at 1076 Hz sampled at 44.1 kHz

182 April 29, 2001Essentials of Test: Agrawal & Bushnell182 Coherent Multi-Tone Testing © 1987 IEEE

183 April 29, 2001Essentials of Test: Agrawal & Bushnell183 Single-Tone Test Example © 1987 IEEE

184 April 29, 2001Essentials of Test: Agrawal & Bushnell184 Multi-Tone Test Example © 1987 IEEE

185 April 29, 2001Essentials of Test: Agrawal & Bushnell185 Total Harmonic Distortion (THD) n Measures energy appearing in harmonics (H2, H3, …) of fundamental tone H1 as % of energy in the fundamental frequency in response spectrum n THD = … H 2 10 H 3 10 H H 1 20

186 April 29, 2001Essentials of Test: Agrawal & Bushnell186 DSP Testing Summary n Analog testing greatly increasing in importance  System-on-a-chip  Wireless  Personal computer multi-media  Automotive electronics  Medicine  Internet telephony  CD players and audio electronics n Analog testing NOT deterministic like digital  Statistical testing process, electrical noise

187 April 29, 2001Essentials of Test: Agrawal & Bushnell187 Delay Test

188 April 29, 2001Essentials of Test: Agrawal & Bushnell188 Delay Test Definition n A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing. n For a combinational or synchronous sequential circuit, delay test verifies the limits of delay in combinational logic. n Delay test problem for asynchronous circuits is complex and not well understood.

189 April 29, 2001Essentials of Test: Agrawal & Bushnell189 Digital Circuit Timing Inputs Outputs time Transient region Clock period Comb. logic Output Observation instant Input Signal changes Synchronized With clock

190 April 29, 2001Essentials of Test: Agrawal & Bushnell190 Circuit Delays n Switching or inertial delay is the interval between input change and output change of a gate: n Depends on input capacitance, device (transistor) characteristics and output capacitance of gate. n Also depends on input rise or fall times and states of other inputs (second-order effects). n Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output. n Propagation or interconnect delay is the time a transition takes to travel between gates: n Depends on transmission line effects (distributed R, L, C parameters, length and loading) of routing paths. n Approximation: modeled as lumped delays for gate inputs. n See Section for timing models.

191 April 29, 2001Essentials of Test: Agrawal & Bushnell191 Event Propagation Delays Path P1 P2 P3 Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew

192 April 29, 2001Essentials of Test: Agrawal & Bushnell192 Circuit Outputs n Each path can potentially produce one signal transition at the output. n The location of an output transition in time is determined by the delay of the path. Initial value Final value Clock period Fast transitions Slow transitions time

193 April 29, 2001Essentials of Test: Agrawal & Bushnell193 Robust Test n A robust test guarantees the detection of a delay fault of the target path, irrespective of delay faults on other paths. n A robust test is a combinational vector-pair, V1, V2, that satisfies following conditions: n Produce real events (different steady-state values for V1 and V2) on all on-path signals. n All on-path signals must have controlling events arriving via the target path. n A robust test is also a non-robust test. n Concept of robust test is general – robust tests for other fault models can be defined.

194 April 29, 2001Essentials of Test: Agrawal & Bushnell194 A Five-Valued Algebra n Signal States: S0, U0 (F0), S1, U1 (R1), XX. n On-path signals: F0 and R1. n Off-path signals: F0=U0 and R1=U1. S0 U0 S1 U1 XX S0 S0 S0 U0 S0 U0 U0 U0 U0 S1 S0 U0 S1 U1 XX U1 S0 U0 U1 U1 XX XX S0 U0 XX XX XX Input 1 Input 2 S0 U0 S1 U1 XX S0 S0 U0 S1 U1 XX U0 U0 U0 S1 U1 XX S1 S1 S1 U1 U1 U1 S1 U1 U1 XX XX XX S1 U1 XX Input 1 Input 2 Input S0 U0 S1 U1 XX S1 U1 S0 U0 XX AND OR NOT Ref.: Lin-Reddy IEEETCAD-87

195 April 29, 2001Essentials of Test: Agrawal & Bushnell195 Non-Robust Test Generation R1 U0 XX U1 U0 R1 Path P2 Fault P2 – rising transition through path P2 has no robust test. R1 XX A. Place R1 at path origin B. Propagate R1 through OR gate; interpreted as U1 on off-path signal; propagates as U0 through NOT gate D. R1 propagates through OR gate since off-path input is U0 C. Set input of AND gate to propagate R1 to output Non-robust test: U1, R1, U0 U1 Non-robust test requires Static sensitization: S0=U0, S1=U1

196 April 29, 2001Essentials of Test: Agrawal & Bushnell196 Path-Delay Faults (PDF) n Two PDFs (rising and falling transitions) for each physical path. n Total number of paths is an exponential function of gates. Critical paths, identified by static timing analysis (e.g., Primetime from Synopsys), must be tested. n PDF tests are delay-independent. Robust tests are preferred, but some paths have only non-robust tests. n Three types of PDFs (Gharaybeh, et al., JETTA (11), 1997): n Singly-testable PDF – has a non-robust or robust test. n Multiply-testable PDF – a set of singly untestable faults that has a non-robust or robust test. Also known as functionally testable PDF. n Untestable PDF – a PDF that is neither singly nor multiply testable. n A singly-testable PDF has at least one single-input change (SIC) non-robust test.

197 April 29, 2001Essentials of Test: Agrawal & Bushnell197 Other Delay Fault Models n Segment-delay fault -- A segment of an IO path is assumed to have large delay such that all paths containing the segment become faulty. n Transition fault -- A segment-delay fault with segment of unit length (single gate): n Two faults per gate; slow-to-rise and slow-to-fall. n Tests are similar to stuck-at fault tests. For example, a line is initialized to 0 and then tested for s-a-0 fault to detect slow-to-rise transition fault. n Models spot (or gross) delay defects. n Line-delay fault – A transition fault tested through the longest delay path. Two faults per line or gate. Tests are dependent on modeled delays of gates. n Gate-delay fault – A gate is assumed to have a delay increase of certain amount (called fault size) while all other gates retain some nominal delays. Gate-delay faults only of certain sizes may be detectable.

198 April 29, 2001Essentials of Test: Agrawal & Bushnell198 Slow-Clock Test Input test clock Output test clock Combinational circuit Input latches Output latches Input test clock Output test clock V1 applied V2 applied Output latched Test clock period Rated clock period

199 April 29, 2001Essentials of Test: Agrawal & Bushnell199 Enhanced-Scan Test Combinational circuit HL SFFHL SFF PI PO SCANIN SCAN- OUT HOLD CK TC CK: system clock TC: test control HOLD: hold signal SFF: scan flip-flop HL: hold latch CK HOLD CK period Normal mode Normal mode TC Scan mode V1 PI applied V2 PI applied Scanin V1 states Scanin V2 states V1 settles Result latched Scanout result

200 April 29, 2001Essentials of Test: Agrawal & Bushnell200 Normal-Scan Test Combinational circuit SFF PI PO SCANIN SCAN- OUT CK TC CK: system clock TC: test control SFF: scan flip-flop Rated CK period Normal mode TC (A) Scan mode V1 PIs applied V2 PIs applied Scanin V1 states Result latched Result scanout V2 states generated, (A) by one-bit scan shift of V1, or (B) by V1 applied in functional mode. Scan mode Normal mode TC (B) Scan mode Slow CK period t Gen. V2 states Path tested Slow clock

201 April 29, 2001Essentials of Test: Agrawal & Bushnell201 Variable-Clock Sequential Test T 1 PI PO T n-2 PI PO T n-1 PI PO T n+1 PI PO T n+m PI PO T n PI PO Initialization sequence (slow clock) Path activation (rated Clock) Fault effect propagation sequence (slow clock) D Off-path flip-flop Note: Slow-clock makes the circuit fault-free in the presence of delay faults.

202 April 29, 2001Essentials of Test: Agrawal & Bushnell202 Variable-Clock Example n ISCAS’89 benchmark s35932 (non-scan). n 2,124 vectors obtained by simulator- selection from random vectors (Parodi, et al., ITC-98). n PDF coverage, 26,228/394,282 ~ 6.7% n Longest tested PDF, 27 gates; longest path has 29 gates. n Test time ~ 4,511,376 clocks.

203 April 29, 2001Essentials of Test: Agrawal & Bushnell203 At-Speed Test n At-speed test means application of test vectors at the rated-clock speed. n Two methods of at-speed test. n External test: n Vectors may test one or more functional critical (longest delay) paths and a large percentage (~100%) of transition faults. n High-speed testers are expensive. n Built-in self-test (BIST): n Hardware-generated random vectors applied to combinational or sequential logic. n Only clock is externally supplied. n Non-functional paths that are longer than the functional critical path can be activated and cause a good circuit to fail. n Some circuits have initialization problem.

204 April 29, 2001Essentials of Test: Agrawal & Bushnell204 Timing Design & Delay Test n Timing simulation: n Critical paths are identified by static (vector-less) timing analysis tools like Primetime (Synopsys). n Timing or circuit-level simulation using designer- generated functional vectors verifies the design. n Layout optimization: Critical path data are used in placement and routing. Delay parameter extraction, timing simulation and layout are repeated for iterative improvement. n Testing: Some form of at-speed test is necessary. PDFs for critical paths and all transition faults are tested.

205 April 29, 2001Essentials of Test: Agrawal & Bushnell205 Summary n Path-delay fault (PDF) models distributed delay defects. It verifies the timing performance of a manufactured circuit. n Transition fault models spot delay defects and is testable by modified stuck-at fault tests. n Variable-clock method can test delay faults but the test time can be long. n Critical paths of non-scan sequential circuits can be effectively tested by rated-clock tests. n Delay test methods (including BIST) for non-scan sequential circuits using slow ATE require investigation: n Suppression of non-functional path activation in BIST. n Difficulty of rated-clock PDF test generation. n Long sequences of variable-clock tests.

206 April 29, 2001Essentials of Test: Agrawal & Bushnell206 I DDQ Test

207 April 29, 2001Essentials of Test: Agrawal & Bushnell207 Basic Principle of I DDQ Testing  Measure I DDQ current through V ss bus

208 April 29, 2001Essentials of Test: Agrawal & Bushnell208 Stuck-at Faults Detected by I DDQ Tests n Bridging faults with stuck-at fault behavior  Levi – Bridging of a logic node to V DD or V SS – few of these  Transistor gate oxide short of 1 K  to 5 K  n Floating MOSFET gate defects – do not fully turn off transistor

209 April 29, 2001Essentials of Test: Agrawal & Bushnell209 Capacitive Coupling of Floating Gates n C pb – capacitance from poly to bulk n C mp – overlapped metal wire to poly n Floating gate voltage depends on capacitances and node voltages n If nFET and pFET get enough gate voltage to turn them on, then I DDQ test detects this defect n K is the transistor gain

210 April 29, 2001Essentials of Test: Agrawal & Bushnell210 Bridging Faults S 1 – S 5 Caused by absolute short (< 50  ) or higher R n Segura et al. evaluated testing of bridges with 3 CMOS inverter chain I DDQRb tests fault when R b > 50 K  or 0 R b 100 K  n Largest deviation when V in = 5 V bridged nodes at opposite logic values  

211 April 29, 2001Essentials of Test: Agrawal & Bushnell211 Delay Faults n Most random CMOS defects cause a timing delay fault, not catastrophic failure n Many delay faults detected by I DDQ test – late switching of logic gates keeps I DDQ elevated n Delay faults not detected by I DDQ test  Resistive via fault in interconnect  Increased transistor threshold voltage fault

212 April 29, 2001Essentials of Test: Agrawal & Bushnell212 Leakage Faults n Gate oxide shorts cause leaks between gate & source or gate & drain n Mao and Gulati leakage fault model:  Leakage path flags: f GS, f GD, f SD, f BS, f BD, f BG G = gate, S = source, D = drain, B = bulk n Assume that short does not change logic values

213 April 29, 2001Essentials of Test: Agrawal & Bushnell213 Weak Faults n nFET passes logic 1 as 5 V – V tn n pFET passes logic 0 as 0 V + |V tp | n Weak fault – one device in C-switch does not turn on  Causes logic value degradation in C-switch

214 April 29, 2001Essentials of Test: Agrawal & Bushnell214 Gate Oxide Short

215 April 29, 2001Essentials of Test: Agrawal & Bushnell215 Fault Coverage Metrics n Conductance fault model (Malaiya & Su)  Monitor I DDQ to detect all leakage faults  Proved that stuck fault test set can be used to generate minimum leakage fault test set n Short fault coverage  Handles intra-gate bridges, but may not handle inter-gate bridges n Pseudo-stuck-at fault coverage  Voltage stuck-at fault coverage that represents internal transistor short fault coverage and hard stuck-at fault coverage

216 April 29, 2001Essentials of Test: Agrawal & Bushnell216 Quietest Results Ckt. 1 2 # of Tran- Sistors # of Leakage Faults % Selected Vectors 0.5 % 0.99 % Leakage Fault Coverage % % # of Weak Faults % Selected Vectors 0.35 % 0.21 % Weak Fault Coverage 85.3 % % Ckt. 1 2

217 April 29, 2001Essentials of Test: Agrawal & Bushnell217 Sematech Results n Test process: Wafer Test Package Test Burn-In & Retest Characterize & Failure Analysis n Data for devices failing some, but not all, tests. pass fail pass pass fail pass fail fail pass fail pass fail Scan-based Stuck-at IDDQ (5  A limit) Functional Scan-based delay

218 April 29, 2001Essentials of Test: Agrawal & Bushnell218 Summary n I DDQ tests improve reliability, find defects causing:  Delay, bridging, weak faults  Chips damaged by electro-static discharge n No natural breakpoint for current threshold  Get continuous distribution – bimodal would be better n Conclusion: now need stuck-fault, I DDQ, and delay fault testing combined n Still uncertain whether I DDQ tests will remain useful as chip feature sizes shrink further

219 April 29, 2001Essentials of Test: Agrawal & Bushnell219 Part III DESIGN FOR TESTABILITY Scan Design

220 April 29, 2001Essentials of Test: Agrawal & Bushnell220 Definition n Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. n DFT methods for digital circuits:  Ad-hoc methods  Structured methods: n Scan n Partial Scan n Built-in self-test (BIST) n Boundary scan n DFT method for mixed-signal circuits: n Analog test bus

221 April 29, 2001Essentials of Test: Agrawal & Bushnell221 Ad-Hoc DFT Methods n Good design practices learnt through experience are used as guidelines: n Avoid asynchronous (unclocked) feedback. n Make flip-flops initializable. n Avoid redundant gates. Avoid large fanin gates. n Provide test control for difficult-to-control signals. n Avoid gated clocks. n... n Consider ATE requirements (tristates, etc.) n Design reviews conducted by experts or design auditing tools. n Disadvantages of ad-hoc DFT methods: n Experts and tools not always available. n Test generation is often manual with no guarantee of high fault coverage. n Design iterations may be necessary.

222 April 29, 2001Essentials of Test: Agrawal & Bushnell222 Scan Design  Circuit is designed using pre-specified design rules.  Test structure (hardware) is added to the verified design: n Add a test control (TC) primary input. n Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. n Make input/output of each scan shift register controllable/observable from PI/PO.  Use combinational ATPG to obtain tests for all testable faults in the combinational logic.  Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test.

223 April 29, 2001Essentials of Test: Agrawal & Bushnell223 Scan Design Rules n Use only clocked D-type of flip-flops for all state variables. n At least one PI pin must be available for test; more pins, if available, can be used. n All clocks must be controlled from PIs. n Clocks must not feed data inputs of flip-flops.

224 April 29, 2001Essentials of Test: Agrawal & Bushnell224 Correcting a Rule Violation n All clocks must be controlled from PIs. Comb. logic Comb. logic D1 D2 CK Q FF Comb. logic D1 D2 CK Q FF Comb. logic

225 April 29, 2001Essentials of Test: Agrawal & Bushnell225 Scan Flip-Flop (SFF) D TC SD CK Q Q MUX D flip-flop Master latchSlave latch CK TC Normal mode, D selectedScan mode, SD selected Master open Slave open t t Logic overhead

226 April 29, 2001Essentials of Test: Agrawal & Bushnell226 Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF) D SD MCK Q Q D flip-flop Master latchSlave latch t SCK TCK SCK MCK TCK Normal mode MCK TCK Scan mode Logic overhead

227 April 29, 2001Essentials of Test: Agrawal & Bushnell227 Adding Scan Structure SFF Combinational logic PI PO SCANOUT SCANIN TC or TCK Not shown: CK or MCK/SCK feed all SFFs.

228 April 29, 2001Essentials of Test: Agrawal & Bushnell228 Comb. Test Vectors I2 I1 O1 O2 S2 S1 N2 N1 Combinational logic PI Presen t state PO Next state SCANIN TC SCANOUT

229 April 29, 2001Essentials of Test: Agrawal & Bushnell229 Comb. Test Vectors I2 I1 O1 O2 PI PO SCANIN SCANOUT S1 S2 N1 N TC Don’t care or random bits Sequence length = (n comb + 1) n sff + n comb clock periods n comb = number of combinational vectors n sff = number of scan flip-flops

230 April 29, 2001Essentials of Test: Agrawal & Bushnell230 Testing Scan Register n Scan register must be tested prior to application of scan test sequences. n A shift sequence of length n sff +4 in scan mode (TC=0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output. n Total scan test length: (n comb + 2) n sff + n comb + 4 clock periods. n Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 10 6 clocks. n Multiple scan registers reduce test length.

231 April 29, 2001Essentials of Test: Agrawal & Bushnell231 Scan Overheads n IO pins: One pin necessary. n Area overhead:  Gate overhead = [4 n sff /(n g +10n ff )] x 100%, where n g = comb. gates; n ff = flip-flops; Example – n g = 100k gates, n ff = 2k flip-flops, overhead = 6.7%.  More accurate estimate must consider scan wiring and layout area. n Performance overhead:  Multiplexer delay added in combinational path; approx. two gate-delays.  Flip-flop output loading due to one additional fanout; approx. 5-6%.

232 April 29, 2001Essentials of Test: Agrawal & Bushnell232 ATPG Example: S5378 Original 2, % 4,603 35/ % 70.9% 5,533 s 414 Full-scan 2, % 4, / % 100.0% 5 s ,662 Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency CPU time on SUN Ultra II, 200MHz processor Number of ATPG vectors Scan sequence length

233 April 29, 2001Essentials of Test: Agrawal & Bushnell233 Automated Scan Design Behavior, RTL, and logic Design and verification Gate-level netlist Scan design rule audits Combinational ATPG Scan hardware insertion Chip layout: Scan- chain optimization, timing verification Scan sequence and test program generation Design and test data for manufacturing Rule violations Scan netlist Combinational vectors Scan chain order Mask data Test program

234 April 29, 2001Essentials of Test: Agrawal & Bushnell234 Summary n Scan is the most popular DFT technique: n Rule-based design n Automated DFT hardware insertion n Combinational ATPG n Advantages: n Design automation n High fault coverage; helpful in diagnosis n Hierarchical – scan-testable modules are easily combined into large scan-testable systems n Moderate area (~10%) and speed (~5%) overheads n Disadvantages: n Large test data volume and long test time n Basically a slow speed (DC) test

235 April 29, 2001Essentials of Test: Agrawal & Bushnell235 Built-In Self-Testing (BIST)

236 April 29, 2001Essentials of Test: Agrawal & Bushnell236 Economics – BIST Costs  Chip area overhead for: n Test controller n Hardware pattern generator n Hardware response compacter n Testing of BIST hardware  Pin overhead -- At least 1 pin needed to activate BIST operation  Performance overhead – extra path delays due to BIST  Yield loss – due to increased chip area or more chips In system because of BIST  Reliability reduction – due to increased area  Increased BIST hardware complexity – happens when BIST hardware is made testable

237 April 29, 2001Essentials of Test: Agrawal & Bushnell237 BIST Benefits n Faults tested:  Single combinational / sequential stuck-at faults  Delay faults  Single stuck-at faults in BIST hardware n BIST benefits  Reduced testing and maintenance cost  Lower test generation cost  Reduced storage / maintenance of test patterns  Simpler and less expensive ATE  Can test many units in parallel  Shorter test application times  Can test at functional system speed

238 April 29, 2001Essentials of Test: Agrawal & Bushnell238 BIST Process n Test controller – Hardware that activates self- test simultaneously on all PCBs n Each board controller activates parallel chip BIST Diagnosis effective only if very high fault coverage

239 April 29, 2001Essentials of Test: Agrawal & Bushnell239 BIST Architecture n Note: BIST cannot test wires and transistors:  From PI pins to Input MUX  From POs to output pins

240 April 29, 2001Essentials of Test: Agrawal & Bushnell240 Example External XOR LFSR n Characteristic polynomial f (x) = 1 + x + x 3 (read taps from right to left)

241 April 29, 2001Essentials of Test: Agrawal & Bushnell241 External XOR LFSR n Pattern sequence for example LFSR (earlier): n Always have 1 and x n terms in polynomial n Never repeat an LFSR pattern more than 1 time – Repeats same error vector, cancels fault effect X0 (t + 1) X1 (t + 1) X2 (t + 1) X0 (t) X1 (t) X2 (t) = X0X1X2X0X1X …

242 April 29, 2001Essentials of Test: Agrawal & Bushnell242 Response Compaction n Severe amounts of data in CUT response to LFSR patterns – example:  Generate 5 million random patterns  CUT has 200 outputs  Leads to: 5 million x 200 = 1 billion bits response n Uneconomical to store and check all of these responses on chip n Responses must be compacted

243 April 29, 2001Essentials of Test: Agrawal & Bushnell243 Definitions n Aliasing – Due to information loss, signatures of good and some bad machines match n Compaction – Drastically reduce # bits in original circuit response – lose information n Compression – Reduce # bits in original circuit response – no information loss – fully invertible (can get back original response) n Signature analysis – Compact good machine response into good machine signature. Actual signature generated during testing, and compared with good machine signature n Transition Count Response Compaction – Count # transitions from 0 1 and 1 0 as a signature

244 April 29, 2001Essentials of Test: Agrawal & Bushnell244 LFSR for Response Compaction n Use cyclic redundancy check code (CRCC) generator (LFSR) for response compacter n Treat data bits from circuit POs to be compacted as a decreasing order coefficient polynomial n CRCC divides the PO polynomial by its characteristic polynomial  Leaves remainder of division in LFSR  Must initialize LFSR to seed value (usually 0) before testing n After testing – compare signature in LFSR to known good machine signature n Critical: Must compute good machine signature

245 April 29, 2001Essentials of Test: Agrawal & Bushnell245 Example Modular LFSR Response Compacter n LFSR seed value is “00000”

246 April 29, 2001Essentials of Test: Agrawal & Bushnell246 Polynomial Division Logic simulation: Remainder = 1 + x 2 + x x x x x x x x x 7 Inputs Initial State X X X X X X X X X X Logic Simulation:

247 April 29, 2001Essentials of Test: Agrawal & Bushnell247 Symbolic Polynomial Division x2x7x7x2x7x x 5 x 5 + x 3 x 3 + x 2 + x + 1 x 5 + x 3 + x + 1 remainder Remainder matches that from logic simulation of the response compacter!

248 April 29, 2001Essentials of Test: Agrawal & Bushnell248 Multiple-Input Signature Register (MISR) n Problem with ordinary LFSR response compacter:  Too much hardware if one of these is put on each primary output (PO) n Solution: MISR – compacts all outputs into one LFSR  Works because LFSR is linear – obeys superposition principle  Superimpose all responses in one LFSR – final remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial

249 April 29, 2001Essentials of Test: Agrawal & Bushnell249 Modular MISR Example X 0 (t + 1) X 1 (t + 1) X 2 (t + 1) = X 0 (t) X 1 (t) X 2 (t) d 0 (t) d 1 (t) d 2 (t) +

250 April 29, 2001Essentials of Test: Agrawal & Bushnell250 Aliasing Theorems n Theorem 15.1: Assuming that each circuit PO d ij has probability p of being in error, and that all outputs d ij are independent, in a k-bit MISR, P al = 1/(2 k ), regardless of initial condition of MISR. Not exactly true – true in practice. n Theorem 15.2: Assuming that each PO d ij has probability p j of being in error, where the p j probabilities are independent, and that all outputs d ij are independent, in a k-bit MISR, P al = 1/(2 k ), regardless of the initial condition.

251 April 29, 2001Essentials of Test: Agrawal & Bushnell251 Built-in Logic Block Observer (BILBO) n Combined functionality of D flip-flop, pattern generator, response compacter, & scan chain  Reset all FFs to 0 by scanning in zeros

252 April 29, 2001Essentials of Test: Agrawal & Bushnell252 Example BILBO Usage n SI – Scan In n SO – Scan Out n Characteristic polynomial: 1 + x + … + x n n CUTs A and C: BILBO1 is MISR, BILBO2 is LFSR n CUT B: BILBO1 is LFSR, BILBO2 is MISR

253 April 29, 2001Essentials of Test: Agrawal & Bushnell253 Circuit Initialization n Full-scan BIST – shift in scan chain seed before starting BIST n Partial-scan BIST – critical to initialize all FFs before BIST starts  Otherwise we clock X’s into MISR and signature is not unique and not repeatable n Discover initialization problems by: 1. Modeling all BIST hardware 2. Setting all FFs to X’s 3. Running logic simulation of CUT with BIST hardware

254 April 29, 2001Essentials of Test: Agrawal & Bushnell254 Circuit Initialization (continued) n If MISR finishes with BIST cycle with X’s in signature, Design-for-Testability initialization hardware must be added n Add MS (master set) or MR (master reset) lines on flip-flops and excite them before BIST starts n Otherwise: 1. Break all cycles of FF’s 2. Apply a partial BIST synchronizing sequence to initialize all FF’s 3. Turn on the MISR to compact the response

255 April 29, 2001Essentials of Test: Agrawal & Bushnell255 Test Point Insertion n BIST does not detect all faults:  Test patterns not rich enough to test all faults n Modify circuit after synthesis to improve signal controllability n Observability addition – Route internal signal to extra FF in MISR or XOR into existing FF in MISR

256 April 29, 2001Essentials of Test: Agrawal & Bushnell256 SRAM BIST with MISR n Use MISR to compress memory outputs n Control aliasing by repeating test:  With different MISR feedback polynomial  With RAM test patterns in reverse order n March test: { (w Address); (r Address); (w Address); (r Address); (r Address); (w Address); (r Address); (r Address) } n Not proven to detect coupling or address decoder faults

257 April 29, 2001Essentials of Test: Agrawal & Bushnell257 BIST System with MISR

258 April 29, 2001Essentials of Test: Agrawal & Bushnell258 Summary n LFSR pattern generator and MISR response compacter – preferred BIST methods n BIST has overheads: test controller, extra circuit delay, Input MUX, pattern generator, response compacter, DFT to initialize circuit & test the test hardware n BIST benefits:  At-speed testing for delay & stuck-at faults  Drastic ATE cost reduction  Field test capability  Faster diagnosis during system test  Less effort to design testing process  Shorter test application times

259 April 29, 2001Essentials of Test: Agrawal & Bushnell259 IEEE Boundary Scan Standard

260 April 29, 2001Essentials of Test: Agrawal & Bushnell260 Motivation for Standard n Bed-of-nails printed circuit board tester gone  We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance n Nails would hit components  Reduced spacing between PCB wires n Nails would short the wires  PCB Tester must be replaced with built-in test delivery system -- JTAG does that  Need standard System Test Port and Bus  Integrate components from different vendors n Test bus identical for various components n One chip has test hardware for other chips

261 April 29, 2001Essentials of Test: Agrawal & Bushnell261 Purpose of Standard n Lets test instructions and test data be serially fed into a component-under-test (CUT)  Allows reading out of test results  Allows RUNBIST command as an instruction n Too many shifts to shift in external tests n JTAG can operate at chip, PCB, & system levels n Allows control of tri-state signals during testing n Lets other chips collect responses from CUT n Lets system interconnect be tested separately from components n Lets components be tested separately from wires

262 April 29, 2001Essentials of Test: Agrawal & Bushnell262 System Test Logic

263 April 29, 2001Essentials of Test: Agrawal & Bushnell263 Instruction Register Loading with JTAG

264 April 29, 2001Essentials of Test: Agrawal & Bushnell264 System View of Interconnect

265 April 29, 2001Essentials of Test: Agrawal & Bushnell265 Boundary Scan Chain View

266 April 29, 2001Essentials of Test: Agrawal & Bushnell266 Elementary Boundary Scan Cell

267 April 29, 2001Essentials of Test: Agrawal & Bushnell267 Serial Board / MCM Scan

268 April 29, 2001Essentials of Test: Agrawal & Bushnell268 Parallel Board / MCM Scan

269 April 29, 2001Essentials of Test: Agrawal & Bushnell269 Tap Controller Signals n Test Access Port (TAP) includes these signals:  Test Clock Input (TCK) -- Clock for test logic n Can run at different rate from system clock  Test Mode Select (TMS) -- Switches system from functional to test mode  Test Data Input (TDI) -- Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions  Test Data Output (TDO) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers)  Test Reset (TRST) -- Optional asynchronous TAP controller reset

270 April 29, 2001Essentials of Test: Agrawal & Bushnell270 SAMPLE / PRELOAD Instruction -- SAMPLE Purpose: 1. Get snapshot of normal chip output signals 2. Put data on bound. scan chain before next instr.

271 April 29, 2001Essentials of Test: Agrawal & Bushnell271 SAMPLE / PRELOAD Instruction -- PRELOAD

272 April 29, 2001Essentials of Test: Agrawal & Bushnell272 EXTEST Instruction n Purpose: Test off-chip circuits and board- level interconnections

273 April 29, 2001Essentials of Test: Agrawal & Bushnell273 INTEST Instruction n Purpose: 1. Shifts external test patterns onto component 2. External tester shifts component responses out

274 April 29, 2001Essentials of Test: Agrawal & Bushnell274 RUNBIST Instruction n Purpose: Allows you to issue BIST command to component through JTAG hardware n Optional instruction n Lets test logic control state of output pins 1. Can be determined by pin boundary scan cell 2. Can be forced into high impedance state n BIST result (success or failure) can be left in boundary scan cell or internal cell  Shift out through boundary scan chain n May leave chip pins in an indeterminate state (reset required before normal operation resumes)

275 April 29, 2001Essentials of Test: Agrawal & Bushnell275 CLAMP Instruction n Purpose: Forces component output signals to be driven by boundary-scan register n Bypasses the boundary scan chain by using the one-bit Bypass Register n Optional instruction n May have to add RESET hardware to control on-chip logic so that it does not get damaged (by shorting 0’s and 1’s onto an internal bus, etc.)

276 April 29, 2001Essentials of Test: Agrawal & Bushnell276 IDCODE Instruction n Purpose: Connects the component device identification register serially between TDI and TDO  In the Shift-DR TAP controller state n Allows board-level test controller or external tester to read out component ID n Required whenever a JEDEC identification register is included in the design

277 April 29, 2001Essentials of Test: Agrawal & Bushnell277 Device ID Register -- JEDEC Code Part Number (16 bits) 11 1 Manufacturer Identity (11 bits) 0 ‘1’ (1 bit) Version (4 bits) MSBLSB

278 April 29, 2001Essentials of Test: Agrawal & Bushnell278 USERCODE Instruction n Purpose: Intended for user-programmable components (FPGA’s, EEPROMs, etc.)  Allows external tester to determine user programming of component n Selects the device identification register as serially connected between TDI and TDO n User-programmable ID code loaded into device identification register  On rising TCK edge n Switches component test hardware to its system function n Required when Device ID register included on user-programmable component

279 April 29, 2001Essentials of Test: Agrawal & Bushnell279 HIGHZ Instruction n Purpose: Puts all component output pin signals into high-impedance state n Control chip logic to avoid damage in this mode n May have to reset component after HIGHZ runs n Optional instruction

280 April 29, 2001Essentials of Test: Agrawal & Bushnell280 BYPASS Instruction n Purpose: Bypasses scan chain with 1-bit register

281 April 29, 2001Essentials of Test: Agrawal & Bushnell281 Summary n Boundary Scan Standard has become absolutely essential --  No longer possible to test printed circuit boards with bed-of-nails tester  Not possible to test multi-chip modules at all without it  Supports BIST, external testing with Automatic Test Equipment, and boundary scan chain reconfiguration as BIST pattern generator and response compacter  Now getting widespread usage

282 April 29, 2001Essentials of Test: Agrawal & Bushnell282 IEEE Analog Test Bus

283 April 29, 2001Essentials of Test: Agrawal & Bushnell283 Analog Test Bus n PROs:  Usable with digital JTAG boundary scan  Adds analog testability – both controllability and observability  Eliminates large area needed for analog test points n CONs:  May have a 5 % measurement error  C-switch sampling devices couple all probe points capacitively, even with test bus off – requires more elaborate (larger) switches  Stringent limit on how far data can move through the bus before it must be digitized to retain accuracy

284 April 29, 2001Essentials of Test: Agrawal & Bushnell284 Analog Test Bus Diagram

285 April 29, 2001Essentials of Test: Agrawal & Bushnell285 Analog Boundary Module

286 April 29, 2001Essentials of Test: Agrawal & Bushnell286 Chaining of ICs

287 April 29, 2001Essentials of Test: Agrawal & Bushnell287 System Test

288 April 29, 2001Essentials of Test: Agrawal & Bushnell288 A System and Its Testing n A system is an organization of components (hardware/software parts and subsystems) with capability to perform useful functions. n Functional test verifies integrity of system: n Checks for presence and sanity of subsystems n Checks for system specifications n Executes selected (critical) functions n Diagnostic test isolates faulty part: n For field maintenance isolates lowest replaceable unit (LRU), e.g., a board, disc drive, or I/O subsystem n For shop repair isolates shop replaceable unit (SRU), e.g., a faulty chip on a board n Diagnostic resolution is the number of suspected faulty units identified by test; fewer suspects mean higher resolution

289 April 29, 2001Essentials of Test: Agrawal & Bushnell289 Functional Test n All or selected (critical) operations executed with non-exhaustive data. n Tests are a subset of design verification tests (test-benches). n Software test metrics used: statement, branch and path coverages; provide low (~70%) structural hardware fault coverage. n Examples: n Microprocessor test – all instructions with random data (David, 1998). n Instruction-set fault model – wrong instruction is executed (Thatte and Abraham, IEEETC-1980).

290 April 29, 2001Essentials of Test: Agrawal & Bushnell290 Gate-Level Diagnosis e d a b c T3 T1 T2 T4 a b c Stuck-at fault tests: T1 = 010 T2 = 011 T3 = 100 T4 = 110 Logic circuit Karnaugh map (shaded squares are true outputs)

291 April 29, 2001Essentials of Test: Agrawal & Bushnell291 Gate Replacement Fault e d a b c T3 T1 T2 T4 a b c Stuck-at fault tests: T1 = 010 (pass) T2 = 011 (fail) T3 = 100 (pass) T4 = 110 (fail) Faulty circuit (OR replaced by AND) Karnaugh map (faulty output shown in red)

292 April 29, 2001Essentials of Test: Agrawal & Bushnell292 Fault Test syndrome t 1 t 2 t 3 t 4 No fault a 0, b 0, d 0 a 1 b 1 c 0 c 1, d 1, e 1 e 0 Fault Dictionary a 0 : Line a stuck- at-0 t i = 0, if Ti passes = 1, if Ti fails

293 April 29, 2001Essentials of Test: Agrawal & Bushnell293 Diagnosis with Dictionary Fault Test syndrome Diagnosis t 1 t 2 t 3 t 4 OR AND e 0 OR-bridge (a,c) b 1 OR NOR c 1, d 1, e 1, e 0 Dictionary look-up with minimum Hamming distance

294 April 29, 2001Essentials of Test: Agrawal & Bushnell294 Diagnostic Tree T4 T1 T2 T3 No fault found T3 T2 b1b1 a1a1 c 1, d 1, e 1 a 0, b 0, d 0 e0e0 c0c0 Pass: t 4 =0 Fail: t 4 =1 a 0, b 0, d 0, e 0 a 1, c 1, d 1, e 1 OR AND OR bridge (a,c) OR NOR

295 April 29, 2001Essentials of Test: Agrawal & Bushnell295 System Test: A DFT Problem n Given the changing scenario in VLSI:  Mixed-signal circuits  System-on-a-chip  Multi-chip modules  Intellectual property (IP) cores n Prepare the engineer for designing testable, i.e., manufacturable, VLSI systems.

296 April 29, 2001Essentials of Test: Agrawal & Bushnell296 Partitioning for Test n Partition according to test methodology:  Logic blocks  Memory blocks  Analog blocks n Provide test access:  Boundary scan  Analog test bus n Provide test-wrappers (also called collars) for cores.

297 April 29, 2001Essentials of Test: Agrawal & Bushnell297 Test-Wrapper for a Core n Test-wrapper (or collar) is the logic added around a core to provide test access to the embedded core. n Test-wrapper provides:  For each core input terminal n A normal mode – Core terminal driven by host chip n An external test mode – Wrapper element observes core input terminal for interconnect test n An internal test mode – Wrapper element controls state of core input terminal for testing the logic inside core  For each core output terminal n A normal mode – Host chip driven by core terminal n An external test mode – Host chip is driven by wrapper element for interconnect test n An internal test mode – Wrapper element observes core outputs for core test

298 April 29, 2001Essentials of Test: Agrawal & Bushnell298 A Test-Wrapper Wrapper test controlle r Scan chain to/from TAP from/to External Test pins Wrapper elements Core Functional core inputs Functional core outputs

299 April 29, 2001Essentials of Test: Agrawal & Bushnell299 Overhead Estimate Rent’s rule: For a logic block the number of gates G and the number of terminals t are related by t = K G  where 1 < K < 5, and  ~ 0.5. Assume that block area A is proportional to G, i.e., t is proportional to A 0.5. Since test logic is added to each terminal t, Test logic added to terminals Overhead = ~ A –0.5 A

300 April 29, 2001Essentials of Test: Agrawal & Bushnell300 DFT Architecture for SOC User defined test access mechanism (TAM) Module 1 Test wrapper Test source Test sink Module N Test wrapper Test access port (TAP) Functional inputs Functional outputs Func. inputs Func. outputs SOC inputs SOC outputs TDI TCK TMS TRST TDO Instruction register control Serial instruction data

301 April 29, 2001Essentials of Test: Agrawal & Bushnell301 DFT Components n Test source: Provides test vectors via on-chip LFSR, counter, ROM, or off-chip ATE. n Test sink: Provides output verification using on-chip signature analyzer, or off-chip ATE. n Test access mechanism (TAM): User-defined test data communication structure; carries test signals from source to module, and module to sink; tests module interconnects via test-wrappers; TAM may contain bus, boundary-scan and analog test bus components. n Test controller: Boundary-scan test access port (TAP); receives control signals from outside; serially loads test instructions in test-wrappers.

302 April 29, 2001Essentials of Test: Agrawal & Bushnell302 Summary n Functional test: verify system hardware, software, function and performance; pass/fail test with limited diagnosis; high (~100%) software coverage metrics; low (~70%) structural fault coverage. n Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree. n SOC design for testability: n Partition SOC into blocks of logic, memory and analog circuitry, often on architectural boundaries. n Provide external or built-in tests for blocks. n Provide test access via boundary scan and/or analog test bus. n Develop interconnect tests and system functional tests. n Develop diagnostic procedures.


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