We think you have liked this presentation. If you wish to download it, please recommend it to your friends in any social system. Share buttons are a little bit lower. Thank you!
Presentation is loading. Please wait.
Published byLorenzo Bache
Modified about 1 year ago
Using Virtual Platforms for Firmware Verification James Pangburn Jason Andrews
2 © 2013 Cadence Design Systems, Inc. All rights reserved. About the Authors James Pangburn −(Cadence, −Firmware Architect at Cadence, 30 years experience in hardware and software development, embedded systems, EDA tools Jason Andrews −(Cadence, −Senior Architect at Cadence, responsible for embedded software and hardware/software co- verification products and methodology
3 © 2013 Cadence Design Systems, Inc. All rights reserved. Abstract Design IP like DDR, PCIe, and Ethernet controllers and their PHYs offer significant configurability (to optimize for the customer’s needs). To reduce a customer’s integration time, providers of configurable IP find it essential to generate companion drivers for the IP. Generation of configurable IP is well understood today, but generation, and especially verification, of the companion drivers is a relatively new challenge. This paper illustrates a hybrid virtual system methodology for verifying firmware drivers in synchronization with the IP.
4 © 2013 Cadence Design Systems, Inc. All rights reserved. Agenda Problem Statement Solution: Virtual Platforms –How to build them –How they help firmware verification Tested Examples Conclusion
5 © 2013 Cadence Design Systems, Inc. All rights reserved. The SoC Developer’s Challenge Multiple, complex interfaces Need to optimize hardware + firmware for application Hardware Area and Power Firmware Footprint Both Performance and Quality Customer’s Application-Specific Components SoC Interconnect Fabric CPU Subsystem 3D Graphics Core Modem High-speed, Wired Interface Peripherals DDR 3 PHY Other Peripherals SATA MIPI HDMI WLAN LTE Low-speed peripheral subsystem Low-speed Peripherals PMU MIPI JTAG INTC I2C SPI Timer GPIO Displa y UAR T Application Accelerators … … AES … … C1 L2 cache USB P H Y 3. 0 P H Y 2. 0 P H Y 2. 0 P H Y PCIe Gen 2,3 PCIe Gen 2,3 PHY Ethernet PHY C2 C3 L2 cache C4 Cache Coherent Fabric
6 © 2013 Cadence Design Systems, Inc. All rights reserved. The IP Developer’s Challenge To optimize for a customer, IP is configurable Therefore, companion firmware must be configurable Master Source (RTL, C, tests, docs, etc.) Customer C Delivery TLM Router CPU Other Peripherals Modem INTC Timer UART Other JTAG GPIO A15 A7 L2 cache A7 Cache Coherent Fabric Customer Configurations Customer B Delivery Other Peripherals Modem INTC Timer UART Other JTAG GPIO A15 A7 L2 cache A7 Cache Coherent Fabric Customer A Delivery IP Package –The IP Factory fabricates optimized IP and firmware packages for each customer configuration o Fully verified in factory –Each customer receives: o Technology content o Documentation o Integration kit o All are best-fit for customer’s needs IP Factory
7 © 2013 Cadence Design Systems, Inc. All rights reserved. The Problem at Hand How to verify that the generated firmware is correct? −Drives the selected configuration of the IP −Causes the IP to perform the functions as understood by the firmware developers Catch errors, misunderstandings, etc. early
8 © 2013 Cadence Design Systems, Inc. All rights reserved. The Solution: Virtual Platforms TLM-based virtual system with Fast CPU model −Operating System and Firmware runs on CPU model −Where RTL is needed, transactors bridge TLM and the RTL’s interface(s) −Virtual platform provides full control and visibility of HW and SW RTL Application Specific Sub-system TLM Router CPU Sub-system 3D Graphics Core Modem DDR3 Application Accelerator … … AES … … C1 L2 cache USB3.0 PCIe Gen 2,3 PCIe Gen 2,3 Ether net Ether net C2 C3 L2 cache C4 TLM Router TLM >i/f Transactor TLM IP
9 © 2013 Cadence Design Systems, Inc. All rights reserved. Early Hardware models for Software Development and Validation SMP Linux boot: CPU0 615,093,547 instructions CPU1 489,558,519 instructions Total Instructions: 1,104,652,066 In 30 seconds on a laptop computer 36 MIPS VP platform available before RTL High performance SW execution Run entire SW stack Arm Processor SRAM GIC Timer UART PCIe Core SRAM TLM Wrapper PIPE3 RTL TLM Key: Linux Kernel UDR kernel Module PCIe RC Initialization Module CDDC PCIe Core Drv Register Access Linux Shell Cmds Unit Test Func SW VP with RTL Hybrid Validate SW driver/firmware Running on the RTL eMMC UART Real Time Clock Real Time Clock USB Host USB Host Frame Buffer Mon Frame Buffer Mon Loader MUX (cRouter) (subsyst.cfg) MUX (cRouter) (subsyst.cfg) NV Clock NV Clock NV Timer NV Timer Flow Control Flow Control Smart Mem Smart Mem AXI Bridge AXI Bridge Fast Model cRouter (top.cfg) cRouter (top.cfg) Mouse Keyboard UI VNC_ SDL UI VNC_ SDL Socket Serv Interrupt Manager Interrupt Manager Reset Manager Reset Manager Term SoC reset interrupt VP with Palladium® XP Hybrid Run entire SW Stack On RTL in Palladium for majority of SoC TLM RTL Key:
10 © 2013 Cadence Design Systems, Inc. All rights reserved. Virtual Platform HW/SW Debug
11 © 2013 Cadence Design Systems, Inc. All rights reserved. How to Build It Using DPI, a SystemVerilog wrapper can connect the TLM world to RTL for register and bus- mastering interfaces Other interfaces: VIP SystemC (VSP) CPU Model w/ TLM Embedded Software SystemVerilog wrapper TLM/Slave Bridge Master/TLM Bridge Verilog IP VIP (Model, Monitor, Partner)
12 © 2013 Cadence Design Systems, Inc. All rights reserved. RTL + Firmware: How to Make It Fast Smart clocking −Keep RTL clocks off until first TLM access o We currently boot Linux in 20 seccnds −Turn off clocks when not needed o Only if you know, i.e. explicit transaction completion RTL TLM >i/f Transactor IP Clock granularity −Tie IP’s “far end” to the highest level (slowest clock) possible, e.g. a PHY parallel interface o Emulating this is easier than emulating the physical layer RTL TLM >i/f Transactor IP Link Partner
13 © 2013 Cadence Design Systems, Inc. All rights reserved. How Does All This Help Verify Firmware? Test casesTest harnessFirmware RTL Application Specific Sub-system TLM Router CPU Sub-system 3D Graphics Core Modem DDR3 Application Accelerator … … AES … … C1 L2 cache USB3.0 PCIe Gen 2,3 PCIe Gen 2,3 Ether net Ether net C2 C3 L2 cache C4 TLM Router TLM >i/f Transactor TLM IP Test cases designed with knowledge of the firmware and IP provide “full-circle” stimulus/ response model (look for expected behaviors to arise after stimulus)
14 © 2013 Cadence Design Systems, Inc. All rights reserved. Platform Example: PCIe A PCIe Root Complex is connected to an endpoint at the PIPE (PHY interface) level Linux Kernel UDR kernel Module PCIe RC Initialization Module CDDC PCIe Core Drv Register AccessLinux Shell Cmds Unit Test Func
15 © 2013 Cadence Design Systems, Inc. All rights reserved. Platform Example: DDR DRAM DRAM controller + DRAM PHY + DRAM model
16 © 2013 Cadence Design Systems, Inc. All rights reserved. Platform Example: Gig Ethernet MAC Two MACs connected back-to-back at GMII
17 © 2013 Cadence Design Systems, Inc. All rights reserved. Conclusion: Time Saved Physical hardware platform creation − Avoid all issues with boards: acquiring, board-specific IP builds and glue code, bring up Firmware development − Need not wait for hardware bring up/stability Firmware verification − Can exercise all code due to ease of error injection (through virtual registers, test harness can inject faults in “switches” or VIP models)
1 Role of Standards in TLM driven D&V Methodology Umesh Sisodia, CircuitSutra
SOC Virtual Prototyping: An Approach towards fast System- On-Chip Solution Date – 09 th April 2012 Mamta CHALANA Tech Leader ST Microelectronics Pvt. Ltd,
Laurent VUILLEMIN Platform Compile Software Manager Emulation Division The Veloce Emulator and its Use for Verification and System Integration of Complex.
SCE-MI Meeting 1 San Jose’, 14 th Nov Author: Andrea Castelnuovo SCE-MI Integrating Emulation in a system level design methodology San Jose’, 14/11/2003.
29 April 2005 Part B Final Presentation Peripheral Devices For ML310 Board Project name : Spring Semester 2005 Final Presentation Presenting : Erez Cohen.
Hardware Overview Net+ARM – Well Suited for Embedded Ethernet Single and Multiple Processor Environments Understand the System on a Chip Net+ARM Performance.
1 Chapter 2. The System-on-a-Chip Design Process Canonical SoC Design System design flow The Specification Problem System design.
April 15, 2013 Atul Kwatra Principal Engineer Intel Corporation Hardware/Software Co-design using SystemC/TLM – Challenges & Opportunities ISCUG ’13.
Silicon Building Blocks for Blade Server Designs accelerate your Innovation.
BridgePoint Integration John Wolfe / Robert Day Accelerated Technology.
LOGO HW/SW Co-Verification -- Mentor Graphics® Seamless CVE By: Getao Liang March, 2006.
Ethernet Bomber Ethernet Packet Generator for network analysis Oren Novitzky & Rony Setter Advisor: Mony Orbach Started: Spring 2008 Final Presentation.
6/30/2015HY220: Ιάκωβος Μαυροειδής1 Moore’s Law Gordon Moore (co-founder of Intel) predicted in 1965 that the transistor density of semiconductor chips.
Programmable Logic- How do they do that? 1/16/2015 Warren Miller Class 5: Software Tools and More 1.
Creation and Utilization of a Virtual Platform for Embedded Software Optimization: An Industrial Case Study Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo.
purpose Search : automation methods for device driver development in IP-based embedded systems in order to achieve high reliability, productivity, reusability.
1 Integration Verification: Re-Create or Re-Use? Nick Gatherer Trident Digital Systems.
February 28 – March 3, 2011 Stepwise Refinement and Reuse: The Key to ESL Ashok B. Mehta Senior Manager (DTP/SJDMP) TSMC Technology, Inc. Mark Glasser.
1 of 24 The new way for FPGA & ASIC development © GE-Research.
TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ,
Hardware Definitions –Port: Point of connection –Bus: Interface Daisy Chain (A=>B=>…=>X) Shared Direct Device Access –Controller: Device Electronics –Registers:
Simics/SystemC Hybrid Virtual Platform A Case Study Asad Khan Chris Wolf
2006 Chapter-1 L3: "Embedded Systems - Architecture, Programming and Design", Raj Kamal, Publs.: McGraw-Hill, Inc. 1 Hardware Elements in the Embedded.
A Flexible Architecture for Simulation and Testing (FAST) Multiprocessor Systems John D. Davis, Lance Hammond, Kunle Olukotun Computer Systems Lab Stanford.
1 Using emulation for RTL performance verification June 4, 2014 DaeSeo Cha Infrastructure Design Center System LSI Division Samsung Electronics Co., Ltd.
KVM/ARM: The Design and Implementation of the Linux ARM Hypervisor Christoffer Dall Department of Computer Science Columbia University
Embedded Systems Design at Mentor. Platform Express Drag and Drop Design in Minutes IP Described In XML Databook s Simple System Diagrams represent complex.
Peter S. Magnusson, Magnus Crhistensson, Jesper Eskilson, Daniel Forsgren, Gustav Hallberg, Johan Högberg, Frederik larsson, Anreas Moestedt. Presented.
PradeepKumar S K Asst. Professor Dept. of ECE, KIT, TIPTUR. PradeepKumar S K, Asst.
January 29, Guy Moshe General Manager Design Creation BU/ESD Innovative Virtual Prototype Technologies for System and Application Bringup Innovative.
Virtual Prototyping with Carbon Design Tools Aalap Tripathy, Rabi Mahapatra Embedded Systems Codesign Lab
I/O Hardware n Incredible variety of I/O devices n Common concepts: – Port – connection point to the computer – Bus (daisy chain or shared direct access)
Synchron’08 Jean-François LE TALLEC INRIA SOP lab, AOSTE INRIA SOP lab, EPI AOSTE ScaleoChip Company SoC Conception Methodology.
ATtiny23131 A SEMINAR ON AVR MICROCONTROLLER ATtiny2313.
Electronic system level design Teacher : 蔡宗漢 Electronic system level Design Lab environment overview Speaker: 范辰碩 2012/10/231.
© 2012 xtUML.org Bill Chown – Mentor Graphics Model Driven Engineering.
1 System Level Verification of OCP-IP based SoCs using OCP-IP eVC Himanshu Rawal eInfochips, Inc.,4655 Old Ironsides Drive, Suite 385,Santa Clara, CA
Embedded Systems Design with Qsys and Altera Monitor Program Tutorial #2.
0 Functional Verification of the SiCortex Multiprocessor System-on-a-Chip June 7, 2007 Oleg Petlin, Wilson Snyder
© Copyright Alvarion Ltd. Hardware Acceleration February 2006.
Xilinx Confidential – Internal Vidhumouli H Xilinx Advantages of Reconfigurable System Architectures.
1 Abstract & Main Goal המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory The focus of this project was the creation of an analyzing device.
© Paradigm Publishing Inc. 4-1 Chapter 4 System Software.
© 2004 Xilinx, Inc. All Rights Reserved EDK Overview.
1 Presented By: Eyal Enav and Tal Rath Eyal Enav and Tal Rath Supervisor: Mike Sumszyk Mike Sumszyk.
NetBurner MOD 5282 Network Development Kit MCF 5282 Integrated ColdFire 32 bit Microcontoller 2 DB-9 connectors for serial I/O supports: RS-232, RS-485,
7/23 CSE 325 Embedded Microprocessor System Design Fall 2010 Computer Science & Engineering Department Arizona State University Tempe, AZ Dr. Yann-Hang.
NIOS II Ethernet Communication Final Presentation By: Gilad Shterenshis Supervisor: Ina Rivkin Winter 2008.
© 2017 SlidePlayer.com Inc. All rights reserved.