Presentation on theme: "E4.Lee1 Software/Hardware Reconfigurable Network Processor for Space Networks Clement Lee Andrew Gray, Jeff Srinivasan, Allen Farrington, Valerie Stanton,"— Presentation transcript:
E4.Lee1 Software/Hardware Reconfigurable Network Processor for Space Networks Clement Lee Andrew Gray, Jeff Srinivasan, Allen Farrington, Valerie Stanton, Ken Peters, Yong Chong
E4.Lee2 Introduction Motivations for software reconfigurable paradigm in space applications Description of a reconfigurable architecture Design methodologies NavaTyrr: prototype transceiver for space-based applications based on this architecture Potential technology infusion to missions –ST-5 –StarLight Future development
E4.Lee3 Software Reconfigurable Paradigm The primary motivations behind the space-based software reconfigurable network processor are the following: –Providing long-life communications infrastructure enabled by on-orbit processor reconfiguration. –Providing greatly improved science instrumentation and processing capabilities through on-orbit science-driven reconfiguration. –Enabling rapid laboratory prototyping and rapid uploading designs of communications, navigation, and science signal processing functions to spacecraft.
E4.Lee4 Motivation: Long Life Numerous potential applications and network interactions cannot be anticipated at mission launch. Moreover, the value of adapting to these unpredictable needs is extremely high, driving the need for reconfigurability. Space missions last for many years beyond the technology. Software Reconfigurable Paradigm
E4.Lee6 Software Reconfigurable Paradigm Motivation: To enable rapid laboratory prototyping and rapid space-qualified implementations of communications, navigation, and science signal processing functions Advanced technologies in the following areas make this rapid prototyping effort possible –Flexible design platform using microprocessors and FPGAs –State-of-the art computer aided design tools Accelerate design and development Eliminate human error Quick turn around for changes
E4.Lee7 Reconfigurable Architecture RISC (Reduced Instruction Set Computer) Processor, FPGA (Field Programmable Gate Array), and RTOS (Real-Time Operating System):
E4.Lee8 Reconfigurable Architecture Hardware for NavaTyrr Analog Devices ADC/DAC evaluation boards, Xilinx Virtex XCV1000 on an Alpha Data PMC card, and Motorola PowerPC
E4.Lee10 Reconfigurable Architecture FPGA to Processor Interface
E4.Lee11 Reconfigurable Architecture Microprocessor: MCP750 with Motorola PowerPC 750 MHz –High MIPS/Watt ratio –Board package support –Driver support –Previous JPL flight experience with PowerPC processor –Radiation tolerant part available FPGA: Xilinx Virtex XCV1000 –Ability to partially reconfigure FPGA with support using modular design tools –Immunity to latch ups –Radiation tolerant part available –Usage in another JPL mission: Mars Exploration Rover (MER) Interface Card: Alpha Data ADM-XRC –Has a user input/output interface for debugging –PCI Mezzanine Card (PMC) provides ease of use with industry standard connections
E4.Lee12 Reconfigurable Architecture RTOS: Integrity from Green Hills Software (GHS) –Hardware memory protection (secure tasks, device drivers, inter- process communications) –Pre-emptive multi-tasking (true real-time scheduler) –Good vendor support (GHS works with JPL in updating RTOS) –Uses virtual memory –Field upgrade and debugging –Complete front-end and back-end tools from GHS Other RTOS considered –Rogue OS (JPL developed) Lacks back-end tools and documentation –VX Works WindRiver Lacks memory protection and virtual memory
E4.Lee13 Design Methodologies Very modular and hierarchical designs –Software: Object oriented Fine granularity libraries Allows for on-board linking –FPGA (Hardware): Design path flows from high-level design tools (SPW) to HDL to configuration files –Lower level designs implemented by tools Well tested and documented modular designs (sometimes COTS product) –Signal processing blocks –Navigation processing blocks –Science processing blocks
E4.Lee14 Design Methodologies Design Tools: Signal Processing Works (SPW) –High level signal processing design and simulation tool –A commercial standard tool for signal processing and communications research –Ability to generate Hardware Description Language (HDL) Verilog, VHDL, etc. (machine generated code) FPGA (Hardware) Tools: Xilinx tools –Foundation ISE, static timing analyzer Software Tools: GHS Multi builder –C, C++, embedded C++, Ada 95 optimizing compilers –Event analyzer, RTOS simulator, debugger, and editor
E4.Lee15 NavaTyrr Prototype Transceiver Lower 3 layers of the OSI are implemented in NavaTyrr. Other layers are commercially available and are used to demonstrate the NavaTyrr.
E4.Lee16 NavaTyrr Prototype Transceiver Physical Layer: Digital Baseband Modulator/Demodulator –Demodulator Specifications BPSK with NRZ and Manchester pulse waveforms Data rates: 1kbps to 4 Mbps 400 kHz to 0.1 Hz loop filter bandwidths (2nd order) Programmable carrier frequency For SNR (E B /N O ) 0 dB –Demodulator Basic Building Blocks Costas Loop (carrier phase recovery for NRZ data) Phased Locked Loop (carrier recovery for a tone or Manchester coded data) Data Transition Tracking Loop, symbol timing-clock recovery Digital Automatic gain control (AGC) to compensate for analog wide band AGC Frequency Acquisition using open loop FFT algorithm Costas Loop, PLL lock detection with I-Q power estimation
E4.Lee22 NavaTyrr Prototype Transceiver Data link layer: Proximity-1 protocol –Intended for space communications around Mars –Specifies physical layer characteristics (frequencies, modulation, channel coding, data rates, and link acquisition procedures) –Primarily emphasizes point to point connection (expanding Prox-1 to one to many connections is currently being done) –Specifies a reliable link mode as well as an unreliable link mode –Full duplex link –Software controller of the hardware, turning on/off parts of the transceiver when necessary, changing data rates, etc.
E4.Lee23 NavaTyrr Prototype Transceiver Data link layer: Proximity-1 protocol (continued) –Software/hardware Attached Synchronization Marker (ASM) determines frame synchronization –Hardware buffer in transmitter and receiver Accommodates high data rates with a relatively low speed software interrupt Sized at 4 kilobytes for the highest data rate Software reads one half buffer during interrupt Interrupt triggered when buffer pointer reaches half or full Implemented using Xilinx circulating dual port RAM
E4.Lee24 NavaTyrr Prototype Transceiver Network layer: Ethernet bridge –Acts as driver to interface Proximity-1 packets to data packetized for higher level protocols, i.e. TCP/IP –Analogous to a commercial router (but this one will be in space using RF links Upper layers of OSI: –Other layers beyond TCP/IP already implemented by commercial plug and play software –Application layer: Apple’s QuickTime
E4.Lee25 NavaTyrr Prototype Transceiver USO ref xmtrcvxmtrcv USO ref Play MP3s LAN Full-Duplex Communications Demonstration Features Digital Carrier @ Baseband BPSK Modulation of Proximity-1 Framed “Data” Convolutional Coding Digital-to-Analog Conversion Analog-to-Digital Conversion Carrier Tracking Symbol Tracking Viterbi Decoding Extraction of “Data” from Proximity-1 Frames Reconfigurable Transceiver Components PowerPC 750 + Xilinx Virtex V1000 FPGA Analog Devices ADC & DAC components C++ and Verilog Software Modules Spacecraft One Encodes/Streams Video Spacecraft Two Decode & Play Video
E4.Lee26 NavaTyrr Prototype Transceiver Preliminary performance: –Effective data rate 90% of actual data rate from Proximity-1 50% of actual data rate from Ethernet bridge and Proximity-1 overhead –Network latency High Buffer implementation not optimal for sending acknowledgements and retransmissions Future implementation of buffer will decrease network latency
E4.Lee27 NavaTyrr Prototype Transceiver Reconfigurability demonstrated –Full reconfiguration using microprocessor At any given time, we can load any configuration file into the FPGA using the processor Scrubbing reprograms the entire FPGA to ensure that no portion of the chip has been corrupted by radiation or other effects –Partial reconfiguration for testing radiation mitigation effects We manually corrupted the FPGA by partially reconfiguring a small part of the FPGA to simulate radiation effects –Partial reconfigurable design Currently working on
E4.Lee28 Space Applications Space Technology 5’s (ST-5) Constellation Communications Transceiver (CCNT) in ‘03 –Dynamic downloads different modes of operation will involve downloading a different entire FPGA configuration file –Similar hardware platform (uses flight qualified evolution of the NavaTyrr commercial hardware) Atmel-Grenoble PPC750 (CGA package) Xilinx XQRV 1000 rad-tolerant (CGA package) RS-422 interfaces instead of Ethernet StarLight’s Autonomous Formation Flyer (AFF) in ‘06 –Similar to CCNT
E4.Lee29 Future Development Space Reconfiguration Memory storage Complete file upload Reliability Large-Scale Partial Reconfiguration –Multiple channels with different modulation and coding schemes More complex networks –Multi-User Network prototype Multiple channels operating in each processor Develop laboratory prototype with larger number of nodes –More complex protocols Improved Proximity-1
E4.Lee30 Summary Software Reconfigurable Paradigm –Long life –Providing greatly improved science instrumentation and processing capabilities –rapid prototyping and rapid development Reconfigurable Architecture –FPGA –RISC processor –RTOS Design Methodologies –High level, modular, hierarchical designs –Tools create lower level designs