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17/04/2015 The CPU Seb Welford C.Eng MIET Slide 1 The CPU The beating heart of the computer.

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Presentation on theme: "17/04/2015 The CPU Seb Welford C.Eng MIET Slide 1 The CPU The beating heart of the computer."— Presentation transcript:

1 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 1 The CPU The beating heart of the computer

2 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 2 The CPU – overview The Central Processing Unit - CPU What does it do? How does it do it? What varieties? What is inside it? How has it developed? Where does it go next? Please ask when you need explanation

3 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 3 The CPU - What does it do? The fetch-execute cycle In order to do anything the CPU has to find out what to do It therefore fetches an instruction from the stored program Then it does what the instruction says – executes it

4 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 4 The CPU - Registers The CPU contains a basic set of Registers A register is an array of logical elements Each element (one per bit) remembers what it was last loaded with It can be toggled, thus can be told to increment (count) The whole array can act as a counter

5 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 5 The Register (1) Set Reset Toggle (clock) Set Reset Set Reset Bit 0Bit 1Bit 2 The clock may also be common to load the value in in

6 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 6 The Register (2) From databus To databus 0 15 Clock

7 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 7 The CPU - Registers The CPU contains a basic set of registers Program Counter – points at next instruction Accumulator – contains data or address Index register – points at data Stack register – points at working memory Program Counter – initialised to default address Accumulator – not initialised Index register – not initialised Stack register – not initialised

8 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 8 Memory Stored program memory Idea introduced around 1945 derived from work at Bletchley Park –Von Neumann architecture –Manchester University ‘Baby’ Working memory –Including on-chip memory Long term memory –Disc drives

9 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 9 Basic Von Neumann architecture CPU ADDRESS DATA PROGRAM MEMORY ROM/RAM DATA MEMORY RAM PERIPHERALS INPUT / OUTPUT CONTROL

10 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 10 Memory speed Memory speed (access time) varies RAM (Random Access Memory) is fairly fast ROM (Read Only Memory) depends on type Hard Disc (HD) is slow Compact Disc (CD/DVD) is very slow Solid State Disc (SSD) is faster than HD On-Chip memory is fastest of all – used for Cache (later)

11 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 11 Memory layout The memory layout depends on its use Parts are static (ROM) Parts are dynamic (RAM) Peripherals may appear in the memory map Program memory at startup (ROM) Read Program memory while running (RAM) Read – needs protection Data memory (RAM) (Read/Write) Stack (RAM) (Read/Write) Peripherals (Read/Write)

12 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 12 Types of instructions (1) Move data –Memory to Register –Register to Memory –Memory to Memory Arithmetic –Add –Subtract –Multiply

13 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 13 Types of instructions (2) Branch –Direct (Jump = GOTO) –Conditional Mathematical e.g. Less than, greater or equal Depending on status flag

14 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 14 Instruction types(1) Reduced Instruction Set Computers (RISC) Early computers, 8 or 16 bit Each instruction takes one clock cycle Each instruction (code) occupies one Word or Byte

15 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 15 Instruction types (2) Complex Instruction Set Computers (CISC) Later computers: 16, 32 or 64 bit Each instruction takes one or more clock cycles Each instruction (code) occupies one or more Bytes

16 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 16 Interrupts (1) Some operations are time sensitive Input from operator –Mouse –Keyboard Communications –Serial devices e.g. USB Hardware –Hard discs (data available/transfer complete)

17 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 17 Interrupts (2) An interrupt stops the current program –Returns after interrupt is serviced Special code is needed for each interrupt –Saves current program registers –Restores registers when completed

18 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 18 The CPU – Inside Registers Depending on type of CPU 8 bit (16 bit address) –6800, 6502, 8080, Z80 16 bit (32 bit address) –Intel 8086 (Segmented address space) –Motorola 68000 (32 bit internal) 32 bit –Intel 80286, 80386 etc –Motorola 68020, 68030 etc.

19 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 19 8086 – all 16 bit registers Data registers –A (ah,al) B (bh,bl) C (ch,cl) D (dh,dl) Index (Address) registers –SI, DI, BP, SP, IP Status (flags) Segment registers –CS, DS, ES, SS –Provide address extension past the 64KByte limit

20 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 20 Basic CPU architecture Internal structure of 8086 processor

21 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 21 68000 – all 32 bit registers Data registers –D0.. D7 Address registers –A0..A7 A7 conventionally used for Stack pointer Status register Interrupt levels 1..7

22 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 22 80x86 vs 68000 (1) Intel 8086 –Early support good (blue box) –Address extension via Segment registers –Awkward to program Motorola 68000 –Early support poor –32 bit internal (linear address space) –Easy to program

23 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 23 80x86 vs 68000 (2) Intel vigorous in product development –80x86 mainly used in IBM Personal Computers Domestic Commercial –Context switch fast Motorola less so –680x0 mainly used in specialist systems Defence –Context switch slow (many registers) Impedes multi-tasking –Superseded by PowerPC

24 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 24 The CPU - How has it developed? Moore’s ‘Law’ (1965) The number of transistors on an IC doubles every two years Has proved surprisingly accurate so far Speed increased by feature size reduction May be now slowing down as the dimensions approach molecular size

25 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 25 Moore’s Law Graph confirms the hypothesis However may be slowing down

26 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 26 Application needs We will now look at how Applications and Operating Systems (OS) have affected the development of the CPU MS Windows is arguably the main platform currently in use Apple IOS has similar needs –Now has moved to x86 hardware Linux also has developed Not forgetting Android

27 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 27 Multi-tasking (1) OS’s needs to run several programs at the same time Need to separate programs and their data Early Windows versions very poor –Blue Screen of Death (BSoD) Windows NT (derived from VAX-VMS) Succeeded by Windows XP etc.

28 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 28 Multi-tasking (2) Each program needs its own memory space Virtual memory solves the problem Operating system keeps track of memory Ideally hardware keeps a register for each program Memory needs have increased 64 bit CPU’s have become common –~18.5 * 10 18 Bytes addressing capability –Should be enough for now …

29 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 29 Processing Speed (1) Programs become more complex Need more CPU speed (fancy graphics) Moore’s law applies Clock speed has increased Now nears limit ~ 3GHz –On chip clock multiplier Off-load some tasks to Graphics processor

30 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 30 Processing speed (2) Factors limiting speed Register timing Clock skew Transistor capacitance Heating effect Speed of light

31 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 31 Processing Speed (3) More methods of speed increase Parallel processing with multiple cores –Operating system distributes the tasks Memory Cache –Stores immediate data in on-chip fast memory Look-ahead –Fetch anticipated instructions But Branch can cause discarding of instructions

32 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 32 80x86 evolution (1) Other manufactures compete with Intel Primarily AMD, but also others Has forced performance race Addressing modes and range have removed the need for Segmentation Other improvements

33 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 33 Example CPU AMD Athlon –Superseded example –Now surplus to requirement

34 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 34 80x86 evolution (2) 1978 8086 with Segmented addressing 1982 80268 with 30bit virtual addressing 1985 AMD produces AM386 clone 1989 Instruction pipelining, Floating point unit 1995 Pentium with Out-of-order execution, Cache 1999 AMD Athlon with Out-of-order execution, Cache 2000 Pentium 4 with Hyperthreading 2003 Low power versions, AMD Hypertransport 2004 Pentium 4, 64 bit internal 2006 Intel Core 2 Multi-core 2007 AMD Phenom Multi-core 2011 Intel Sandy Bridge series

35 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 35 Advanced features Virtual memory addressing –Protected mode operation Pipelining –Array etc. processing Out-of-Order processing –Anticipated instructions executed while waiting for large instructions to complete Hyper-threading –Parallel operation in logical elements Multi-core processors

36 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 36 Virtual memory addressing (1) Program uses 512 Byte pages Page table allocates Physical memory Pages are swapped out to disc when ‘stale’ When a swapped page is accessed a Page Fault interrupts program flow OS restores page to memory Program flow continues

37 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 37 Virtual memory addressing (2) Physical memory Program A 0000 Working memory Swapped out Program B 0000 Page table

38 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 38 Pipelining Instructions are fetched early Then kept in a queue awaiting use This saves time waiting for memory access However a branch may cause the queue to be flushed

39 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 39 Out of Order Processing Some instructions take many CPU cycles Following instructions may be short CPU starts long instruction in local cache Following instruction(s) are done in local cache When long instruction data is complete it is used Then shorter instructions are used

40 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 40 Hyper-threading Each program is a ‘Thread’ There may be many threads in a system Parts of the CPU core are duplicated This can improve performance ~ 30% with software that knows it exists, e.g. Video processing Not very helpful with common software

41 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 41 Multi-core processors CPU Processors share internal bus, cache etc. Could speed up processing by factor of ‘n cores’ Operating system tasks each core Processing may be unbalanced, therefore … Speed increase may not be achieved in practice Common parts may be bottleneck Internal Buses

42 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 42 The CPU – summary What it does How it does it Varieties of processors What is inside it How it has evolved Some Advanced features

43 17/04/2015 The CPU Seb Welford C.Eng MIET Slide 43 The CPU Any more questions? p.s. I used wikipedia to remind me of what I had forgotten and had not fully kept up with!


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