# Reading1: An Introduction to Asynchronous Circuit Design Al Davis Steve Nowick University of Utah Columbia University.

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Reading1: An Introduction to Asynchronous Circuit Design Al Davis Steve Nowick University of Utah Columbia University

Signaling Protocol SenderReceiver req ack data Signaling Protocol: communication protocol req: initiate an action ack: signal completion of that action

Signaling Protocol Control signaling 1. Two-phase handshaking protocol 2. Four-phase handshaking protocol Data signaling 1. Bundled Data with two-phase, four-phase HPs 2. Dual-rail Data with two-phase, four-phase HPs,

Control Signaling Protocol Four -phase Handshaking protocol Level signaling or return to zero SenderReceiver req ack data

Data Signaling Protocol Bundled Data Signaling 1. Similar to synchronous circuits 2. Measure maximum delay of each circuit piece Com. Logic Delay A B C SenderReceiver req ack data a. Bundled data Computation b. Bundle Data transfer 3. Require n+2 wires

Data Signaling Protocol Dual­Rail Data signaling 1. Two wires per bit, encoded to show validity. 2. 00 = no data (spacer), 01 = 0, 10 = 1, 11 = error Com. Logic A B C A1=0 A0=0 A1=0 A0=1 A1=1 A0=0 A1=1 A0=1 a. No data b. valid 0 c. valid 1 d. illegal 3. Require 2n wires Register

Signaling Protocol: EX Bundling Constraint VS Delay-Insensitive adders

Completion Detection Circuits Self-timed component with completion detection circuit. Ack: completion of dual-rail signal DoneReset=1: completion of computation DoneReset=0: completion of reset

Classes of Asynchronous Circuits Classification based on delay model: Gate and wire 1. Delay-insensitive (DI) circuits. 2. Quasi­delay­insensitive (quasi­DI or QDI) circuits 3. Speed­independent (SI) circuits 4. Self­timed (ST)circuits DISTQDI Async SI

Delay-insensitive circuits Arbitrary (unbounded but finite) delays on gates and wires Most robust (reliable) circuits Very small class (Martin)

Quasi­delay­insensitive circuits Delay insensitive with isochronous forks Delay in isochronous forks assumed to be similar Weakest compromise to pure delay-insensitivity needed to build practical circuits fork A BCBC

Speed­independent circuits Arbitrary delays on gates Wires have no delay Introduced by David Muller in the 50’s

Self­timed circuits Communication between elements is delay­insensitive Elements may be DI, QDI, SI or well­bounded Introduced by Seitz

Hazards Hazards: unwanted glitches 0 1 glitch Combinational and sequential Hazards May not be severe: No inverter no hazard

Combinational Hazards Static hazards: Dynamic hazards 0 1 0 11 0 Static 0 hazard Static 1 hazard

Combinational Hazards Static Hazard in Single Input Change

Combinational Hazards Static Hazard in Multiple Input Change

Combinational Hazards Dynamic Hazard in Multiple Input Change

Petri Net Petri Net :bipartite graph places (circle) transitions (bar) Token (dot) A R1 B If A is true then B is true

Petri Net A R1 C Input places of a transition: Output places of a transition: Transition enable: all conditions of a transition are true Transition fire: removes the tokens from the input places and insert tokens to output places B A R1 C B Transition Firing

Petri Net: (Interface Net) C-element XYXY Z

Petri Net Arbiter

Petri Net: I-Net I-Net describes the allowed interface behavior I-Net ==> ISG (Interface State Graph) (finite state machine) X Y Z X Y 1 2 3 4

Petri Net: X+ Z+ Y+ ISG ==> Encoded ISG X-Y- X+Y+ Z- X-Y- 000 100010 110 111 011 101 001 XY Z

Translation Method: Wireprefix*[a?;b!] Toggleprefix*[a?;b!;a?;c!] C-elementprefix*[a?||b?;c!] Mergeprefix*[a?|b?;c!] Basic DI Elements :

Translation Method: Operators: ? an input to the wire ! an output of the wire ; concatenation * repetition | choice || weave pref prefix-closure operator

Modulo-3 Counter MOD3=prefix*[a?;q!;a?;q!;a?;p!]

Tangram Compiler-based approach by van Berkel at Philips Research Laboratories and Eindhoven University of Technology Tangram: based on CSP, is a specification language for concurrent systems. A Tangram program for a 1­place buffer, BUF1: (a?W&b!W ) * | [x : var W | #[a?x; b!x]] |

Tangram A Tangram program for a 1­place buffer, BUF1: (a?W & b!W ) * | [x : var W | #[a?x; b!x]] | Interface: an input port, a, an output port, b, data type, W command [x : var W | #[a?x; b!x]] x is local variable ; : sequencing # : infinite repetition T : transfer go

Tangram: Buf1 Channel (arc): c, d, e, wx, rx, a, b A channel has two ports Active port: black dot initiates a request Passive port: white dot returns an acknowledgment Buf1: data is received on port a stored in internal variable x; data is then sent out on port b.

Tangram: Buf2=(a?W&c!W )*| [b:chan W|(BUF 1 (a; b) || BUF 2 (b; c))] | New command ||:parallel composition. :synchronizer Major goal of Tangram rapid turnaround time low­power implementation. portable electronics: an error corrector for a digital compact cassette player counters, decoders, image generators

Micropipeline 4-stage pipeline

Micropipeline

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