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Reading1: An Introduction to Asynchronous Circuit Design Al Davis Steve Nowick University of Utah Columbia University.

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Presentation on theme: "Reading1: An Introduction to Asynchronous Circuit Design Al Davis Steve Nowick University of Utah Columbia University."— Presentation transcript:

1 Reading1: An Introduction to Asynchronous Circuit Design Al Davis Steve Nowick University of Utah Columbia University

2 Signaling Protocol SenderReceiver req ack data Signaling Protocol: communication protocol req: initiate an action ack: signal completion of that action

3 Signaling Protocol Control signaling 1. Two-phase handshaking protocol 2. Four-phase handshaking protocol Data signaling 1. Bundled Data with two-phase, four-phase HPs 2. Dual-rail Data with two-phase, four-phase HPs,

4 Control Signaling Protocol Four -phase Handshaking protocol Level signaling or return to zero SenderReceiver req ack data

5 Control Signaling Protocol Two-phase Handshaking protocol Transition signaling or Non-return to zero SenderReceiver req ack data

6 Data Signaling Protocol Bundled Data Signaling 1. Similar to synchronous circuits 2. Measure maximum delay of each circuit piece Com. Logic Delay A B C SenderReceiver req ack data a. Bundled data Computation b. Bundle Data transfer 3. Require n+2 wires

7 Data Signaling Protocol Dual­Rail Data signaling 1. Two wires per bit, encoded to show validity = no data (spacer), 01 = 0, 10 = 1, 11 = error Com. Logic A B C A1=0 A0=0 A1=0 A0=1 A1=1 A0=0 A1=1 A0=1 a. No data b. valid 0 c. valid 1 d. illegal 3. Require 2n wires Register

8 Signaling Protocol: EX Bundling Constraint VS Delay-Insensitive adders

9 Completion Detection Circuits Self-timed component with completion detection circuit. Ack: completion of dual-rail signal DoneReset=1: completion of computation DoneReset=0: completion of reset

10 Classes of Asynchronous Circuits Classification based on delay model: Gate and wire 1. Delay-insensitive (DI) circuits. 2. Quasi­delay­insensitive (quasi­DI or QDI) circuits 3. Speed­independent (SI) circuits 4. Self­timed (ST)circuits DISTQDI Async SI

11 Delay-insensitive circuits Arbitrary (unbounded but finite) delays on gates and wires Most robust (reliable) circuits Very small class (Martin)

12 Quasi­delay­insensitive circuits Delay insensitive with isochronous forks Delay in isochronous forks assumed to be similar Weakest compromise to pure delay-insensitivity needed to build practical circuits fork A BCBC

13 Speed­independent circuits Arbitrary delays on gates Wires have no delay Introduced by David Muller in the 50’s

14 Self­timed circuits Communication between elements is delay­insensitive Elements may be DI, QDI, SI or well­bounded Introduced by Seitz

15 Hazards Hazards: unwanted glitches 0 1 glitch Combinational and sequential Hazards May not be severe: No inverter no hazard

16 Combinational Hazards Static hazards: Dynamic hazards Static 0 hazard Static 1 hazard

17 Combinational Hazards Static Hazard in Single Input Change

18 Combinational Hazards Static Hazard in Multiple Input Change

19 Combinational Hazards Dynamic Hazard in Multiple Input Change

20 Petri Net Petri Net :bipartite graph places (circle) transitions (bar) Token (dot) A R1 B If A is true then B is true

21 Petri Net A R1 C Input places of a transition: Output places of a transition: Transition enable: all conditions of a transition are true Transition fire: removes the tokens from the input places and insert tokens to output places B A R1 C B Transition Firing

22 Petri Net: (Interface Net) C-element XYXY Z

23 Petri Net Arbiter

24 Petri Net: I-Net I-Net describes the allowed interface behavior I-Net ==> ISG (Interface State Graph) (finite state machine) X Y Z X Y

25 Petri Net: X+ Z+ Y+ ISG ==> Encoded ISG X-Y- X+Y+ Z- X-Y XY Z

26 Translation Method: Wireprefix*[a?;b!] Toggleprefix*[a?;b!;a?;c!] C-elementprefix*[a?||b?;c!] Mergeprefix*[a?|b?;c!] Basic DI Elements :

27 Translation Method: Operators: ? an input to the wire ! an output of the wire ; concatenation * repetition | choice || weave pref prefix-closure operator

28 Modulo-3 Counter MOD3=prefix*[a?;q!;a?;q!;a?;p!]

29 Tangram Compiler-based approach by van Berkel at Philips Research Laboratories and Eindhoven University of Technology Tangram: based on CSP, is a specification language for concurrent systems. A Tangram program for a 1­place buffer, BUF1: (a?W&b!W ) * | [x : var W | #[a?x; b!x]] |

30 Tangram A Tangram program for a 1­place buffer, BUF1: (a?W & b!W ) * | [x : var W | #[a?x; b!x]] | Interface: an input port, a, an output port, b, data type, W command [x : var W | #[a?x; b!x]] x is local variable ; : sequencing # : infinite repetition T : transfer go

31 Tangram: Buf1 Channel (arc): c, d, e, wx, rx, a, b A channel has two ports Active port: black dot initiates a request Passive port: white dot returns an acknowledgment Buf1: data is received on port a stored in internal variable x; data is then sent out on port b.

32 Tangram: Buf2=(a?W&c!W )*| [b:chan W|(BUF 1 (a; b) || BUF 2 (b; c))] | New command ||:parallel composition. :synchronizer Major goal of Tangram rapid turnaround time low­power implementation. portable electronics: an error corrector for a digital compact cassette player counters, decoders, image generators

33 Micropipeline 4-stage pipeline

34 Micropipeline


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