# Microprocessor-based Systems Course 3

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Microprocessor-based Systems Course 3
A (simple) computer structure

Instruction format - Without explicit operands - With one operand
Operation code - Without explicit operands - With one operand Operation code Operand1 - Address Operation code Operand1 - Address Operand2 - Address/Data - With 2 operands Operation code Operand1 - Address Operand2 - Address/Data Result - Address - With 2 operands and a result

Addressing modes How the operand is determined
Immediate addressing – for constants MOV AX, 1234h Direct addressing – for simple variables SUB BX, [100h] Indexed addressing – for vectors ADD [SI+500h], AX Based addressing – for records AND DX, [BX+200h] Mixed (based and indexed) – for complex data structures OR CX, [SI+BX+100h]

The instruction set of a simple computer
Op. code: 0 0 0 1 1 0 1 1 7 6 Op. code Address field 0 0 a b c x x x 0 0 0 0 0 1 1 1 1 NOP xxx - CLA xxx A=0 CPL xxx A=Not A SHR xxx A=A>>1 SHL xxx A=A<<1 SKIPO xxx If A0=1 NP++ SKIPN xxx If A7=1 NP++ STOP xxx Stop the clock Instruction Instr. code Explanations JMP 01 addr NP=addr ADD 10 addr A=A+M[addr] MEM 11 addr M[addr]=A

The general scheme of a simple computer
Address display Data display STOP START Clock gen. Sel_Op Sel_I/D Ld_IR CLK IR – instruction reg. INIT M U X Phase gen. OC OC/Addr M WrM UAL 1 Decoder and comand block MUX Man/Auto LdPC Program counter micocomands IncPC SHR A MUX Ld_A Man/Auto SHL RstA Front panel Addr. switches Data switches

Decomposition of instructions into phases
INIT I1 Sel_I/D=0 Ld_IR I2 IncPC E1 E1 JMP ADD MEM NOP CLA CPL SHR SHL SKIPO SKIPN STOP Sel_I/D=1 Sel_op=0 1 1 LdPC Sel_I/D=1 RstA Sel_op=1 A0 A7 IncPC IncPC E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 E2 Sel_I/D=1 LdA WrM LdA SHR SHL STOP

Phase generator (PG), Instruction decoder (ID) and Command and control block (CCB)
Modulo 4 counter CLK CG INIT 7 6 2 3 DEC 11 MEM JMP DEC ADD Stop NOP a. Phase generator b. Instruction decoder Sel_I/D = E1  (ADD + MEM) E1 MEM ADD Sel_I/D CCB STOP I1 I2 E2 NOP microcommands a. The contro and command block b. Implementation of the Sel_I/D cmd.

Sequential execution of instructions (Scalar architecture)
Execution phases of an instruction: Instruction fetch (IF) Instruction decode (ID) Execution (Ex) Memory operation (Mem) Write back (Wr) CPI = 5 IF ID Ex Me Wr IF ID Ex Me Wr IF ID Ex Me Wr Instr. 1 Instr. 2 Instr. 3

Parallel instruction execution on a pipeline architecture (assembly line)
IF ID Ex Mem Wr IF ID Ex Mem Wr instruction i instruction i2 Sequential execution CPI = 5 T T T T T T T T T T10 Parallel execution CPI=1 (ideal case) i1 i2 i3 i4 i6 IF ID Ex Mem Wr IF ID Ex Mem Wr IF ID Ex Mem Wr Comparison between sequential and pipeline execution

Example of a pipeline architecture
IR P C Instr. mem. Data mem. instr. addr Reg. block. +4 Reg. block addr. Di IF ID Ex Mem Wr A CPU with a pipeline structure A B R I M D e c ex me wr C1 C2 C3

Hazard cases in pipeline architecture
Data hazard Data dependency between consecutive instructions Solutions: Idle states, multiple registers, instruction reordering IF ID Ex Mem Wr MOV AX, 5 IF ID Ex Wr ADD BX, AX IF ID Ex Wr SUB CX, 5 IF ID Ex Mem MOV DX, CX

Hazard cases in pipeline architecture
Control hazard Caused by jump/branch instructions Solutions: branch prediction, memorize previous jumps JE et IF ID Ex ADD AX, BX IF ID Ex Wr SUB CX, DX IF ID Ex Wr et1: MOV SI, 1234h IF ID Ex Mem Wr

Hazard cases in pipeline architecture
Structural hazard Two different phases of consecutive instructions require the same structural unit (e.g. ALU, memory, etc.) Solutions: Idle states, instruction reordering, multiple structural units (e.g. multiple execution units, ALUs, data memory and instruction memory) IF ID Ex Wr IF ID Ex Mem Wr

Superscalar and superpipeline architectures
T1 T2 T3 T4 T5 T6 instr. i IF ID Ex Mem Wr instr. i+1 IF ID Ex Mem Wr a. Superscalar architecture CPI=1/2 instr. i IF ID Ex Mem Wr instr. i IF ID Ex Mem Wr T1 T2 T3 T4 T5 T6 instr. i IF ID Ex Mem Wr b. Superpipeline architecture CPI=1/2 instr. i IF ID Ex Mem Wr instr. i IF ID Ex Mem Wr instr. i IF ID Ex Mem Wr Comparison between superscalar and superpipeline architectures

Scheduling instruction execution
Objective: reordering instruction execution in order to avoid hazard situations and increase performance Static scheduling: Reordering in the compilation phase Instructions are grouped in Very Long Instruction Words VLIW – Very Long Instruction Word Dynamic scheduling: Reordering during the execution of a program Techniques: data flow analysis, dependency trees, branch predictions