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1 Microprocessor-based Systems Course 3 A (simple) computer structure.

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Presentation on theme: "1 Microprocessor-based Systems Course 3 A (simple) computer structure."— Presentation transcript:

1 1 Microprocessor-based Systems Course 3 A (simple) computer structure

2 2 Instruction format Operation code - Without explicit operands Operand1 - AddressOperation code Operand1 - AddressOperation codeOperand2 - Address/Data - With one operand Operand1 - Address Operation code Operand2 - Address/DataResult - Address - With 2 operands - With 2 operands and a result

3 3 Addressing modes  How the operand is determined Immediate addressing – for constants  MOV AX, 1234h Direct addressing – for simple variables  SUB BX, [100h] Indexed addressing – for vectors  ADD [SI+500h], AX Based addressing – for records  AND DX, [BX+200h] Mixed (based and indexed) – for complex data structures  OR CX, [SI+BX+100h]

4 4 The instruction set of a simple computer Instruc tion Instr. code Explanations JMP01 addrNP=addr ADD10 addrA=A+M[addr] MEM11 addrM[addr]=A Op. code : Address field Op. code a b c x x x NOP xxx- CLA xxxA=0 CPL xxxA=Not A SHR xxxA=A>>1 SHL xxxA=A<<1 SKIPO xxx If A 0 =1 NP++ SKIPN xxx If A 7 =1 NP++ STOP xxx Stop the clock

5 5 The general scheme of a simple computer Clock gen. STOPSTART Phase gen. INIT OCOC/Addr Decoder and comand block micocomands MUXMUX Program counter LdPC IncPC MUX Front panel MUX A SHR SHL M WrM UAL Ld_A Ld_IR Sel_I/D IR – instruction reg. 1 0 Addr. switches Data switches Man/ Auto CLK Sel_Op Data displayAddress display RstA

6 6 Decomposition of instructions into phases I1 Sel_I/D=0 Ld_IR IncPC I2 E1 JMP INIT LdPC E2 Sel_I/D=1 ADD Sel_I/D=1 Sel_op=0 E2 LdA MEM Sel_I/D=1 E2 WrM NOP E2 CLA RstA E2 CPL E2 A0A0 E1 SHR E2 SHR SHL E2 SHL SKIPO E2 STOP E2 STOP IncPC 1 0 A7A7 SKIPN E2 IncPC 1 0 Sel_op=1 LdA

7 7 Phase generator (PG), Instruction decoder (ID) and Command and control block (CCB) DEC I1I2E1 E2 Modulo 4 counter CLK CG INIT a. Phase generator RI DEC MEM ADD JMP DEC Stop NOP b. Instruction decoder a. The contro and command block b. Implementation of the Sel_I/D cmd. Sel_I/D = E1  (ADD + MEM) E1 MEM ADD Sel_I/D CCB Sel_I/DSTOP I1I2E1E2MEMNOP microcommands

8 8 Sequential execution of instructions (Scalar architecture)  Execution phases of an instruction: 1. Instruction fetch (IF) 2. Instruction decode (ID) 3. Execution (Ex) 4. Memory operation (Mem) 5. Write back (Wr) CPI = 5 IFIDExMeWrIFIDExMeWrIFIDExMeWr Instr. 1Instr. 2Instr. 3

9 9 Parallel instruction execution on a pipeline architecture (assembly line) IF ID Ex Mem Wr IF ID Ex Mem Wr instruction i 1 instruction i 2 Sequential execution CPI = 5 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 Parallel execution CPI=1 (ideal case) i1i1 i2i2 i3i3 i4i4 i6i6 IF ID Ex Mem Wr Comparison between sequential and pipeline execution T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10

10 10 Example of a pipeline architecture IR PCPC Instr. mem. Data mem. instr. addr Reg. block. +4 Reg. block addr. Di IF ID Ex Mem Wr A CPU with a pipeline structure A B R I M D DecDec ex me wr me wr C1C2C3

11 11 Hazard cases in pipeline architecture  Data hazard Data dependency between consecutive instructions Solutions:  Idle states, multiple registers, instruction reordering IF ID Ex Mem Wr MOV AX, 5 IF ID Ex Wr ADD BX, AX IF ID Ex Wr SUB CX, 5 IF ID Ex Mem MOV DX, CX

12 12 Hazard cases in pipeline architecture  Control hazard Caused by jump/branch instructions Solutions: branch prediction, memorize previous jumps JE et1 IF ID Ex ADD AX, BX IF ID Ex Wr SUB CX, DX IF ID Ex Wr et1: MOV SI, 1234h IF ID Ex Mem Wr

13 13 Hazard cases in pipeline architecture  Structural hazard Two different phases of consecutive instructions require the same structural unit (e.g. ALU, memory, etc.) Solutions: Idle states, instruction reordering, multiple structural units (e.g. multiple execution units, ALUs, data memory and instruction memory) IF ID Ex Wr IF ID Ex Mem Wr

14 14 Superscalar and superpipeline architectures instr. i IF ID Ex Mem Wr instr. i+1 IF ID Ex Mem Wr instr. i+2 IF ID Ex Mem Wr instr. i+3 IF ID Ex Mem Wr T1 T2 T3 T4 T5 T6 a. Superscalar architecture CPI=1/2 instr. i IF ID Ex Mem Wr instr. i+1 IF ID Ex Mem Wr instr. i+2 IF ID Ex Mem Wr instr. i+3 IF ID Ex Mem Wr T1 T2 T3 T4 T5 T6 b. Superpipeline architecture CPI=1/2 Comparison between superscalar and superpipeline architectures

15 15 Scheduling instruction execution  Objective: reordering instruction execution in order to avoid hazard situations and increase performance  Static scheduling: Reordering in the compilation phase Instructions are grouped in Very Long Instruction Words  VLIW – Very Long Instruction Word  Dynamic scheduling: Reordering during the execution of a program Techniques: data flow analysis, dependency trees, branch predictions


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