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Jan 28, 2004Blackfin Compute Unit REV B A comparison of DSP Architectures BlackFin ADSP-BFXXX Compute Unit Based on a ENEL619.23 white paper prepared by.

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Presentation on theme: "Jan 28, 2004Blackfin Compute Unit REV B A comparison of DSP Architectures BlackFin ADSP-BFXXX Compute Unit Based on a ENEL619.23 white paper prepared by."— Presentation transcript:

1 Jan 28, 2004Blackfin Compute Unit REV B A comparison of DSP Architectures BlackFin ADSP-BFXXX Compute Unit Based on a ENEL white paper prepared by Darrell Anklovitch

2 Jan 28, 2004Blackfin Compute Unit REV B Overview Architecture Overview Register Map ALU features and sample instructions Multiplier features and sample instructions Shifter features and sample instructions

3 Jan 28, 2004Blackfin Compute Unit REV B References ADSP-BF535 Blackfin Processor Hardware Reference, Rev 2, April 2004, Analog Devices. – Section 2 Blackfin Processor Instruction Set Reference, Rev 2, May 2003, Analog Devices. – Sections 8 ~ 10, 14 & 15 A number of the figures in this presentation are based on figures found in the ADSP-BF535 Blackfin Processor Hardware Reference.

4 Jan 28, 2004Blackfin Compute Unit REV B ADSP-2106x Core Architecture

5 Jan 28, 2004Blackfin Compute Unit REV B Register File and COMPUTE Units Key issues –5 data paths FROM COMPUTE units –5 data paths TO COMPUTE units –Highly parallel operations UNDER THE RIGHT CONDITIONS

6 Jan 28, 2004Blackfin Compute Unit REV B BF533 Memory Accesses Under the right conditions -- 4 memory accesses at same time 64 bit Instruction Fetch, 2x32 bit Data Loads, 32 bit Data Store PLUS up to 2 ALU(32 bit) and 2 MAC(16 bit) operations at the same time PLUS background DMA activity

7 Jan 28, 2004Blackfin Compute Unit REV B Compute Unit Architecture 2 Multipliers 2 ALUs 1 set of Video ALUs 1 Shifter Register File

8 Jan 28, 2004Blackfin Compute Unit REV B Register File 8 x 32 bit OR 16 x 16 bit 2 x 40 bit accumulators DATA REGISTER SYNTAX: R0, R1 etc refer to 32 bit registers R0.L refers to the low 16 bits of the R0 32 bit reg R0.H refers to the high 16 bits of the R0 register ACCUMULATOR SYNTAX: A0.L => low 16 bits A0.H => next 16 bits A0.W => least significant 32 bit word A0.X => MS 8 bit extension SHARC – bit data registers, integer and float There is a pair of SHARC accumulator registers too

9 Jan 28, 2004Blackfin Compute Unit REV B ALU Data Flow 2 x 32 bit paths to dual Multiplier/ALU units 2 x 32 bit paths back to register file

10 Jan 28, 2004Blackfin Compute Unit REV B Sample instructions Blackfin R0 = R1 + R2; R0.L = R1.L + R2.H; R0 = R1 +|- R2; Means R0.L = R1.L – R2.L in parallel with R0.H = R1.H + R2.H SHARC R0 = R1 + R2; Closest R0 = R1 + R2, R4 = R1 – R2; 68K MOVE.L R2, R0 ADD.L R1, R0 MOVE.W R2, R0 ADD.W R1, R0 MOVE.L R2, R0 ASR.L #16, R0 MOVE.L R1, R3 ASR.L #16, R3 ADD.W R3, R0 ASL.L #16, R0 MOVE.W R2, R0 ADD.W R1, R0

11 Jan 28, 2004Blackfin Compute Unit REV B ALU Features Dual 16 bit OPS: Can be : Single 16 bit OPS: Single 32 bit OPS: 31 Rm Rp Rn Rm Rp Rn Dual 16 bit Cross:

12 Jan 28, 2004Blackfin Compute Unit REV B ALU Sample Instructions Single 16 bit ops:Dual 16 bit ops: Quad 16 bit ops: ABABDC Single 32 bit ops: Dual 32 bit ops: A & B registers must stay on the same side of the ‘|’ for both Instructions For dual and quad 16 bit operations the (CO) option causes the destination registers to cross Operator order is important + must come before - Does not work in parallel Must have this option

13 Jan 28, 2004Blackfin Compute Unit REV B Multiply Data Flow 2 x 32 bit paths to dual Multiplier/ALU units 2 x 32 bit paths back to register file 2 x 40 bit accumulator Multiplier share the same operand/result buses as the ALU

14 Jan 28, 2004Blackfin Compute Unit REV B Multiply Features HH HL LH LL Multiplies are signed fractional by default Signed fractional multiply result is automatically left shifted 1 bit. Signed fractional multiply != signed integer multiply Rounding available on fractional number multiplies and special option of integer number multiplies

15 Jan 28, 2004Blackfin Compute Unit REV B Rounding 2 cases: 0x Rd top 16 bits go to destination register 31 Rm 31 Rp 0x Rd top 16 bits go to destination register 32 bit result Rounding adds 0x8000 to the 32 bit multiplier result or accumulator value before extracting a 16 bit value to the destination register

16 Jan 28, 2004Blackfin Compute Unit REV B Fractional Multiply When extracting a 16 bit fractional value from an accumulator the high 16 bits is taken Where in the destination register it goes depends on which accumulator is being extracted from Fractional Multiply != Integer Multiply Fractional Multiply != Integer Multiply

17 Jan 28, 2004Blackfin Compute Unit REV B Integer Multiply When extracting a 16 bit integer value from an accumulator the low 16 bits is taken. Where in the destination register the 16 bit value goes depends on which accumulator is being extracted from Fractional Multiply != Integer Multiply

18 Jan 28, 2004Blackfin Compute Unit REV B Multiply Sample Instructions 16 bit extraction from ACC 016 bit extraction from ACC 1 32 bit extraction A1 += R1.H * R2.L, A0 += R1.L * R2.L; R3.H = (A1 += R1.H * R2.L), R3.L = (A0 += R1.L * R2.L); Any combination of.H and.L in the 2 operands is allowed R3 = (A1 += R1.H*R2.L), R2 = (A0 += R1.L * R2.L); Where destination registers must be paired as follows: R[1,0], R[3,2], R[5,4] and R[7,6] R3.H = (A1 += R1.H * R2.L), A0 += R1.L * R2.L; Multi-issue MAC Instruction Examples

19 Jan 28, 2004Blackfin Compute Unit REV B Shifter Sample Instructions 2 operator Register shifts 2 operator Immediate shifts 3 op Reg shift 3 op Immediate shift Arithmetic shift

20 Jan 28, 2004Blackfin Compute Unit REV B Parallel Instruction Examples In general there are 16 and 32 bit versions of the arithmetic instructions Most of the 32 bit instructions can be executed in parallel with 2 x 16 bit memory/index operations Exceptions are DIVS, DIVQ and MULTIPLY with 32 bit operands || means parallel Examples: –A1=R2.L*R1.L,A0=R2.H*R1.H||R2.H=W[I2++] || [I3++]=R3;\ –R2=R2+|+R4, R4=R2-|-R4 || I0+=M0||R1=[I0];


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