Presentation on theme: "Subject Code : 3330705 Name Of Subject : Microprocessor and assembly language programming Name of Unit : Instruction cycle and Timing diagram Topic : Instruction."— Presentation transcript:
Subject Code : 3330705 Name Of Subject : Microprocessor and assembly language programming Name of Unit : Instruction cycle and Timing diagram Topic : Instruction cycle Name of Faculty : H.M.Avaiya & N.D.Dhameliya Name of Students: (i) SAINI SHIVANISINGH J(091) (ii) PANDYA DHVANIBEN D(092)
The microprocessor primarily performs four operations as listed below: 1.Memory read-to read data from memory 2.Memory write-to write data into memory 3.I/O read-to take data from input device 4.I/O write-to send data from output device
Example:- Let us consider the timing and execution of MOV A, B instruction stored in the program memory. This example is for 1 bit instruction. op code fetch Memory locationInstructionMachine code 2000hMOV A, B78h
In this opcode fetch four T-state are used. T-state:- each operation of the microprocessor is performed in synchronization with the internal clock. One clock pulse is called T-state. ALE: It stands for Address Latch Enable. when it is high it indicates address and when it is low it indicates data and opcode.
A8-A15: It indicates higher order address. In this cross is indicates the muitibit line is given. In this example higher order address is 20h. AD7-ADO: It is the multiple line to data/add line. so for this example ooh is the lower order address and 78h is op code. IO/M: In op code fetch IO/M is IO/M=0 S1=1 S2=2
Example: Let us consider the timing and execution of MVI A, FFh instruction stored in program memory. When 2 byte instruction is given draw op code fetch and memory read together. Memory locationInstructionMachine code 2000h 2001h MVI A, FFh3Eh FFh
Memory read AND memory write: In memory read cycle store the data from memory. MEMR signal enable the memory device for read operation. The memory write operation is also very similar to memory read operation except it uses WR signal to generate MEMW signal as shown in figures.