Presentation on theme: "End of First Semester Presentation DigiSat Reliable Computer – Multiprocessor Control System. Niv Best, Shai Israeli Instructor: Oren Kerem HS-DS Lab,"— Presentation transcript:
End of First Semester Presentation DigiSat Reliable Computer – Multiprocessor Control System. Niv Best, Shai Israeli Instructor: Oren Kerem HS-DS Lab, Technion, Winter 2003 This presentation will probably involve audience discussion, which will create action items. Use PowerPoint to keep track of these action items during your presentation In Slide Show, click on the right mouse button Select “Meeting Minder” Select the “Action Items” tab Type in action items as they come up Click OK to dismiss this box This will automatically create an Action Item slide at the end of your presentation with your points entered.
Project Goals Design & implement a hardware mechanism for multiprocessor monitoring & control. Part of the DigiSat reliable computer project.
The DigiSat Computer PowerPC based. Implemented upon the Virtex II-pro platform. Hardware redundancy throughout the entire system. Our project handles processor redundancy & control.
Description Satellites contain redundant hardware since servicing in space is not applicable. A monitoring system is required to identify & handle malfunctions. Must be implemented in hardware.
Current Status Simulated a PowerPC system using ModelSim 5_6d. Built autonomic monitoring sub-systems that survey PowerPC hardware outputs. Studied Assembler programming of the PowerPC. Built state-machine for controller.
Reset Requests Monitor Monitored signals: 1. Chip reset request (c405rstchipresetreq) 2. Core reset request (c405rstcoreresetreq) 3. System reset request (c405rstsysresetreq) If asserted, the required reset action is performed. Processors switch upon core reset request.
Timer Reset Monitor Monitored signal: c405cpmtimerresetreq The signal is the logical “OR” of the reset request signals. Serves as another way for resetting the system. Monitored along with the regular reset request signals – checks the watchdog functionality.
Bus Error Monitor PPC core & PLB are “tightly coupled”. Monitored signal: bus_error_det Asserted when a bus error interrupt occurs. Implies an error has occurred within the PLB arbiter. Preliminary inspection of the PLB arbiter.
Schedule Find a way to initiate CoreReset on PPC. (3 weeks) Find more ways to monitor the PPC. (5 weeks) Write WatchDog software to check internal parts of PPC. (8 weeks) Download hardware to chip and run tests on single PPC. (11 weeks) Wait for chip with dual cores. (T.B.D)