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Digital Correlator Design Using Vertex-2 FPGAs Zuo Yingxi Yao Qijun Lin Zhenhui Purple Mountain Observatory Nanjing 210008, Chian Yx.zuo@mwlab.pmo.ac.cn Nov.4, 2003

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Outline u Brief Review of Digital Correlators u Principle & General Structure of a 2-Bit Digital Correlator u Vertex-2 Series FPGAs u Design & Implementation u Experiment u Conclusion

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A Brief Review of Digital Correlators u Application: – Single-dish telescope » Sample & Quantize IF Signal » Calculate Rxx » FFT → spectrum – Array, VLBI » Sample IF outputs from 2 telescopes → calculate Cross- correlation Rxy – Mm-wave VLBI correlator requirement » Broad band u 2 Types – XF – FX u 2-bits vs. 1-bit quantization efficiency (affecting SNR) 1-bit (two-level) quantization Sampling at Nyquist rate 0.64 at 2× Nyquist rate 0.74 2-bit (four-level) quantization Sampling at Nyquist rate 0.87 So 2-bit quantization is more efficient, specially for VLBI

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Brief Review of Current Digital Correlators u Haystack CMOS Correlator u GBT 256K Spectrometer u COBRA Correlator System u Digital Spectrometer for Nobeyama 45-m Telescope u S500C128A Digital Correlator Chip from Spaceborne Inc. u UWBC (Ultra-Wide Band Correlator) for NMA u ACSIS (Auto-Correlation Spectrometer and Image System) at JCMT u ALMA Baseline Correlator

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Haystack CMOS Correlator u Complex or real cross/auto correlation surported u Up to 64 MSPS sampling rate u 2-bit, 4-level arithmetic surported u 512 lags, with many configuration options u 24-bit accumulator stages u Fully cascadable u Integration can continue while data is output u CMOS compatible I/O u 4 input channels, can handle demultiplexd data u Applications: – The SMA, The Westerbork Array, The NASA/MIT MKIV VLBI processor, The Joint European VLBI processor u Report Date: Sep. 15,1998

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GBT 256K Spectrometer u Up to 800MHz Bandwidth (1.6-GSPS), down to 12.5MHz u Up to 16384 lags, 49KHz resolution at 800MHz u 3-level up to 800MHz, 9-level below 50MHz BW u Using “Quaint” correlator chips: – Cross/Auto Correlation surported – 1024 Lags – 100MSPS sampling rate – 3-level or 2-level – 33-bit accumulation stage for 3-level operation – 32-bit 3-state asynchronous output port – Data and control signals cascadable – Integration can continue while data is output – CMOS and TTL compatible inputs u Report Date: Feb. 13, 1995

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COBRA Correlator System u For the Millimeter-Wavelength Array (MWA) at Owens Valley Radio Observatory (OVRO) u Digitizer – 1GSPS sampling rate – 2-bit – Serial-to-parellel converter (1:8 @125MHz, or 1:16 @62.5MHz) u Correlation – Using FPGAs (Altera 100KA or 100KE) for calculating average cross-correlation – 62.5MHz clock – 10 FPGAs on a correlator card u DSP for real-time control and FFT u Report Date: 04/16/1996

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Digital Spectrometer for Nobeyama 45-m Telescope u For the 25-Beam Array Receiver System (BEARS) u Using A/D in a digital oscilloscope, 1GSPS, 2-bits u 1024-Lags autocorrelation (with 32 LSIs of 32 lags connected in cascades) u Report date: 2000

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S500C128A Digital Correlator Chip from Spaceborne Inc. u 500MHz effective signal bandwidth u 500HMz clock frequency u 2-bit, 4-levels u 128 Lags/chip u 22s Max. integration time u 100us Min. readout time u TTL level for computer interface u Differential ECL I/O for clock and digital data u Single 3.3V power supply u Fully cascadable u S500S1024 available u Application: JPL Digital Autocorrelator Spectrometer u Report date: April 2000

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UWBC (Ultra-Wide Band Correlator) for NMA u 2 GSPS sampling rate (1024-MHz BW) u 2-Bits, 4-levels A/D, ECL output u With 1:64 demultiplexer, 2GHz/64=32MHz u Using a simple “bit-match” method to calculate 2-bit cross-correlation u Special-purpose LSI (UWBC2) operating at 32 MHz u Integration time from 0.1s up to 1.0s with 24-bits acuumulator u 256 Lags u Application: for Nobeyama Millimeter Array (NMA) u Report Date: 2000

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ACSIS (Auto-Correlation Spectrometer and Image System) at JCMT u A/D – 2 GSPS – 2-bit, 3-level u Correlator – Using “Quaint” Correlator chips – Consists of 32 correlation modules. On each module are 32 “Quaint” ICs – Simmilar to the NRAO/GBT correlator u It is currently in the design and development stage (by 3 Jan. 2002)

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ALMA Baseline Correlator u A/D – 4-GHz sampling rate, 2-GHz BW – 3-bit, 8-levels – Transmittied over fiber optic cables to the correlator – Use FIR filter and then form 2-bit 4-levels u Correlator: 2-bit, 4-levels u Schedule – The minimally populated correlator will be complete by April 2002 – Will be working in the lab by the end of 2002 – Will be delivered to the VLA site in May 2003

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Characteristics of the above correlators u High sampling rate u Using 2-bit ADC u Ultra-high speed sampling; Serial-to-parellel converting; Relative low correlation speed u ASICs; General programmable logic devices u More lags u Hybrid design u Cross- & auto-correlation

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Principle & General Structure of a 2-Bit Digital Correlator u General Structure From Rx.1 IF From Rx.2 IF

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Parellel correlation arithmetic and diagram (1) After 1:4 serial-to-parellel converting ， i= 0, 1, 2, …, 4N-1 n= 0, 1, 2, …, N-1 Sampling two input signals X(t) and Y(t) ，

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Arithmetic of the parellel correlation and the diagram (2) j = 0, 1, 2, …, M-1

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Parellel- correlation diagram

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Vertex-2 series FPGA (Field Programmable Gate Array) u Wide-band digital correlator needs high-speed & large- scale logical devices u FPGAs advantages – Very large-sacle IC, up to 10 million gates in one chip – Very high speed, up to 410MHz – Rapid time-to-production » Design with an FPGA is just “configuration” – High reliability » Chip’s quality garranted by producer » Verified by many other apllications

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Vertex- Ⅱ series FPGA

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Design & Implementation Using “design entry” of Xilinx F4.1i software u Using Xilinx F4.1i software u XC2V2000 u XC2V2000 FPGA chip as the target device (2 million gates) u Goal: 64 Lags, 250MHz clock rate u Schematic diagram – Top-level schematic – Control module – 4-Lag correlation module for 4-parellel inputs – Elementary 1-Lag correlation

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Top-level Schematic Using “design entry” of Xilinx F4.1i software

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Control module

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4-Lag correlation module for 4-parellel input

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Elementary 1-Lag Correlation

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Implementation u Map report: – Target Device : x2v2000 – Number of Slices: 5,505 out of 10,752 51% – Number of Slice Flip Flops: 8,702 out of 21,504 40% – Total Number 4 input LUTs: 4,402 out of 21,504 20% – Number of bonded IOBs: 105 out of 408 25% – Number of Tbufs: 2,176 out of 5,376 40% u Timing report: – NET "CLK" PERIOD = 4 nS ( constraint) ; – 10923 items analyzed, 0 timing errors detected. – Minimum period is 3.909ns.

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Simulation (1)

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Simulation (2)

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Simulation Results u Correct u Meet the design goal – 64 lags – 250 MHz clock rate u Equivalent input signal can be up to 500 MHz (Due to the parellel correlation scheme)

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Experiment Based on V2LC1000 Demo Board The Demo Board – XC2V1000 – XC2V1000 FPGA chip – PROM memory chip – 100MHz/24MHz clock – JTAG download connector and cable – DDR memory chip – RS232 connector – User I/O connectors – Voltage generators

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Experiment u To achieve 32-lag auto-correlation u Using the on-board 100MHz clock u Input signal generated by the same FPGA chip u Controlled by a PC – Set the integration time – Read the correlation results – Via printer port

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Experiment --- the input signal u Assuming an input signal as Quantized by a 2-bit ADC, achieve a 2-bit series (3, 3, 0, 1, 0, 2, 0, 0, 3, 3, 1, 1, 2, 3, 2, 0, 2, 2, 1, 1), … further through a 1:4 demultiplexer, obtain a 8-bit series (79, 8, 95, 46, 90), … This signal generator was implemented in the same FPGA

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Slightly revised Top-level Schematic

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Experiment --- result SIMCALMEASIMCALMEA Simulation is performed by Xilinx F4.1i software Experiment result agree well with the simulation & calculation result

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Experiment --- result Measureed auto-correlation function Red line ---measured data Blue line ---calculated from the unquantized input signal Power spectrum obtained by FFT Red line ---from the measured data Blue line ---calculated from the unquantized input signal

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Conclusion u A 64-Lag correlator design and simulation With XC2V2000 (2M-gate FPGA chip), fully cascadeble to achieve more lags. u Speed meets the design requirement (250MHz verified by timing simulation, 100MHz verified by experiment). Results are correct. u It is a efficient method (saving circuit resources) to use only 1 accumulator for 4-parellel inputs correlation. u Speed requirement of the device for correlating operation decreased (input bandwidth of the overall correlator increased) by serial-to-parellel converting. u Sampling rate can be up to 1-GSPS (input bandwidth up to 500MHz) With this correlation module. u A 32-lag auto-correlator experiment has been performed.

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Thanks Zuo Yingxi Yao Qijun Lin Zhenhui Purple Mountain Observatory Nanjing 210008, Chian

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