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CS6290 Tomasulo’s Algorithm

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Implementing Dynamic Scheduling Tomasulo’s Algorithm –Used in IBM 360/91 (in the 60s) –Tracks when operands are available to satisfy data dependences –Removes name dependences through register renaming –Very similar to what is used today Almost all modern high-performance processors use a derivative of Tomasulo’s… much of the terminology survives to today.

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Tomasulo’s Algorithm: The Picture

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Issue (1) –Get next instruction from instruction queue. –Find a free reservation station for it (if none are free, stall until one is) –Read operands that are in the registers –If the operand is not in the register, find which reservation station will produce it –In effect, this step renames registers (reservation station IDs are “temporary” names)

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Issue (2) F1 = F2 + F3 F4 = F1 – F2 F1 = F2 / F3 Instruction Buffers F2=F4+F1 AdderFP-Cmplx A1 (1) A2 (2) A3 (3) C1 (4) C2 (5) F1 F2 F3 F4 RAT F1 F2 F3 F4 Reg File To-Do list (from last slide): Get next inst from IB’s Find free reservation station Read operands from RF Record source of other operands Update source mapping (RAT) To-Do list (from last slide): Get next inst from IB’s Find free reservation station Read operands from RF Record source of other operands Update source mapping (RAT)

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Execute (1) –Monitor results as they are produced –Put a result into all reservation stations waiting for it (missing source operand) –When all operands available for an instruction, it is ready (we can actually execute it) –Several ready instrs for one functional unit? Pick one. Except for load/store Load/Store must be done in the proper order to avoid hazards through memory (more loads/stores this in a later lecture)

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Execute (2) F4=F1-F2 F1=F2+F3 F1=F2/F3 AdderFP-Cmplx A1 (1) A2 (2) A3 (3) C1 (4) C2 (5) (4)(1) To-Do list (from last slide): Monitor results from ALUs Capture matching operands Compete for ALUs To-Do list (from last slide): Monitor results from ALUs Capture matching operands Compete for ALUs (1) F2=F4+F1 (1)

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Execute (3) More than one ready inst for the same unit F4=F3-F2 F1=F2+F3 F1=F2/F3 AdderFP-Cmplx A1 (1) A2 (2) A3 (3) C1 (4) C2 (5) (1) (1) F2=F4+F1 (1) Common heuristic: oldest first Optimal is impossible: Precedence constrained scheduling problem is NP-complete [GJ,p239] … and that assumes you have access to the entire graph You can do whatever: it only affects performance, not correctness

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Write Result (1) –When result is computed, make it available on the “common data bus” (CDB), where waiting reservation stations can pick it up –Stores write to memory –Result stored in the register file –This step frees the reservation station –For our register renaming, this recycles the temporary name (future instructions can again find the value in the actual register, until it is renamed again)

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Write Result (2) F4=F1-F2 F1=F2+F3 F1=F2/F3 AdderFP-Cmplx A1 (1) A2 (2) A3 (3) C1 (4) C2 (5) (4) To-Do list (from last slide): Broadcast on CDB Writeback to RF Update Mapping Free reservation station To-Do list (from last slide): Broadcast on CDB Writeback to RF Update Mapping Free reservation station F1 F2 F3 F4 Reg File F1 F2 F3 F4 RAT (1) F2=F4+F (1) F1 = F2 + F3 F4 = F1 – F2 F1 = F2 / F F2 = F4 + F Only update RAT (and RF) if RAT still contains your mapping! Only update RAT (and RF) if RAT still contains your mapping! X

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Tomasulo’s Algorithm: Load/Store The reservation stations take care of dependences through registers. Dependences also possible through memory –Loads and stores not reordered in original IBM 360 –We’ll talk about how to do load-store reordering later

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F2 Is ExW BusyOpVjVkQjQkA Reservation Stations … F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 1 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Assume R2 is 100 R3 is 200 F4 is 2.5

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F2 1 Is ExW 1L.D134 BusyOpVjVkQjQkA Reservation Stations LD1… F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 2 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Assume R2 is 100 R3 is 200 F4 is 2.5

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F2 1 4 Is ExW 1L.D134 1L.D245 BusyOpVjVkQjQkA Reservation Stations LD2LD1… F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 3 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles 2 Assume R2 is 100 R3 is 200 F4 is 2.5

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F2 1 2 Is ExW 1L.D134 1L.D245 1MUL.D2.5LD2 BusyOpVjVkQjQkA Reservation Stations ML1LD2LD1… F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 4 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles 2 3 Assume R2 is 100 R3 is 200 F4 is 2.5 3

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F Is ExW 0 1L.D245 1SUB.D0.5LD2 1MUL.D2.5LD2 BusyOpVjVkQjQkA Reservation Stations ML1LD2AD1… F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 5 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Assume R2 is 100 R3 is 200 F4 is 2.5 3

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F Is ExW 0 0 1SUB.D MUL.D DIV.D0.5ML1 BusyOpVjVkQjQkA Reservation Stations ML1AD1ML2… F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 6 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Assume R2 is 100 R3 is 200 F4 is

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F Is ExW 0 0 1SUB.D ADD.D2.5AD1 1MUL.D DIV.D0.5ML1 BusyOpVjVkQjQkA Reservation Stations ML1AD2AD1ML2… F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 8 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Assume R2 is 100 R3 is 200 F4 is

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F Is ExW ADD.D MUL.D DIV.D0.5ML1 BusyOpVjVkQjQkA Reservation Stations ML1AD2ML2… F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 9 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Assume R2 is 100 R3 is 200 F4 is

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F Is ExW ADD.D MUL.D DIV.D0.5ML1 BusyOpVjVkQjQkA Reservation Stations ML1AD2ML2… F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 11 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Assume R2 is 100 R3 is 200 F4 is

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F Is ExW MUL.D DIV.D0.5ML1 BusyOpVjVkQjQkA Reservation Stations ML1ML2… F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 16 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Assume R2 is 100 R3 is 200 F4 is

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F Is ExW DIV.D BusyOpVjVkQjQkA Reservation Stations ML2… F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 17 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Assume R2 is 100 R3 is 200 F4 is

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F Is ExW DIV.D BusyOpVjVkQjQkA Reservation Stations ML2… F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 18 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Assume R2 is 100 R3 is 200 F4 is

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Detailed Example 1. L.DF6, 34(R2) 2. L.DF2, 45(R3) 3. MUL.DF0, F2, F4 4. SUB.DF8, F2, F6 5. DIV.DF10,F0,F6 6. ADD.DF6, F8, F Is ExW DIV.D BusyOpVjVkQjQkA Reservation Stations ML2… F0F2F4F6F8F10F12 Register Status: LD1 LD2 AD1 AD2 AD3 ML1 ML2 57 Cycle: Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Assume R2 is 100 R3 is 200 F4 is

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Timing Example Kind of hard to keep track with previous table-based approach Simplified version to track timing only F6,34(R2)124L.D OperandsIsExecWrCommentsInst F2, 45(R3)235L.D F0,F2,F43616MUL.D F8,F2,F6468SUB.D F10,F0,F651757DIV.D F6,F8,F26911ADD.D Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles Load: 2 cycles Add: 2 cycles Mult: 10 cycles Divide: 40 cycles

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