Presentation is loading. Please wait.

Presentation is loading. Please wait.

Wojciech Dulinski BNL/IReS/LEPSI STAR Video Conference, 5.02.2004 1 MIMOSA9 tracker test chip submission Goals: design optimization.

Similar presentations


Presentation on theme: "Wojciech Dulinski BNL/IReS/LEPSI STAR Video Conference, 5.02.2004 1 MIMOSA9 tracker test chip submission Goals: design optimization."— Presentation transcript:

1 Wojciech Dulinski BNL/IReS/LEPSI STAR Video Conference, MIMOSA9 tracker test chip submission Goals: design optimization for STAR microvertex application 1. Exploration of (new) fabrication process 2. Test of a new readout architecture Status: submitted 26 of January 04 expected in April 04 tests (including beam tests) in May-July 04

2 Wojciech Dulinski BNL/IReS/LEPSI STAR Video Conference, AMS 0.35 µm CMOS OPTO process - Advanced mixed-signal polycide gate CMOS: 4 metal, 2 poly, high-resistive poly, 3.3V and 5V gates - Optimized N-well diode leakage current: <45 pA/mm 2 (cm 2 °C - 20 µm epi substrate (samples on non-epi high resistivity substrate also available) - Availability in multiproject submissions in 2004, with a reasonable pricing

3 Wojciech Dulinski BNL/IReS/LEPSI STAR Video Conference, MIMOSA9: 4 “standard” arrays for tracking performance study and 5 test arrays with a new readout scheme (analog CDS on pixel) Dimensions: 4.1x4.3 mm 2 Array#0 Array#1 Array#3 Array#2 Test arrays (on pixel CDS)

4 Wojciech Dulinski BNL/IReS/LEPSI STAR Video Conference, vdd select reset vdd gnd output vdd select vdd gnd output 3 transistor pixel cell Self-biased pixel cell TypeDimensionPitchN-well diode size Array#0SB64x6420µm4.3x3.4, 6x6 Array#13T32x3240µm3.4x3.4*, 6x6 Array#2SB32x3230µm4.3x3.4, 5x5 Array#3SB32x3240µm4.3x3.4, 6x6 Mimosa9: arrays for tracking study * “thin oxide diode” P++ N++ N-WELL POLY P-WELL LOCOS M1 plate

5 Wojciech Dulinski BNL/IReS/LEPSI STAR Video Conference, Analog CDS on pixel: possible way to limit the integration time, effective use of a trigger) gnd output1 vbias S2 S1 Cs2 pwr_on output2 Read1 Read2 Cs1 AVDD x(5-10) - Slow integration clock (1MHz  640 µs integration time): low dissipation, comfortable stabilisation time of the on-pixel amplifier after Power_On - Readout of all pixels after trigger only: no need for perfect internal readout chain compensation - External compensation, global correction (common mode) possible: limited risk for experimental “unknown” factors - Lower signal amplitude dispersion: less power, smaller digitisation precision required (~8bits) Five different pixel arrays tested on Mimosa9 (array size 22x4 pixels for a pitch of 30µm) output1 output2 Out BUF


Download ppt "Wojciech Dulinski BNL/IReS/LEPSI STAR Video Conference, 5.02.2004 1 MIMOSA9 tracker test chip submission Goals: design optimization."

Similar presentations


Ads by Google