Download presentation

Presentation is loading. Please wait.

Published byRobyn Bride Modified over 2 years ago

1
NextPrevious Main Objective: A comparison between single-edge-triggered Flip-Flop(SET FF) and double edge triggered Flip-Flop based Bit-serial adder in terms of power and speed.

2
NextPrevious Project states: Literature and investigations. Choosing a suitable DETFF. Bit serial adder circuit construction. Power preliminary comparisons. Comments & next steps.

3
NextPrevious Choosing a DET FF outb M2 M1 M3 M4 M5 M6 M11 M8 M7 M9 M10 M12 M16 M13 M14 M15 PLO NLO In SN/SP-BAL-CS Dynamic DET FF clk D QQ Static DET FF clk DA X Q

4
NextPrevious Conventional not-fully-pipelined bit-serial adder [1] A sum output every clock cycle [1]. Single edge triggered based activity. C n+1 1D C1 1D C1 1D C1 1D C1 CnCn C n+1 C7C7 C6C6 C3C3 C0C0 C5C5 C4C4 C1C1 C2C2 S3S3 S2S2 S1S1 S0S0 S7S7 S6S6 S5S5 S4S4 S b a b7b7 b2b2 b6b6 b1b1 b0b0 b5b5 b4b4 b3b3 a7a7 a6a6 a3a3 a2a2 a1a1 a0a0 a5a5 a4a4

5
NextPrevious b 3, b 2, b 1, b 0 Dual edge triggered FF-based bit-serial adder [2] Output every half clock cycle under a 50% duty cycle restriction. 4 Mux’s were added 1D C1 1D C1 0101 a 3, a 2, a 1, a 0 1D C1 1D C1 0101 1D C1 1D C1 1010 1D C1 1D C1 1010 o o o o ADD cy 1 [2]

6
NextPrevious Preliminary power comparison results Aggressive sizing is needed to push the speed of the FF and the circuit. Moving forward with the frequency is bounded by the adder circuit and the correct functionality of the DETFF. (I might need to switch to dynamic DETFF.) Low power will be the first priority. A repetitive architecture (parallelism=> f/4) could be a good approach to lower VDD while maintaining the same throughput. 194 uw 92 uw 116 uw

7
NextPrevious 1D C1 1D C1 1D C1 1D C1 1D C1 o o 1D C1 o o ADD a 3, a 2, a 1, a 0 b 3, b 2, b 1, b 0 cy cy 1 0 1 cy 1 cy 1D C1 1D C1 ADD

8
NextPrevious [1] J. Yuan and C. Svensson, “High-Speed CMOS Circuit Technique,” IEEE J. Solid-State Circuits, vol. 24, no.1, pp.62-70, Feb. 1989. [2] J. Yuan and C. Svensson, “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings,” IEEE J. Solid-State Circuits, vol. 32, no.1, pp.62-69, Jan. 1997. [3] W. M. Chung and M. Sachdev, “A Comparative Analysis of Dual Edge Triggered Flip-Flops,” [4] R.P. Llopis and M. Sachdev, “Low Power, Testable Dual Edge Triggered FlipFlops”, International on Low Power Electronics and Design, 1996, pp.341-5. [5] A.G.M. Strollo, E. Napoli, and C. Cimino, “Analysis of Power Dissipation in Double Edge-Triggered Flip-Flops,” IEE Trans. On VLSI Systems, Vol. 8, no.5, Oct. 2000. References

9
NextPreviousReferences [6] S.M.M. Mishra, S.S.Rofail and K.S.Yeo, “Design of High Performance [7] Double Edge-Triggered Flip-Flops,” IEEE Proc. Circuits Devices Syst., Vol.147, no.5, Oct. 2000. [8] Dual edge clocking schemes and alternate edge clocking J.Knight.

Similar presentations

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google