# Fall 2005 1 EE 333 Lillevik480f05-a3 University of Portland School of Engineering EE 333 Final Exam December 15, 2005 Instructions 1.Print your name, student.

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Fall 2005 2 EE 333 Lillevik480f05-a3 University of Portland School of Engineering Problem 1, (10 pts) 1.Convert hex 0xc4a to decimal? 2.Convert decimal 432 to hex? D = c x 16 2 + 4 x 16 1 + a x 16 0 = 12 x 256 + 4 x 16 + 10 x 1 = 3072 + 64 + 10 = 3164 H : 432/16 = 27, R =0 : 27/16 = 1, R =11 : 1--11-- 0 = 0x1B0

Fall 2005 3 EE 333 Lillevik480f05-a3 University of Portland School of Engineering MIPS machine language (decimal) You may also use the following pseudo-instructions: la rdest, address lb rt, address sb rt, address

Fall 2005 4 EE 333 Lillevik480f05-a3 University of Portland School of Engineering Problem 2, (10 pts) Find the machine instruction for sub \$10, \$6, \$16 0x 00d0 5022 R typeFields Size 6 bits5 bits 6 bits R typeoprsrtrdshamtfunct 00 00000 01101 00000 10100 000010 0010 sub rd, rs, rt

Fall 2005 5 EE 333 Lillevik480f05-a3 University of Portland School of Engineering Problem 3, (10 pts) probclocksns add0.242 sub0.1542 lw0.452.5 sw0.242 j0.0531.5 A.Assume F max = 2.0 GHz, complete the table (clocks, ns). B.Use the probability information to determine the average instruction time in ns. MIPS data path

Fall 2005 6 EE 333 Lillevik480f05-a3 University of Portland School of Engineering Problem 4, (10 pts) A 16-bit computer is built entirely from the 7400LS logic family. Use only the following information to find the maximum clock frequency for the ideal case. Show units. setup = 10ns, hold=5ns, propagation=20ns, gate delay =10ns

Fall 2005 7 EE 333 Lillevik480f05-a3 University of Portland School of Engineering Problem 5 (10 pts) Complete the 64x16 ROM design; fully decode for 0x00 start address.

Fall 2005 8 EE 333 Lillevik480f05-a3 University of Portland School of Engineering Problem 6 ( 10 pts ) Cache memory indexVMtagdata 000YY100x123 001NY110x456 010NN010x789 011YY000xabc 100YN010xdef 101YY110x123 110YY100x456 111NY000x789 CPU write adrhit?WB? 1 0001NN, invalid 1 1101YN 0 0011YN 0 0010NN 1 0000YN 0 1110NY 0 0000NY 0 1111NN, invalid For the direct mapped, write-back cache below, complete the table (Y or N)? WB = miss-modified

Fall 2005 9 EE 333 Lillevik480f05-a3 University of Portland School of Engineering Problem 7 (10 pts) Determine the speedup S of a pipelined CPU with p stages as the number of instructions becomes infinitely large? Series Parallel

Fall 2005 10 EE 333 Lillevik480f05-a3 University of Portland School of Engineering Problem 8 ( 10 pts ) A.What are the advantages of microprogramming? Solve large FSM problems Flexibility for changes Assembler can check for errors B.What are the general steps? edit source file assemble create µROM

Fall 2005 11 EE 333 Lillevik480f05-a3 University of Portland School of Engineering Problem 9 ( 10 pts ) MDP16 system trace

Fall 2005 12 EE 333 Lillevik480f05-a3 University of Portland School of Engineering Problem 9 ( 10 pts ), continued. 1.What machine instruction is executing at 6200 ns? 2.What is the optimistic branch address for the instruction executing at 7600 ns? 3.At 6800 ns, the instruction is a sw, what is the effective address? 4.At 8400 ns, the instruction is a sw, what is the data? 5.At 6000 ns, the instruction is an addi, what is the immediate data? 0xAC20 0x004A 0x0201 0x0095 0x0020

Fall 2005 13 EE 333 Lillevik480f05-a3 University of Portland School of Engineering Problem 10 (10 pts) Find an expression for the average access time T ave of a memory-hard disk hierarchy? Assume the page rate (hit) is p, memory access time is m, the I/O bus bandwidth is b, the size of a page is s bytes, a page is found dirty (modified) with probability d, and the free page list is always empty (memory full).

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