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Modeling with Constraint Logic Programming Ulf Nilsson Dept of Computer and Information Science Linköping University

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Representing DC Circuits r(R) R C1C2 ser(C1, C2) par(C1, C2) C1 C2 c(V) V

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Example V ser(c(9), par(r(10), r(5))) circuit(c(N)) :- {N>=0}. circuit(r(N)) :- {N>=0}. circuit(ser(C1, C2)) :- circuit(C1), circuit(C2). circuit(par(C1, C2)) :- circuit(C1), circuit(C2).

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Resistance % res(C, R) % Circuit C has resistance R res(c(V), 0) :- {V>=0}. res(r(R), R) :- {R>=0}. res(ser(C1, C2), R1+R2) :- res(C1, R1), res(C2, R2). res(par(C1, C2), R1*R2/(R1+R2)) :- res(C1, R1), res(C2, R2).

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Derivation =0, res(r(X),R2) | 10=R1+R2 > =0 > X=5

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Typical CLP program solve(Term) :- setup_constraints(Term), redundant_constraints(Term), solve_constraints.

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Language of CLP(B) zBoolean constants: 0 and 1 zParameters: X, Y,... zNegation: ~ zBinary connectives: *, +, #, =<, =:=,... zCardinality: card(Is, Es)

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CLP built-ins zsat(BOOLEXPR) The boolean expression is added to the constraint store if the store is still satisfiable ztaut(BOOLEXPR, TRUTHVAL) Succeeds if TRUTHVAL=1 and BOOLEXPR is entailed by the constraint store or if TRUTHVAL=0 and ~BOOLEXPR is entailed by the constraint store. zlabeling(VARLIST) Enumerates all bindings of the variables in VARLIST that satisfy the constraint store.

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Examples ?- sat(A+B), sat(~A). A=0, B=1 ?- sat(A*B), sat(~A). no ?- sat(A+B), sat(~A), taut(B, 1). A=0, B=1 ?- sat(A=:=B), labeling([A,B]). A=0, B=0 A=1, B=1

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Examples: Cardinality ?- sat(A+B), sat(card ([1], [A, B])). sat(A=\= B) ?- sat(A=**
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Circuit Verfication p-switch MOSn-switch MOS Source Drain Gate Drain Source nswitch(S, D, G) :- sat(D*G =:= G*S). pswitch(S, D, G) :- sat(D* ~G =:= ~G*S).

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Example ?- nswitch(S, D, G), labeling([S, D, G]). D = 0, G = 0, S = 0 D = 1, G = 0, S = 0 D = 0, G = 1, S = 0 D = 0, G = 0, S = 1 D = 1, G = 0, S = 1 D = 1, G = 1, S = 1

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Circuit verification (cont’d) 0 1 yx z tmp xor(X, Y, Z) :- pswitch(Tmp,1,X), nswitch(0, Tmp, X), pswitch(Z, X, Y), nswitch(Z, Tmp, Y), nswitch(Z, Y, Tmp), pswitch(Z, Y, X). 11 0

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Is It Really an XOR? ?- xor(X, Y, Z). sat(X=:=Y#Z) ?- xor(X,Y,Z), labeling([X, Y, Z]). X = 0, Y = 0, Z = 0 X = 1, Y = 0, Z = 1 X = 1, Y = 1, Z = 0 X = 0, Y = 1, Z = 1

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Testing vs Verification ?- xor(X, Y, Z), taut(Z=:=X#Y, 1). sat(X=:=Y#Z) Can we verify the circuit without testing it? Yes! Schematically: ?- sat(System), taut(Property, 1).

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Very Useful Theorem Property is entailed by System iff (System * ~Property) is unsatisfiable ?- xor(X, Y, Z), sat(~(Z=:=X#Y)). no

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