1. ADVANCE Multi-simulation Concepts John Colley 10 th November 2011 Southampton 1

2. Introduction Motivation Discrete Event Simulation Principles Single-thread/Multi-thread Implementations Co/Multi-simulation Principles – Two Simulators – More than Two Simulators Continuous Simulation Principles Hybrid Continuous/Discrete Multi-simulation Summary 2

3. Discrete Event Simulation: Motivation Dominant Verification Technology for Synchronous Digital Hardware and Systems on Chip – $300 million per year Market – Mature Tools (30 years of development) – High Price Tools ($30k per seat + maintenance) Single Kernel, Multi-Language Tools for Model Re-use – VHDL – SystemVerilog – SystemC (C++) – C 3

4. A A C C B B D D C1 C2 COMPONENT VIEW Components: A, B, C, D (processes) Connections: C1, C2 (unidirectional) Ports: IN OUT SIMULATOR API GetValue(port) HasChanged(port) SetValue(OUT port, val, delay) ScheduleEval(component, delay) Discrete Event Simulation 4

5. A A C C B B D D C1 C2 update list evaluation list t = 0 The Two-list Simulation Algorithm t = n 5

6. A A C C B B D D C1 C2 update list evaluation list t = 0 The Two-list Simulation Algorithm t = n Why not just have a single, time-ordered list? 6

7. A A C C B B D D C1 C2 update list evaluation list A B C D t = 0 Time Zero Initialisation: Evaluate all Components 7

8. A A C C B B D D C1 C2 update list evaluation list t = 0 Component evaluations call SetValue, ScheduleEval t = 20 C1 t = 30 C2 t = 30 ED t = 50 EC 8

9. A A C C B B D D C1 C2 update list evaluation list t = 0 Component evaluations call SetValue, ScheduleEval t = 20 C1 t = 30 C2 t = 30 ED t = 50 EC C : future eval D : future eval C : C2 new val A : C1 new val 9

10. A A C C B B D D C1 C2 update list evaluation list t = 0 Global Time is Advanced to t = 20 t = 20 C1 t = 30 C2 t = 30 ED t = 50 EC 10

11. A A C C B B D D C1 C2 update list evaluation list t = 0 Add to eval list each component on C1 fanout t = 20 C1 t = 30 C2 t = 30 ED t = 50 EC B D 11

12. A A C C B B D D C1 C2 update list evaluation list B calls ScheduleEval with delay 40 t = 20 C1 t = 30 C2 t = 30 ED t = 50 EC B D t = 60 EB 12

13. A A C C B B D D C1 C2 update list evaluation list Time advances to t = 30: two updates t = 20 C1 t = 30 C2 t = 30 ED t = 50 EC t = 60 EB 13

14. A A C C B B D D C1 C2 update list evaluation list Time advances to t = 30: two updates, one eval t = 30 C2 t = 30 ED t = 50 EC t = 60 EB D 14

15. A A C C B B D D C1 C2 update list evaluation list t = 30 C2 t = 30 ED t = 50 EC t = 60 EB Simple Algorithm, Complex Implementation for Performance 15

16. A A C C B B D D C1 C2 update list evaluation list t = 30 C2 t = 30 ED t = 50 EC t = 60 EB Simple Algorithm, Complex Implementation for Performance Why not just have a single, time-ordered list? RACE Why not just have a single, time-ordered list? RACE 16

17. A A C C B B D D C1 C2 update list evaluation list Simulating Models without Discrete Delays – Unit Delay EB C1 Each evaluate/update cycle advances time by one tick 17

18. A A C C B B D D C1 C2 The Simulation Testbench Primary inputs Primary outputs 18

19. A A C C B B D D C1 C2 The Simulation Testbench Primary inputs Primary outputs In principle, just another component using the API In practice, a complex model of the design environment: Constrained Random Test Generation Assertion Checking Functional Coverage Metrics In principle, just another component using the API In practice, a complex model of the design environment: Constrained Random Test Generation Assertion Checking Functional Coverage Metrics 19

20. A A C C B B D D C1 C2 Discrete Event Simulation Languages: Hierarchy 20

21. A A C C B B D D C1 C2 Discrete Event Simulation Languages: Hierarchy Hierarchy is flattened for simulation 21

22. Discrete Event Simulation Languages: Function There must be an Entry Point to implement the Eval API call Eval call must execute to completion – Method call – Actor Languages with Embedded Wait – Eval call must resume at the Wait Point – Implement as Finite State Machine Stored Current State represents the next Entry Point 22

23. A A C C B B D D C1 C2 update list evaluation list t = 0 A Concurrent Simulator Implementation? t = n 23

24. A A C C B B D D C1 C2 update list evaluation list t = 0 A Concurrent Simulator Implementation t = n A B C D EVAL Components in Parallel Atomic Insertion 24

25. A A C C B B D D C1 C2 update list evaluation list t = 0 A Concurrent Simulator Implementation t = n A B C D EVAL Components in Parallel Atomic Insertion Amdahl’s Law Revisited for Single Chip Systems Jo-Ann M. Paul and Brett H. Meyer, 2006 Amdahl’s Law Revisited for Single Chip Systems Jo-Ann M. Paul and Brett H. Meyer, 2006 25

26. Event-Driven vs Process-Driven Event-Driven – Single core, single process Process-Driven – Threads OpenMP – Portable – Optimised for multi-core Python Generators (coroutines) Single core only (SimPy) 26

27. A A C C B B D D C1 C2 update list evaluation list t = 0 What if Component D does not have a native implementation? t = n A B C D C3 27

28. A A C C B B D External Model D External Model C1 C2 update list evaluation list t = 0 Component D is simulated with a different Simulator: Co-Simulation t = n A B C D C3 28

29. A A C C B B D External Model D External Model C1 C2 Master/Slave Co-Simulation Master Simulator -Master Event Queue -Design Topology -Components -Connectors -Initiates the Slave and establishes Inter-Process Communication Master Simulator -Master Event Queue -Design Topology -Components -Connectors -Initiates the Slave and establishes Inter-Process Communication Slave Simulator -Slave Event Queue -Slave Component Slave Simulator -Slave Event Queue -Slave Component C3 29

30. A A C C B B D External Model D External Model C1 C2 Master/Slave Co-Simulation Co-Simulation -Initialise Master Simulator -Initialise Slave Simulator -Get time Ts of next event from Slave -Run Master until -Time = Ts OR -D sees change on C1 or C2 -Get time Tm of next event from Master -Tell Slave to run until -Time = Tm -B sees change on C3 Co-Simulation -Initialise Master Simulator -Initialise Slave Simulator -Get time Ts of next event from Slave -Run Master until -Time = Ts OR -D sees change on C1 or C2 -Get time Tm of next event from Master -Tell Slave to run until -Time = Tm -B sees change on C3 C3 30

31. A A C C B External Model B External Model D External Model D External Model C1 C2 What if B is represented by a 3 rd Simulator? Master Simulator -Initialise Master Simulator -Initialise Slave Simulator -Get time Ts of next event from Slave -Run Master until -Time = Ts OR -D sees change on C1 or C2 -Get time Tm of next event from Master -Tell Slave to run until -Time = Tm -B sees change on C3 Master Simulator -Initialise Master Simulator -Initialise Slave Simulator -Get time Ts of next event from Slave -Run Master until -Time = Ts OR -D sees change on C1 or C2 -Get time Tm of next event from Master -Tell Slave to run until -Time = Tm -B sees change on C3 C3 31

32. A A C C B External Model B External Model D External Model D External Model C1 C2 What if B is represented by a 3 rd Simulator? Master Simulator -Initialise Master Simulator -Initialise Slave Simulator -Get time Ts of next event from Slave -Run Master until -Time = Ts OR -D sees change on C1 or C2 -Get time Tm of next event from Master -Tell Slave to run until -Time = Tm -B sees change on C3 Master Simulator -Initialise Master Simulator -Initialise Slave Simulator -Get time Ts of next event from Slave -Run Master until -Time = Ts OR -D sees change on C1 or C2 -Get time Tm of next event from Master -Tell Slave to run until -Time = Tm -B sees change on C3 C3 Simulators run in Lock-Step Simulators run in Lock-Step 32

33. A A C C B B D External Model D External Model C1 C2 Two Simulators, Slave Evaluates much more slowly than Master and Slave can Backtrack Co-Simulation -Initialise Master Simulator -Initialise Slave Simulator -Run Slave -Run Master until D sees a change on C1 or C2 at time Tc -If Slave time Ts < Tc -Continue running Slave until Tc -Else -Slave backtracks to Tc -Slave accepts new input value Co-Simulation -Initialise Master Simulator -Initialise Slave Simulator -Run Slave -Run Master until D sees a change on C1 or C2 at time Tc -If Slave time Ts < Tc -Continue running Slave until Tc -Else -Slave backtracks to Tc -Slave accepts new input value C3 33

34. Continuous v Discrete Simulation Continuous Equation-based model cont01 Real x, y, z; equation x + y + z = 5.000; der(y) = x + 1.365; y = der(z) – 1.875; end cont01; Discrete Assignment-based always @ (posedge clk) begin x <= x + 1 y <= x - 1 end 34

35. Hybrid Modeling Continuous-time + Discrete-time Modeling – Modelica “when” model t03 Real x, y, z; equation x + y + z = 5; when sample(0, 1) then x = x + 1; y = delay(x – 1, 20); end when; end t03; 35

36. A A C C B External Model B External Model D External Model D External Model C1 C2 What if B is represented by a Continuous Simulator? Multi-Simulation -A, C in Master multi-sim environment -B in Continuous Simulator -Modelica -Simulink -D in 3 rd party Discrete Simulator -IN/OUT interfaces to B must be Discrete -Modelica when Multi-Simulation -A, C in Master multi-sim environment -B in Continuous Simulator -Modelica -Simulink -D in 3 rd party Discrete Simulator -IN/OUT interfaces to B must be Discrete -Modelica when C3 36

37. A A Multi-sim Architecture 37 Rodin Platform ProB Multi-Simulation Core 3 rd Party sim 3 rd Party sim 3 rd Party sim 3 rd Party sim... ADVANCE

38. Summary Discrete Event Simulation – Two-List Algorithm for Deterministic Execution – “Event-driven” or “Process-driven” – Hardware/Software Continuous Simulation – Modelica, Matlab/Simulink Co-Simulation/Multi-Simulation – Optimisations for 2 Simulators – More than 2 Simulators must run in Lock-Step – Hybrid Continous/Discrete Simulation Discrete Interfaces 38