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Principles of Computer Engineering: Lecture 9: Sequential Logic Circuits

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Introduction Digital Timing Circuits Sequential Logic Flip-Flops Traffic Light Problem Combinational Logic Required Summary

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Digital Timing Circuits (NE555) All sequential digital circuits require a master clock signal A “555” timer is often used for this purpose Need to design our timer to give a frequency of 0.5 Hz f = 1/(1.4RC) Given that C = 1 F What value for R = ? +5V

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Sequential Logic: State Machine Can construct a “state machine” using JK Flip Flops Can use combination logic to control state changes Simplest state machine is a counter (prebuilt JK FFs cascaded) We will use a 3-bit counter (000 111) 8-states

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Traffic Light Problem Red, amber and green, LEDs to indicate the traffic lights The LEDs are turned on by logic ‘0’ inverse logic (don’t use the Hex inverter package this time as logic simpler). In this way, the decoder can be designed using a maximum of just one 74LS00 quad NAND chip.

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Traffic Light Problem T/sQ0Q1Q2Q3 00000011 21000011 40100011 61100011 80010011 101010011 120110001 141110001 160001110 181001110 200101110 221101110 240011110 261011110 280111101 301111101 (Not) Red = ? (Not) Amber = ? (Not) Green = ?

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4 5 14 16 11 2 6 7 (Not) Red = (Not) Amber = (Not) Green = Combinational NAND Logic Required 8

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Summary Timing circuits required for sequential logic 555 timer often used for this purpose Traffic light problem requires sequential logic Simple to use a binary counter Combinational NAND logic required to drive LEDs Questions?

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Formal Report Semester 1 You are each required to submit a formal report based on one experiment, either; Exp 4: The Wheatstone Bridge OR Exp 7: Transformers and Power Supplies Details and guidelines on VLE please read! The report is due on Wednesday the 7 th of January 2015 to the Faculty Office T313 by 4:00pm You must submit your logbooks at the same time Report worth 20% of module Logbook worth 10% of module

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