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Grant Willson Department of Chemical Engineering Department of Chemistry The University of Texas Austin, Texas 78712 Dual.

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Presentation on theme: "Grant Willson Department of Chemical Engineering Department of Chemistry The University of Texas Austin, Texas 78712 Dual."— Presentation transcript:

1 Grant Willson Department of Chemical Engineering Department of Chemistry The University of Texas Austin, Texas Dual Damascene using Step and Flash Imprint Lithography

2 S-FIL fluid dispenser – 126 ink jet system Planarization layer Substrate Step 1: Dispense drops Step 2: Lower template and fill pattern Step 3: Polymerize S-FIL fluid with UV exposure Step 4: Separate template from substrate Template Substrate Template Step & Repeat or whole wafer imprint Substrate Planarization layer Photomask 6025 template, coated with release layer Step and Flash Imprint Lithography Template filling driven by capillary action – low imprint pressure and room temperature process Template

3 The First SFIL Tool “Step and Flash Imprint Lithography: A New Approach to High-Resolution Patterning,” Proc. SPIE (1999)

4 SFIL tool today Resolution: Sub-32 nanometer half pitch Alignment: < 10nm, 3 sigma (single point, X,Y) Automation: Fully automated wafer and mask loading Flexibility: 200mm and 300mm substrates (SEMI standard) Field size: 26mm x 32mm (step-and-scan compatible)

5 Resolution of Imprint Lithography 2nm Replication (Rogers et al, Illinois) 20nm Replication 25nm vias 22nm logic (M1) SFIL ~130 atoms wide

6 Imprints from the Imprio nm Logic 32nm half-pitch24nm half-pitch 32nm Metal 1 25nm Contacts 22nm half-pitch Thanks to Toshiba

7 38 nm HP Flash Memory Imprints Thanks to Samsung

8 Non-CMOS Applications Photonic Crystals Patterned Media 100nm 20 nm

9 Multitiered Templates Fabricated with alternating layers of ITO and PECVD Oxide S. Johnson, et.al. Microelectron. Eng. (2003) 67, 221 SFIL Imprint

10 Our Job! Moore You?

11 Egyptian Damascene

12 ATDF Dual Damascene Process resist etch stop substrate ILD initial stacktrench lithotrench etch resist ashBARC / resistvia litho via etchresist Ash plate CMP 23 unit process steps/layer = 184 steps for 8 layers of metal

13 Direct Etch or Direct Imprint Previous Metal Layer Dielectric Layer Sacrificial Imprint Material Imprint Template SIM Previous Metal Layer Imprint Template DPD Directly Patternable Dielectric SIM ProcessDPD Process

14 SIM Damascene Process M1 Copper Barrier # of process steps: 0 ◄ CVD ILD 1 2 SFIL IMPRINT PressFlashRelease ◄ Dispense SIM ◄ Cured SIM Multi-Tier Template 3

15 3 SIM Damascene Process M1 # of process steps: 4 Etch transfer 56 x – 64 = 120 steps Savings of 7 Barrier EtchCopper SeedCopper PlateCMP 8

16 BEOL Multilevel Imprint Cost Saving 20% overall wafer cost saving at 30 wph Cost analysis by Sergei V. Postnikov, Infineon Technologies; presented at Semicon Europa 2007, Stuttgart, Germany 20%

17 Lloyd Litt, et. Al NNT 08

18 Multi-level Templates Vias Lines 240 nm 360 nm 120 nm 125 nm FeaturesHeightCD 1 μm vias Vias Lines 125 nm 313 nm 50 nm 125 nm FeaturesHeightCD Courtesy of Toppan Photomask Courtesy of IMS Chips

19 Multi-Level S-FIL Test Vehicle M2 by SFIL M1 by Photolithography Test Structures Via chain

20 SIM Via Chain Structures 100nm vias100nm via100nm vias M2 by SFIL M1 by Photolithography Via chain

21 Pattern Transfer Demonstration Trench Descum N 2 /H 2 Trench Descum N 2 /H 2 Via Etch Ar/C 4 F 8 /N 2 Via Etch Ar/C 4 F 8 /N 2 SIM Material ILD Material

22 Pattern Transfer Demonstration Trench Etch CF 4 /C 4 F 8 /N 2 Trench Etch CF 4 /C 4 F 8 /N 2 Ash N 2 /H 2 Ash N 2 /H 2 Both Coral ® and Black Diamond ® were processed

23 Via Chain – 120 nm 1000 Contacts Yield statistics (6 valid and identical chains tested) Overall yield of 1000-contact chains with via CD 120 nm (nominal) / 115 nm (final) – 96.83% Individual contact yield – % Template CD = 120 nm Final CD = 115 nm Template CD = 120 nm Final CD = 115 nm Cu (M2) Coral Cu (M1) Ta

24 Directly Patternable Dielectric Previous Metal Layer Imprint Template DPD

25 DPD Property Requirements Property Viscosity Photocurable Cure shrinkage Dielectric Constant Thermal Stability Mechanical Properties CTE Water Sorption Requirement Less than 20 cP Chain reaction polymerization Less than 15%  ≤ 3 Less than 1% wt 400 o C Young’s Modulus ≥ 4 GPa Less than 30 ppm/ o C Less than 1% wt

26 Sol-gel Design/Formulation Sol-Gel H 2 O, H + Alkoxysilanes ultrasonication, vacuum

27 Sol-gel DPD Characterization Property Viscosity Acrlyate conversion Vertical shrinkage a Dielectric Constant Thermal Stability b Mechanical Properties c CTE Measurement 9-17 cP 1.2 J/cm 2 ~ 30%  ≤ ° C 3-7 GPa 23.4 ppm/ ° C a.Shrinkage is composite of UV cure bake at 300 °C b.Measured after bake at 350 °C. c.Measured by both nanoindentation and SAWS.  ? ?

28 Metal Patterns (via chains) in Sol-gel DPD Wires (M2) “Dummy“ metal fill Via chain

29 Sol-Gel DPD Integration Study Defect Sources M1 defects (not expected) Particle defects (expected) Imprint uniformity alignment template BEOL etch metal CMP

30 Sol-Gel Via Chain Yield 120nm Via Chains Poor Yield Cause of Failure Open at via bottom Courtesy of Brook Chao

31 POSS Design/Synthesis for DPD

32 POSS Characterization a.Measured after bake at 250 °C. b.Measured by both nanoindentation and SAWS. Property Viscosity Exposure UV shrinkage Thermal shrinkage a Dielectric Constant Thermal Stability a Mechanical Properties b CTE Measurement ~640 cP 89 mJ/cm 80% conv. 17 ± 4% 5 ± 3% o C 2-5 GPa ? 32 ppm/ o C 

33 Issue: inkjet requires  < 20 cP Solution: new viscous fluid dispense technology is being implemented Viscous Dispense System

34 POSS Design/Synthesis Polyhedral Oligomeric Silsesquioxane (POSS) Benzocyclobutane (BCB) (Meth)acrylate A B B A B B B A Hydrosilylation chemistry

35 Conclusions Multi-level S-FIL is a viable approach for Cu / low-k dual damascene processing SIM Process has been demonstrated by good electrical yield in various via and line test structures Implementation does not involve reliability testing Lower cost DPD Process is making progress Opportunity for materials design Some processing challenges remain Implementation of DPD requires reliability testing

36 Brook H. Chao, Frank Palmieri, Wei-Lun Jen, and D. Hale McMichael The University of Texas at Austin Jordan Owens, Rich Berger, Ken Sotoodeh, Bruce Wilks, Joseph Pham, Ronald Carpio, Ed LaBelle, and Jeff Wetzel Advanced Technology Development Facility, Inc. These people did the work These people paid for the work


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