Presentation is loading. Please wait.

Presentation is loading. Please wait.

Dual Damascene using Step and Flash Imprint Lithography

Similar presentations

Presentation on theme: "Dual Damascene using Step and Flash Imprint Lithography"— Presentation transcript:

1 Dual Damascene using Step and Flash Imprint Lithography
Grant Willson Department of Chemical Engineering Department of Chemistry The University of Texas Austin, Texas 78712

2 Step and Flash Imprint Lithography
Photomask 6025 template, coated with release layer S-FIL fluid dispenser – 126 ink jet system Template Step 1: Dispense drops Planarization layer Substrate Step 2: Lower template and fill pattern Template filling driven by capillary action – low imprint pressure and room temperature process Template Substrate Planarization layer Step 3: Polymerize S-FIL fluid with UV exposure So how does the technology work. Well before I go into the details of SFIL, lets talk about imprint technology in general. It had its genesis I suppose with the wax seals that the Chinese invested to authenticate documents, and the same thermoplastic process has been used in the past decade to make very high resolution lithography patterns – with Stephen Chou at Princeton leading the way. However, any thermal process is an absolute non starter in the CMOS industry since it makes accurate overlay impossible. The next alternative was to use a UV curable film spun onto the wafer, but now you have the challenge of moving a relative high viscosity material between the various patterns on the template, so Grant and SV came up with the idea of using a low viscosity monomer placed on the surface of the wafer. This slides shows a schematic animation of the SFIL process: Points to make – template is common with photolithography – smaller dimensions yes, but otherwise common to allow commercial supply – no membranes per previous NGL efforts - process leaves a very thin film which can be removed in an etch descum. ie the process is compatible with etch. Thus the upstream template and the down stream etch and compatible. Just replace the litho cell. - some application are whole wafer Planarization layer Substrate Step & Repeat or whole wafer imprint Step 4: Separate template from substrate Template Planarization layer Substrate

3 The First SFIL Tool “Step and Flash Imprint Lithography: A New Approach to High-Resolution Patterning,” Proc. SPIE (1999)

4 SFIL tool today Resolution has always been an attractive feature of imprint technologies. This is an example for 20nm L/S with essentially no LER at all. The great advantage of the SFIL technology is that the template controls the lithographic quality and you can afford to take a long time to make the template – using less sensitive resist etc to help the LER. We think 20nm is the table stakes for this business – and I will discuss this in more detail in a moment – but extensibility is also important – and the next image shows some university existence proof of just how far this can go. This image is the work of Prof Rogers at the Univ of Illinois and shows that an imprinted image can be made as small as 3nm – not perfect but the evidence of literally molecular dimension is shown. Finally the technology is capable of doing 3D printing and the last image shows an example of this – namely micro-lenses on the top of a CMOS camera chip. By molding the template to the exact prescription required, imprinting a suitable acrylate polymer – and then leaving the imprinted image on the wafer, gives a very effective set op lenses for this application. Resolution:  Sub-32 nanometer half pitch Alignment:  < 10nm, 3 sigma (single point, X,Y) Automation:  Fully automated wafer and mask loading Flexibility:   200mm and 300mm substrates (SEMI standard) Field size:   26mm x 32mm (step-and-scan compatible)

5 Resolution of Imprint Lithography
2nm Replication (Rogers et al, Illinois) SFIL 20nm Replication 25nm vias ~130 atoms wide 22nm logic (M1)

6 Imprints from the Imprio 250
32nm half-pitch 24nm half-pitch 22nm half-pitch Thanks to Toshiba 32nm Logic 32nm Metal 1 25nm Contacts

7 Flash Memory Imprints Thanks to Samsung
38 nm HP

8 Non-CMOS Applications
20 nm 100nm Patterned Media Photonic Crystals

9 Multitiered Templates
Fabricated with alternating layers of ITO and PECVD Oxide SFIL Imprint S. Johnson, Microelectron. Eng. (2003) 67, 221

10 Our Job! Moore You?

11 Egyptian Damascene

12 ATDF Dual Damascene Process
resist etch stop substrate ILD initial stack trench litho trench etch via litho BARC / resist resist ash plate via etch resist Ash 23 unit process steps/layer = 184 steps for 8 layers of metal CMP

13 Direct Etch or Direct Imprint
SIM Process DPD Process Imprint Template Previous Metal Layer Imprint Template DPD Sacrificial Imprint Material Directly Patternable Dielectric SIM Dielectric Layer Previous Metal Layer

14 SIM Damascene Process 1 3 2 ◄ Cured SIM ◄ Dispense SIM ◄ CVD ILD
Multi-Tier Template 1 3 2 # of process steps: SFIL IMPRINT Press Flash Release ◄ Cured SIM ◄ Dispense SIM ◄ CVD ILD Copper Barrier M1

15 SIM Damascene Process 5 4 6 8 7 3 x 8 64 184 – 64 = 120
# of process steps: x 8 64 Savings of 184 – 64 = 120 steps Copper Seed Copper Plate Barrier Etch Etch transfer CMP M1

16 BEOL Multilevel Imprint Cost Saving
20% 20% overall wafer cost saving at 30 wph Cost analysis by Sergei V. Postnikov, Infineon Technologies; presented at Semicon Europa 2007, Stuttgart, Germany

17 Lloyd Litt, et. Al NNT 08

18 Multi-level Templates
Vias Lines 240 nm 360 nm 120 nm 125 nm Features Height CD 1 μm vias Vias Lines 125 nm 313 nm 50 nm Features Height CD Courtesy of IMS Chips Courtesy of Toppan Photomask

19 Multi-Level S-FIL Test Vehicle
Via chain M1 by Photolithography M2 by SFIL Test Structures

20 SIM Via Chain Structures
M1 by Photolithography M2 by SFIL 100nm vias 100nm vias 100nm via

21 Pattern Transfer Demonstration
SIM Material Via Etch Ar/C4F8/N 2 ILD Material Trench Descum N2/H2

22 Pattern Transfer Demonstration
Trench Etch CF4/C4F8/N 2 Ash N2/H2 Both Coral® and Black Diamond® were processed

23 Via Chain – 120 nm 1000 Contacts Cu (M2) Coral Cu (M1) Ta Template CD = 120 nm Final CD = 115 nm Yield statistics (6 valid and identical chains tested) Overall yield of 1000-contact chains with via CD 120 nm (nominal) / 115 nm (final) – 96.83% Individual contact yield – %

24 Directly Patternable Dielectric
Imprint Template DPD Previous Metal Layer

25 DPD Property Requirements
Viscosity Photocurable Cure shrinkage Dielectric Constant Thermal Stability Mechanical Properties CTE Water Sorption Requirement Less than 20 cP Chain reaction polymerization Less than 15% e ≤ 3 Less than 1% wt 400oC Young’s Modulus ≥ 4 GPa Less than 30 ppm/oC Less than 1% wt

26 Sol-gel Design/Formulation
H2O, H+ ultrasonication, vacuum Alkoxysilanes Sol-Gel

27 Sol-gel DPD Characterization
Property Viscosity Acrlyate conversion Vertical shrinkage a Dielectric Constant Thermal Stability b Mechanical Properties c CTE Measurement 9-17 cP 1.2 J/cm2 ~ 30% e ≤ 2.3 364 °C 3-7 GPa 23.4 ppm/°C ? ? Shrinkage is composite of UV cure bake at 300 °C Measured after bake at 350 °C. Measured by both nanoindentation and SAWS.

28 Metal Patterns (via chains) in Sol-gel DPD
Wires (M2) “Dummy“ metal fill Via chain

29 Sol-Gel DPD Integration Study
BEOL etch metal CMP Imprint uniformity alignment template Defect Sources M1 defects (not expected) Particle defects (expected)

30 Sol-Gel Via Chain Yield
120nm Via Chains Poor Yield Courtesy of Brook Chao Cause of Failure Open at via bottom

31 POSS Design/Synthesis for DPD

32 POSS Characterization
Property Viscosity Exposure UV shrinkage Thermal shrinkage a Dielectric Constant Thermal Stability a Mechanical Properties b CTE Measurement ~640 cP 89 80% conv. 17 ± 4% 5 ± 3% 2.84 344 oC 2-5 GPa ? 32 ppm/oC Measured after bake at 250 °C. Measured by both nanoindentation and SAWS.

33 Viscous Dispense System
Issue: inkjet requires m < 20 cP Solution: new viscous fluid dispense technology is being implemented

34 POSS Design/Synthesis
Polyhedral Oligomeric Silsesquioxane (POSS) Benzocyclobutane (BCB) (Meth)acrylate A B Hydrosilylation chemistry

35 Conclusions Multi-level S-FIL is a viable approach for Cu / low-k dual damascene processing SIM Process has been demonstrated by good electrical yield in various via and line test structures Implementation does not involve reliability testing Lower cost DPD Process is making progress Opportunity for materials design Some processing challenges remain Implementation of DPD requires reliability testing

36 These people did the work
Brook H. Chao, Frank Palmieri, Wei-Lun Jen, and D. Hale McMichael The University of Texas at Austin Jordan Owens, Rich Berger, Ken Sotoodeh, Bruce Wilks, Joseph Pham, Ronald Carpio, Ed LaBelle, and Jeff Wetzel Advanced Technology Development Facility, Inc. These people paid for the work

Download ppt "Dual Damascene using Step and Flash Imprint Lithography"

Similar presentations

Ads by Google