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CH 4CH 3 Control CH 2CH 1 DATA A J4J3J2J1FrLnIn OUT CH 1CH 2Control InCH 3CH 4Control Out CDSCnv LnFr JCLKJ4J3J2J1 2 nd AIM (optional) PI-2110x Pattern.

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Presentation on theme: "CH 4CH 3 Control CH 2CH 1 DATA A J4J3J2J1FrLnIn OUT CH 1CH 2Control InCH 3CH 4Control Out CDSCnv LnFr JCLKJ4J3J2J1 2 nd AIM (optional) PI-2110x Pattern."— Presentation transcript:

1 CH 4CH 3 Control CH 2CH 1 DATA A J4J3J2J1FrLnIn OUT CH 1CH 2Control InCH 3CH 4Control Out CDSCnv LnFr JCLKJ4J3J2J1 2 nd AIM (optional) PI-2110x Pattern Card PI-41100 Timing and Control Card PI-3100 Acquisition Interface Module (AIM), Rear View PI-41110 Multiplexer Card PI-41000 Digital Acquisition Card

2 PI-3100 Acquisition Interface Module (AIM), Front View DUT PI-3150 PA 4S4PA 3S3PA 2S2PA 1S1 CDS Mon Vid Mon Conv Mon

3 AIM 4 AIM 1 AIM 2 AIM 3 AIM 4 Ch 1 Ch 2 Ch 3 Ch 4 Mux 1 DACQ 1 Chs. 5-16 Timing & Control Card 1 ABCD Mux 2 Timing & Control Card 2 ABCD AIM 1 AIM 2 AIM 3 Chs. 17 - 32 DACQ 2 (Arm Out) Timing Connections Control Cable

4 Pattern Card 16-1312-98-54-1 DACQ Slot 3 DataFLP FLPArm DACQ Slot 4 DataFLP FLPArm DACQ Slot 5 DataFLP FLPArm DACQ Slot 6 DataFLP FLPArm

5 Pixel Clk Frame Sync Line Sync Clk/Data Alignment At Front Panel Connector Data Pixel Clk* 4 ns Inside the PI-41000, the Pixel Clk is inverted and delayed by approx. 4 ns.


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