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ECE 238L Computer Logic Design Spring 2010 Lab -1 Introduction to Discrete Digital Logic 01/25/101

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2 Basic logic gates And Gate Or Gate Lecture Notes – Lab 1

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01/25/103 Inverter Elementary Theorem - Identity X*1 = X; X*0 = 0X + 1 = 1; X + 0 = X NAND Lecture Notes – Lab 1 Basic logic gates

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01/25/104 Lecture Notes – Lab 1 Other Theorem Commutative: x*y=y*x, x+y=y+x Associative: x*(y*z)=(x*y)*z x+(y+z)=(x+y)+z Distributive: x*(y+z)=x*y+x*z x+y*z=(x+y)*(x+z) Absorption: x+x*y=x x*(x+y)=x

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01/25/105 Lecture Notes – Lab 1 Other Theorem Combining: x*y+x*y'=x, (x+y)(x+y')=x DeMorgan's theorem:(x*y)'=x'+y' (x+y)'=x'+y' x+x'y=x+y x(x'+y)=xy Consensus: xy+yz+x'z=xy+x'z (x+y)(y+z)(x'+z)=(x+y)(x'+z)

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01/25/106 F3= (Y + Z') X + X'YZ=XY + XZ’ + X’YZ Design a circuit for the following function: F3=X'YZ+XY'Z'+XYZ'+XYZ=M 3 +M 4 +M 6 +M 7 F3 equals 1 when XY or XZ’ or X’YZ equals 1 Is it the simplist? Example 1 Lecture Notes – Lab 1 Note: every row of a truth table with a one in the output column is called a minterm

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01/25/107 K-maps Lecture Notes – Lab 1 The idea behind a Karnaugh Map (Karnaugh, 1953) is to draw an expression’s truth table as a matrix in such a way that each row and each column of the matrix puts the minterms that differ in the value of a single variable adjacent to each other. Basic Rules Every minterm must be inside at least one rectangle, but there must not be any zeros inside any rectangles. Every rectangle has to be as large as possible. Rectangles may wrap around to include cells in both the leftmost and rightmost columns. Likewise for the top and bottom rows. The number of minterms enclosed in a rectangle must be a power of two (1, 2, 4, 8, or 16 minterms for 4-variable maps).

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01/25/108 F3= YZ + XZ' Logic diagram Layout diagram - position on the breadboard Design an AND/OR circuit Lecture Notes – Lab 1

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01/25/109 Lecture Notes – Lab 1 Simplify the function F = A'B'D + BC'D + A'BC + ACD, and design a circuit for the simplified function using any 7400 logic you wish. Step 1: Draw the Truth Table Step 2: Simplify the Equation Step 3: Draw the logic diagram performing the Equation in Step 2 Step 4: Draw the corresponding layout diagram Step 5: Implement the circuit Lab 1 task:

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01/25/1010 Step 1: Truth Table corresponding to F = A'B'D + BC'D + A'BC + ACD ABCDF 00000 00011 00100 00111 01000 01011 01101 01111 10000 10010 10100 10111 11000 11011 11100 11111

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01/25/1011 Step 2: Simplify the Equation 1- Maps the TT to K-map 2- Simplify the boolean function 00011110 000110 010111 110110 100010 AB CD 00011110 000110 010111 110110 100010 AB CD BD A’D CD A’BC

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01/25/1012 Step 3: Draw the logic diagram F = A’BC + BD + CD + A’D Step 4: Draw the layout diagram Step 5: Implement the circuit

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