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CHAPTER 3 MEMORY MANAGEMENT PART 2 by U ğ ur Halıcı.

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Presentation on theme: "CHAPTER 3 MEMORY MANAGEMENT PART 2 by U ğ ur Halıcı."— Presentation transcript:

1 CHAPTER 3 MEMORY MANAGEMENT PART 2 by U ğ ur Halıcı

2 3.3 Paging Logical memory PAGE TABLE Physical memory pageframeAttributes 04 13 21 35 1 In paging, the OS divide the physical memory into frames which are blocks of small and fixed size

3 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 f1 P2 13 f2 P3 21 f3 35 f4 f5 2 In paging, the OS divide the physical memory into frames which are blocks of small and fixed size

4 3.3 Paging Logical memory PAGE TABLE Physical memory pageframeAttributes f0 04 f1 13 f2 21 f3 35 f4 f5 3 OS divides also the logical memory (program) into pages which are blocks of size equal to frame size.

5 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 f1 P2 13 f2 P3 21 f3 35 f4 f5 4 OS divides also the logical memory (program) into pages which are blocks of size equal to frame size.

6 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 f1 P2 13 f2 P3 21 f3 35 f4 f5 5 The OS uses a page table to map program pages to memory frames.

7 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 f1 P2 13 f2 P3 21 f3 35 P0f4 f5 6 The OS uses a page table to map program pages to memory frames.

8 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 f1 P2 13 f2 P3 21 P1f3 35 P0f4 f5 7 The OS uses a page table to map program pages to memory frames.

9 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 P2f1 P2 13 f2 P3 21 P1f3 35 P0f4 f5 8 The OS uses a page table to map program pages to memory frames.

10 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 P2f1 P2 13 f2 P3 21 P1f3 35 P0f4 P3f5 9 The OS uses a page table to map program pages to memory frames.

11 3.3 Paging Logical memory PAGE TABLE Physical memory P0 pageframeAttributes f0 P1 04 P2f1 P2 13 f2 P3 21 P1f3 35 P0f4 P3f5 10 Paging permits a program to allocate noncontiguous blocks of memory

12 3.3 Paging  Page size (S) is defined by the hardware.  Generally page size is chosen as a power of 2 such as 512 words/page or 4096 words/page etc.  With this arrangement, the words in the program have an address called as logical address. Every logical address is formed of pair 11

13 3.3 Paging  Logical address:  p is page number p = logical address div S  d is displacement (offset) d = logical address mod S 12

14 3.3 Paging  When a logical address is generated by the processor, first the frame number f corresponding to page p is determined by using the page table and then the physical address is calculated as (f*S+d) and the memory is accessed. 13

15 3.3 Paging Logical address Physical address pdfd pageframeattr d d p f pf logical memory physical memory 14

16 3.3 Paging Example 3.2  Consider the following information to form a physical memory map.  Page Size = 8 words  d : 3 bits  Physical Memory Size = 128 words = 128/8=16 frames  f : 4 bits  Assume maximum program size is 4 pages  p : 2 bits  A program of 3 pages where P0  f3; P1  f6; P2  f4 15

17 Logical memoryPhysical memory Word 0…… Word 1 Page 0Word 0 … (P0)Word 1 Frame 3 Word 7 PAGE TABE … (f3) Word 8PageFrameWord 7 Word 9 Page 103Word 16 … (P1)16Word 17 Frame 4 Word 1524… (f4) Word 16Word 23 Word 17 Page 2 … (P2)…… Word 23 Word 8 Word 9 Frame 6 … (f6) Word 15 …… 16

18 3.3 Paging Program Line Word 0 Word 1 … Word 7 Word 8 Word 9 … Word 15 Word 16 Word 17 … Word 23 17

19 3.3 Paging Program Line Logical Address Word 000 000 Word 100 001 …… Word 700 111 Word 801 000 Word 901 001 …… Word 1501 111 Word 1610 000 Word 1710 001 …… Word 2310 111 18

20 3.3 Paging Program Line Logical Address Offset Word 000 000000 Word 100 001001 ……… Word 700 111111 Word 801 000000 Word 901 001001 ……… Word 1501 111111 Word 1610 000000 Word 1710 001001 ……… Word 2310 111111 19

21 3.3 Paging Program Line Logical Address OffsetPage Number Word 000 00000000 Word 100 00100100 ………… Word 700 11111100 Word 801 00000001 Word 901 00100101 ………… Word 1501 11111101 Word 1610 00000010 Word 1710 00100110 ………… Word 2310 11111110 20

22 3.3 Paging Program Line Logical Address OffsetPage Number Frame Number Word 000 000000000011 Word 100 001001000011 …………… Word 700 111111000011 Word 801 000000010010 Word 901 001001010010 …………… Word 1501 111111010010 Word 1610 000000100000 Word 1710 001001100000 …………… Word 2310 111111100100 21

23 3.3 Paging Program Line Logical Address OffsetPage Number Frame Number Physical Address Word 000 0000000000110011 000 Word 100 0010010000110011 001 ……………… Word 700 1111110000110011 111 Word 801 0000000100100110 000 Word 901 0010010100100110 001 ……………… Word 1501 1111110100100110 111 Word 1610 0000001000000100 000 Word 1710 0010011000000100 001 ……………… Word 2310 1111111001000100 111 22

24 3.3 Paging  Every access to memory should go through the page table. Therefore, it must be implemented in an efficient way.  How to Implement The Page Table?  Using fast dedicated registers  Keep the page table in main memory  Use content-addressable associative registers 23

25 Using fast dedicated registers  Keep page table in fast dedicated registers. Only the OS is able to modify these registers.  However, if the page table is large, this method becomes very expensive since requires too many registers. 24

26 Using fast dedicated registers 25 P { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/3359228/12/slides/slide_25.jpg", "name": "Using fast dedicated registers 25 P

27 Keep the page table in main memory  In this second method, the OS keeps a page table in the memory, instead of registers.  For every logical memory reference, two memory accesses are required: 1. To access the page table in the memory, in order to find the corresponding frame number. 2. To access the memory word in that frame  This is cheap but a time consuming method. 26

28 Keep the page table in main memory 27 P { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/3359228/12/slides/slide_27.jpg", "name": "Keep the page table in main memory 27 P

29 Use content-addressable associative registers  This is a mixing of first two methods.  Associative registers are small, high speed registers built in a special way so that they permit an associative search over their contents.  That is, all registers may be searched in one machine cycle simultaneously.  However, associative registers are quite expensive. So, a small number of them should be used.  In the overall, the method is not-expensive and not- slow. 28

30 Use content-addressable associative registers 29 Effective Memory Access Time: h: hit ratio Emat=h *emat HIT + (1-h) * emat MISS =h(rat+mat)+(1-h)(rat+mat+mat) P { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/3359228/12/slides/slide_29.jpg", "name": "Use content-addressable associative registers 29 Effective Memory Access Time: h: hit ratio Emat=h *emat HIT + (1-h) * emat MISS =h(rat+mat)+(1-h)(rat+mat+mat) P

31 Use content-addressable associative registers  Assume we have a paging system which uses associative registers. These associative registers have an access time of 30 ns, and the memory access time is 470 ns. The system has a hit ratio of 90 %.  rat=30 ns  mat=470ns  h=0.9 30

32 Use content-addressable associative registers rat=30 ns, mat=470ns, h=0.9  Now, if the page number is found in one of the associative registers, then the effective access time:  emat HIT = 30 + 470 = 500 ns.  Because one access to associative registers and one access to the main memory is sufficient. 31

33 Use content-addressable associative registers rat=30 ns, mat=470ns, h=0.9  On the other hand, if the page number is not found in associative registers, then the effective access time:  emat MISS = 30 + (470+470) = 970 ns.  Since one access to associative registers and two accesses to the main memory are required. 32

34 Use content-addressable associative registers rat=30 ns, mat=470ns, h=0.9 emat HIT = 500 ns, emat MISS = 970 ns.  Then, the emat is calculated as follows: emat= h *emat HIT + (1-h) * emat MISS = 0.9 * 500 + 0.1 * 970 = 450 + 97 = 547 ns 33

35 Sharing Pages  Sharing pages is possible in a paging system, and is an important advantage of paging.  It is possible to share system procedures or programs, user procedures or programs, and possibly data area.  Sharing pages is especially advantageous in time-sharing systems. 34

36 Sharing Pages  A reentrant program (non-self-modifying code = read only) never changes during execution.  So, more than one process can execute the same code at the same time.  Each process will have its own data storage and its own copy of registers to hold the data for its own execution of the shared program. 35

37 Sharing Pages  Example 3.4  Consider a system having page size=30 MB.  There are 3 users executing an editor program which is 90 MB (3 pages) in size, with a 30 MB (1 page) data space.  To support these 3 users, the OS must allocate 3 * (90+30) = 360 MB space.  However, if the editor program is reentrant (non-self-modifying code = read only), then it can be shared among the users, and only one copy of the editor program is sufficient. Therefore, only 90 + 30 * 3 = 180 MB of memory space is enough for this case 36

38 37 User-1PT-1Physical P0e1Page#Frame#Memory P1e208f0OS P2e314f1OS P3data125f2OS 37f3 f4e2 User-2PT-2f5e3 P0e1Page#Frame#f6 P1e208f7data1 P2e314f8e1 P3data225f9 312f10 f11 User-3PT-3f12 P0e1Page#Frame#f13 P1e208f14 P2e314f15 P3data325 310

39 38 User-1PT-1Physical P0e1Page#Frame#Memory P1e208f0OS P2e314f1OS P3data125f2OS 37f3 f4e2 User-2PT-2f5e3 P0e1Page#Frame#f6 P1e208f7data1 P2e314f8e1 P3data225f9 312f10 f11 User-3PT-3f12data 2 P0e1Page#Frame#f13 P1e208f14 P2e314f15 P3data325 310

40 39 User-1PT-1Physical P0e1Page#Frame#Memory P1e208f0OS P2e314f1OS P3data125f2OS 37f3 f4e2 User-2PT-2f5e3 P0e1Page#Frame#f6 P1e208f7data1 P2e314f8e1 P3data225f9 312f10data3 f11 User-3PT-3f12data 2 P0e1Page#Frame#f13 P1e208f14 P2e314f15 P3data325 310

41 40 User-1PT-1Physical P0e1Page#Frame#Memory P1e208f0OS P2e314f1OS P3data125f2OS 37f3 f4e2 User-2PT-2f5e3 P0e1Page#Frame#f6 P1e208f7data1 P2e314f8e1 P3data225f9 312f10data3 f11 User-3PT-3f12 P0e1Page#Frame#f13 P1e208f14 P2e314f15 P3data325 310 User 2 terminates: Data2 page is removed from memory, but editör pages remain.. User 2 terminates: Data2 page is removed from memory, but editör pages remain..

42 41 User-1PT-1Physical P0e1Page#Frame#Memory P1e208f0OS P2e314f1OS P3data125f2OS 37f3 f4e2 User-2PT-2f5e3 P0e1Page#Frame#f6 P1e208f7 P2e314f8e1 P3data225f9 312f10data3 f11 User-3PT-3f12 P0e1Page#Frame#f13 P1e208f14 P2e314f15 P3data325 310 User 1 terminates: data1 is also removed from memory. User 1 terminates: data1 is also removed from memory.

43 42 User-1PT-1Physical P0e1Page#Frame#Memory P1e208f0OS P2e314f1OS P3data125f2OS 37f3 f4 User-2PT-2f5 P0e1Page#Frame#f6 P1e208f7 P2e314f8 P3data225f9 312f10 f11 User-3PT-3f12 P0e1Page#Frame#f13 P1e208f14 P2e314f15 P3data325 310 When User 3 terminates: Data-3 and also editor segments are removed from memory. When User 3 terminates: Data-3 and also editor segments are removed from memory.

44 3.4 Segmentation  In segmentation, programs are divided into variable size segments, instead of fixed size pages.  This is similar to variable partitioning, but programs are divided to small parts.  Every logical address is formed of a segment name and an offset within that segment.  In practice, segments are numbered.  Programs are segmented automatically by the compiler or assembler. 43

45 3.4 Segmentation  For example, a C compiler may create segments for:  the code of each function  the local variables for each function  the global variables. 44 main Func 1 Func 2 Data 1 Data 2 Data 3 OS main Func 1 Func 2 Data 1 Data 2 Data 3 Logical memoryPhysical memory

46 3.4 Segmentation  For logical to physical address mapping, a segment table is used. When a logical address is generated by the processor: 1. Base and limit values corresponding to segment s are determined using the segment table 2. The OS checks whether d is in the limit. (0  d < limit) 3. If so, then the physical address is calculated as (base + d), and the memory is accessed. 45

47 3.4 Segmentation 46 s s d d Logical address seg. # limit base attr Segment Table 0≤d { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/3359228/12/slides/slide_46.jpg", "name": "3.4 Segmentation 46 s s d d Logical address seg.", "description": "# limit base attr Segment Table 0≤d

48 3.4 Segmentation  Example 3.5 Generate the memory map according to the given segment table. Assume the generated logical address is ; find the corresponding physical address. 47 SegmentLimitBase 015001000 12005500 27006000 320003500

49 3.4 Segmentation 48 SegmentLimitBase 015001000 12005500 27006000 320003500 OS s0 s3 s1 s2 Physical memory 1000 2500 3500 5500 5700 6000 6700 1500 2000 200 700 0

50 3.4 Segmentation 49 SegmentLimitBase 015001000 12005500 27006000 320003500 OS s0 s3 s1 s2 Physical memory 1000 2500 3500 5500 5700 6000 6700 1500 2000 200 700 Logical address: s=3, d=1123 Check if d { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/3359228/12/slides/slide_49.jpg", "name": "3.4 Segmentation 49 SegmentLimitBase 015001000 12005500 27006000 320003500 OS s0 s3 s1 s2 Physical memory 1000 2500 3500 5500 5700 6000 6700 1500 2000 200 700 Logical address: s=3, d=1123 Check if d

51 3.4 Segmentation 50 SegmentLimitBase 015001000 12005500 27006000 320003500 OS s0 s3 s1 s2 Physical memory 1000 2500 3500 5500 5700 6000 6700 1500 2000 200 700 Logical address: s=3, d=1123 Check if d { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/3359228/12/slides/slide_50.jpg", "name": "3.4 Segmentation 50 SegmentLimitBase 015001000 12005500 27006000 320003500 OS s0 s3 s1 s2 Physical memory 1000 2500 3500 5500 5700 6000 6700 1500 2000 200 700 Logical address: s=3, d=1123 Check if d

52 3.4 Segmentation 51 SegmentLimitBase 015001000 12005500 27006000 320003500 OS s0 s3 s1 s2 Physical memory 1000 2500 3500 5500 5700 6000 6700 1500 2000 200 700 Logical address: s=3, d=1123 Check if d { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/3359228/12/slides/slide_51.jpg", "name": "3.4 Segmentation 51 SegmentLimitBase 015001000 12005500 27006000 320003500 OS s0 s3 s1 s2 Physical memory 1000 2500 3500 5500 5700 6000 6700 1500 2000 200 700 Logical address: s=3, d=1123 Check if d

53 3.4 Segmentation  Segment tables may be implemented in the main memory or in associative registers, in the same way it is done for page tables.  Also sharing of segments is applicable as in paging. Shared segments should be read only and should be assigned the same segment number. 52

54 Sharing Segments ST1 seglimbase 015001000 120003500 53 OS Editör Data-1 Physical memory 1000 2500 3500 5500 1500 2000 0 Editör Data-1 user1 s0 s1

55 Sharing Segments ST1 seglimbase 015001000 120003500 ST2 seglimbase 015001000 12005500 54 OS Editör Data-1 Data-2 Physical memory 1000 2500 3500 5500 5700 1500 2000 200 0 Editör Data-1 user1 s0 s1 Editör Data-2 user2 s0 s1

56 Sharing Segments ST1 seglimbase 015001000 120003500 ST2 seglimbase 015001000 12005500 ST3 seglimbase 015001000 17006000 55 OS Editör Data-1 Data-2 Data-3 Physical memory 1000 2500 3500 5500 5700 6000 6700 1500 2000 200 700 0 Editör Data-1 user1 s0 s1 Editör Data-2 user2 s0 s1 Editör Data-3 user3 s0 s1

57 Sharing Segments ST1 seglimbase 015001000 120003500 ST3 seglimbase 01500100 17006000 56 OS Editör Data-1 Dat-3 Physical memory 1000 2500 3500 5500 6000 6700 1500 2000 700 0 Editör Data-1 user1 s0 s1 Editör Data-3 user3 s0 s1 User 2 terminates: Data-2 removed from memory, but editör remains.. User 2 terminates: Data-2 removed from memory, but editör remains..

58 Sharing Segments ST3 seglimbase 01500100 17006000 57 OS Editör Data-3 Physical memory 1000 2500 6000 6700 1500 700 0 Editör Data-3 user3 s0 s1 User 1 terminates: Data-1segment is removed from memory. User 1 terminates: Data-1segment is removed from memory.

59 Sharing Segments 58 OS Physical memory 0 When User 3 terminates: Data-1 and also editor segments are removed from memory. When User 3 terminates: Data-1 and also editor segments are removed from memory. When User 3 terminates: Data-3 segment and also editor segment are removed from memory. When User 3 terminates: Data-3 segment and also editor segment are removed from memory.


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