Presentation is loading. Please wait.

Presentation is loading. Please wait.

3.3 Paging PAGE TABLE Logical memory Physical memory page frame

Published byAnnette Tibbits Modified over 9 years ago

Similar presentations

Presentation on theme: "3.3 Paging PAGE TABLE Logical memory Physical memory page frame"— Presentation transcript:

0 CHAPTER 3 MEMORY MANAGEMENT PART 2
by Uğur Halıcı

1 3.3 Paging PAGE TABLE Logical memory Physical memory page frame
Attributes 4 1 3 2 5 In paging, the OS divide the physical memory into frames which are blocks of small and fixed size

2 3.3 Paging PAGE TABLE Logical memory Physical memory P0 page frame
Attributes f0 P1 4 f1 P2 1 3 f2 P3 2 f3 5 f4 f5 In paging, the OS divide the physical memory into frames which are blocks of small and fixed size

3 3.3 Paging PAGE TABLE Logical memory Physical memory page frame
Attributes f0 4 f1 1 3 f2 2 f3 5 f4 f5 OS divides also the logical memory (program) into pages which are blocks of size equal to frame size.

4 3.3 Paging PAGE TABLE Logical memory Physical memory P0 page frame
Attributes f0 P1 4 f1 P2 1 3 f2 P3 2 f3 5 f4 f5 OS divides also the logical memory (program) into pages which are blocks of size equal to frame size.

5 3.3 Paging PAGE TABLE Logical memory Physical memory P0 page frame
Attributes f0 P1 4 f1 P2 1 3 f2 P3 2 f3 5 f4 f5 The OS uses a page table to map program pages to memory frames.

6 3.3 Paging PAGE TABLE Logical memory Physical memory P0 page frame
Attributes f0 P1 4 f1 P2 1 3 f2 P3 2 f3 5 f4 f5 The OS uses a page table to map program pages to memory frames.

7 3.3 Paging PAGE TABLE Logical memory Physical memory P0 page frame
Attributes f0 P1 4 f1 P2 1 3 f2 P3 2 f3 5 f4 f5 The OS uses a page table to map program pages to memory frames.

8 3.3 Paging PAGE TABLE Logical memory Physical memory P0 page frame
Attributes f0 P1 4 P2 f1 1 3 f2 P3 2 f3 5 f4 f5 The OS uses a page table to map program pages to memory frames.

9 3.3 Paging PAGE TABLE Logical memory Physical memory P0 page frame
Attributes f0 P1 4 P2 f1 1 3 f2 P3 2 f3 5 f4 f5 The OS uses a page table to map program pages to memory frames.

10 3.3 Paging PAGE TABLE Logical memory Physical memory P0 page frame
Attributes f0 P1 4 P2 f1 1 3 f2 P3 2 f3 5 f4 f5 Paging permits a program to allocate noncontiguous blocks of memory

11 3.3 Paging Page size (S) is defined by the hardware.
Generally page size is chosen as a power of 2 such as 512 words/page or 4096 words/page etc. With this arrangement, the words in the program have an address called as logical address. Every logical address is formed of <p,d> pair

12 3.3 Paging Logical address: <p,d> p is page number
p is page number p = logical address div S d is displacement (offset) d = logical address mod S

13 3.3 Paging  When a logical address <p, d> is generated by the processor, first the frame number f corresponding to page p is determined by using the page table and then the physical address is calculated as (f*S+d) and the memory is accessed.

14 3.3 Paging Logical address Physical address p d f logical memory
page frame attr logical memory physical memory

15 3.3 Paging Example 3.2 Consider the following information to form a physical memory map. Page Size = 8 words  d : 3 bits Physical Memory Size = 128 words = 128/8=16 frames  f : 4 bits Assume maximum program size is 4 pages  p : 2 bits A program of 3 pages where P0  f3; P1  f6; P2  f4

16 PAGE TABE Logical memory Physical memory Word 0 … Word 1 Page 0 (P0)
Frame 3 Word 7 PAGE TABE (f3) Word 8 Page Frame Word 9 Page 1 3 Word 16 (P1) 1 6 Word 17 Frame 4 Word 15 2 4 (f4) Word 23 Page 2 (P2) Frame 6 (f6)

17 3.3 Paging Program Line Word 0 Word 1 … Word 7 Word 8 Word 9 Word 15

18 3.3 Paging Program Line Logical Address Word 0 00 000 Word 1 00 001 …
00 111 Word 8 01 000 Word 9 01 001 Word 15 01 111 Word 16 10 000 Word 17 10 001 Word 23 10 111

19 3.3 Paging Program Line Logical Address Offset Word 0 00 000 000
00 001 001 … Word 7 00 111 111 Word 8 01 000 Word 9 01 001 Word 15 01 111 Word 16 10 000 Word 17 10 001 Word 23 10 111

20 3.3 Paging Program Line Logical Address Offset Page Number Word 0
00 000 000 00 Word 1 00 001 001 … Word 7 00 111 111 Word 8 01 000 01 Word 9 01 001 Word 15 01 111 Word 16 10 000 10 Word 17 10 001 Word 23 10 111

21 3.3 Paging Program Line Logical Address Offset Page Number
Frame Number Word 0 00 000 000 00 0011 Word 1 00 001 001 … Word 7 00 111 111 Word 8 01 000 01 0010 Word 9 01 001 Word 15 01 111 Word 16 10 000 10 0000 Word 17 10 001 Word 23 10 111 0100

22 3.3 Paging Program Line Logical Address Offset Page Number
Frame Number Physical Address Word 0 00 000 000 00 0011 Word 1 00 001 001 … Word 7 00 111 111 Word 8 01 000 01 0010 Word 9 01 001 Word 15 01 111 Word 16 10 000 10 0000 Word 17 10 001 Word 23 10 111 0100

23 3.3 Paging Every access to memory should go through the page table. Therefore, it must be implemented in an efficient way. How to Implement The Page Table? Using fast dedicated registers Keep the page table in main memory Use content-addressable associative registers

24 Using fast dedicated registers
Keep page table in fast dedicated registers. Only the OS is able to modify these registers. However, if the page table is large, this method becomes very expensive since requires too many registers.

25 Using fast dedicated registers
logical address PTLR: Page Table Length Register p d access PT in registers f d physical address access memory rat mat P<PTLR YES NO ERROR Effective Memory Access Time emat=rat+mat

26 Keep the page table in main memory
In this second method, the OS keeps a page table in the memory, instead of registers. For every logical memory reference, two memory accesses are required: To access the page table in the memory, in order to find the corresponding frame number. To access the memory word in that frame This is cheap but a time consuming method.

27 Keep the page table in main memory
P<PTLR p d logical address Access PT entry in Memory at address PTBR + p f physical address access memory mat NO YES ERROR PTBR: Page Table Base Register PTLR: Page Table Length Register Effective Memory Access Time: emat=mat+mat=2mat

28 Use content-addressable associative registers
This is a mixing of first two methods. Associative registers are small, high speed registers built in a special way so that they permit an associative search over their contents. That is, all registers may be searched in one machine cycle simultaneously. However, associative registers are quite expensive. So, a small number of them should be used. In the overall, the method is not-expensive and not- slow.

29 Use content-addressable associative registers
P<PTLR p d logical address Access PT entry in Memory at address PTBR + p f physical address access memory mat No Yes ERROR rat search PT in AR Found? Yes (HIT) No (MISS) Effective Memory Access Time: h: hit ratio Emat=h *ematHIT + (1-h) * ematMISS =h(rat+mat)+(1-h)(rat+mat+mat)

30 Use content-addressable associative registers
Assume we have a paging system which uses associative registers. These associative registers have an access time of 30 ns, and the memory access time is 470 ns. The system has a hit ratio of 90 %. rat=30 ns mat=470ns h=0.9

31 Use content-addressable associative registers
rat=30 ns, mat=470ns, h=0.9 Now, if the page number is found in one of the associative registers, then the effective access time: ematHIT = = 500 ns. Because one access to associative registers and one access to the main memory is sufficient.

32 Use content-addressable associative registers
rat=30 ns, mat=470ns, h=0.9 On the other hand, if the page number is not found in associative registers, then the effective access time: ematMISS = 30 + ( ) = 970 ns. Since one access to associative registers and two accesses to the main memory are required.

33 Use content-addressable associative registers
rat=30 ns, mat=470ns, h=0.9 ematHIT = 500 ns, ematMISS = 970 ns. Then, the emat is calculated as follows: emat= h *ematHIT + (1-h) * ematMISS = 0.9 * * 970 = = 547 ns

34 Sharing Pages Sharing pages is possible in a paging system, and is an important advantage of paging. It is possible to share system procedures or programs, user procedures or programs, and possibly data area. Sharing pages is especially advantageous in time-sharing systems.

35 Sharing Pages A reentrant program (non-self-modifying code = read only) never changes during execution. So, more than one process can execute the same code at the same time. Each process will have its own data storage and its own copy of registers to hold the data for its own execution of the shared program.

36 Sharing Pages Example 3.4 Consider a system having page size=30 MB.
There are 3 users executing an editor program which is 90 MB (3 pages) in size, with a 30 MB (1 page) data space. To support these 3 users, the OS must allocate 3 * (90+30) = 360 MB space. However, if the editor program is reentrant (non-self-modifying code = read only), then it can be shared among the users, and only one copy of the editor program is sufficient. Therefore, only * 3 = 180 MB of memory space is enough for this case

37 User-1 PT-1 Physical P0 e1 Page# Frame# Memory P1 e2 8 f0 OS P2 e3 1 4 f1 P3 data1 2 5 f2 3 7 f3 f4 User-2 PT-2 f5 f6 f7 f8 data2 f9 12 f10 f11 User-3 PT-3 f12 f13 f14 f15 data3 10

38 User-1 PT-1 Physical P0 e1 Page# Frame# Memory P1 e2 8 f0 OS P2 e3 1 4 f1 P3 data1 2 5 f2 3 7 f3 f4 User-2 PT-2 f5 f6 f7 f8 data2 f9 12 f10 f11 User-3 PT-3 f12 data 2 f13 f14 f15 data3 10

39 User-1 PT-1 Physical P0 e1 Page# Frame# Memory P1 e2 8 f0 OS P2 e3 1 4 f1 P3 data1 2 5 f2 3 7 f3 f4 User-2 PT-2 f5 f6 f7 f8 data2 f9 12 f10 data3 f11 User-3 PT-3 f12 data 2 f13 f14 f15 10

40 Data2 page is removed from memory, but editör pages remain..
User-1 PT-1 Physical P0 e1 Page# Frame# Memory P1 e2 8 f0 OS P2 e3 1 4 f1 P3 data1 2 5 f2 3 7 f3 f4 User-2 PT-2 f5 f6 f7 f8 data2 f9 12 f10 data3 f11 User-3 PT-3 f12 f13 f14 f15 10 User 2 terminates: Data2 page is removed from memory, but editör pages remain..

41 data1 is also removed from memory.
User-1 PT-1 Physical P0 e1 Page# Frame# Memory P1 e2 8 f0 OS P2 e3 1 4 f1 P3 data1 2 5 f2 3 7 f3 f4 User-2 PT-2 f5 f6 f7 f8 data2 f9 12 f10 data3 f11 User-3 PT-3 f12 f13 f14 f15 10 User 1 terminates: data1 is also removed from memory.

42 Data-3 and also editor segments are removed from memory.
User-1 PT-1 Physical P0 e1 Page# Frame# Memory P1 e2 8 f0 OS P2 e3 1 4 f1 P3 data1 2 5 f2 3 7 f3 f4 User-2 PT-2 f5 f6 f7 f8 data2 f9 12 f10 f11 User-3 PT-3 f12 f13 f14 f15 data3 10 When User 3 terminates: Data-3 and also editor segments are removed from memory.

43 3.4 Segmentation In segmentation, programs are divided into variable size segments, instead of fixed size pages. This is similar to variable partitioning, but programs are divided to small parts. Every logical address is formed of a segment name and an offset within that segment. In practice, segments are numbered. Programs are segmented automatically by the compiler or assembler.

44 3.4 Segmentation OS main Func 1 Func 2 Data 1 Data 2 Data 3
For example, a C compiler may create segments for: the code of each function the local variables for each function the global variables. main Func 1 Func 2 Data 1 Data 2 Data 3 Logical memory Physical memory

45 3.4 Segmentation For logical to physical address mapping, a segment table is used. When a logical address <s, d> is generated by the processor: Base and limit values corresponding to segment s are determined using the segment table The OS checks whether d is in the limit. (0  d < limit) If so, then the physical address is calculated as (base + d), and the memory is accessed.

46 3.4 Segmentation s d OS segment s ERROR Logical address No 0≤d
<limit s d base Segment Table d Yes acess the word at physical address = base + d seg. # limit base attr Physical memory

47 3.4 Segmentation Example 3.5 Generate the memory map according to the given segment table. Assume the generated logical address is <1,1123>; find the corresponding physical address. Segment Limit Base 1500 1000 1 200 5500 2 700 6000 3 2000 3500

48 3.4 Segmentation OS s0 s3 s1 s2 Segment Limit Base 1500 1000 1 200
3.4 Segmentation OS s0 s3 s1 s2 Segment Limit Base 1500 1000 1 200 5500 2 700 6000 3 2000 3500 1000 1500 2500 3500 2000 5500 200 5700 6000 700 6700 Physical memory

49 3.4 Segmentation OS s0 s3 s1 s2 Segment Limit Base 1500 1000 1 200
3.4 Segmentation OS s0 s3 s1 s2 Segment Limit Base 1500 1000 1 200 5500 2 700 6000 3 2000 3500 1000 1500 2500 3500 2000 5500 200 Logical address: <3,1123> s=3, d=1123 Check if d<limit? 1123<2000, OK Physical address= base+d= =4623 5700 6000 700 6700 Physical memory

50 3.4 Segmentation OS s0 s3 s1 s2 Segment Limit Base 1500 1000 1 200
3.4 Segmentation OS s0 s3 s1 s2 Segment Limit Base 1500 1000 1 200 5500 2 700 6000 3 2000 3500 1000 1500 Base= 3500 2500 3500 2000 5500 200 Logical address: <3,1123> s=3, d=1123 Check if d<limit? 1123<2000, OK Physical address= base+d= =4623 5700 6000 700 6700 Physical memory

51 3.4 Segmentation OS s0 s3 s1 s2 Segment Limit Base 1500 1000 1 200
3.4 Segmentation OS s0 s3 s1 s2 Segment Limit Base 1500 1000 1 200 5500 2 700 6000 3 2000 3500 1000 1500 Base= 3500 2500 3500 d= 1123 2000 4623 5500 200 Logical address: <3,1123> s=3, d=1123 Check if d<limit? 1123<2000, OK Physical address= base+d= =4623 5700 6000 700 6700 Physical memory

52 3.4 Segmentation Segment tables may be implemented in the main memory or in associative registers, in the same way it is done for page tables. Also sharing of segments is applicable as in paging. Shared segments should be read only and should be assigned the same segment number.

53 Sharing Segments OS Editör Editör Data-1 Data-1 user1 s0 s1
Sharing Segments OS Editör Data-1 user1 s0 s1 ST1 seg lim base 1500 1000 1 2000 3500 1000 Editör 1500 2500 3500 Data-1 2000 5500 Physical memory

54 Sharing Segments OS Editör Editör Data-1 Data-1 Editör Data-2 Data-2
Sharing Segments OS Editör Data-1 user1 s0 s1 ST1 seg lim base 1500 1000 1 2000 3500 ST2 200 5500 1000 Editör 1500 2500 Editör Data-2 user2 s0 s1 3500 Data-1 2000 5500 Data-2 200 5700 Physical memory

55 Sharing Segments OS Editör Editör Data-1 Data-1 Editör Data-2 Data-2
Sharing Segments OS Editör Data-1 Data-2 Data-3 Editör Data-1 user1 s0 s1 ST1 seg lim base 1500 1000 1 2000 3500 ST2 200 5500 ST3 700 6000 1000 1500 2500 Editör Data-2 user2 s0 s1 3500 2000 5500 200 5700 Editör Data-3 user3 s0 s1 6000 700 6700 Physical memory

56 Data-2 removed from memory, but editör remains..
Sharing Segments OS Editör Data-1 user1 s0 s1 ST1 seg lim base 1500 1000 1 2000 3500 ST3 100 700 6000 1000 Editör 1500 2500 3500 User 2 terminates: Data-2 removed from memory, but editör remains.. Data-1 2000 5500 Editör Data-3 user3 s0 s1 6000 Dat-3 700 6700 Physical memory

57 Data-1segment is removed from memory.
Sharing Segments OS ST3 seg lim base 1500 100 1 700 6000 User 1 terminates: Data-1segment is removed from memory. 1000 Editör 1500 2500 Editör Data-3 user3 s0 s1 6000 Data-3 700 6700 Physical memory

58 Sharing Segments OS When User 3 terminates:
Sharing Segments OS When User 3 terminates: Data-1 and also editor segments are removed from memory. When User 3 terminates: Data-3 segment and also editor segment are removed from memory. Physical memory

Download ppt "3.3 Paging PAGE TABLE Logical memory Physical memory page frame"

Similar presentations

Memory.

Memory.
Page Table Implementation

Page Table Implementation
Memory management In a multiprogramming system, in order to share the processor, a number of processes must be kept in memory. Memory management is achieved.

Memory management In a multiprogramming system, in order to share the processor, a number of processes must be kept in memory. Memory management is achieved.
Allocating Memory.

Allocating Memory.
CSC 4250 Computer Architectures December 8, 2006 Chapter 5. Memory Hierarchy.

CSC 4250 Computer Architectures December 8, 2006 Chapter 5. Memory Hierarchy.
Day 20 Memory Management. Assumptions A process need not be stored as one contiguous block. The entire process must reside in main memory.

Day 20 Memory Management. Assumptions A process need not be stored as one contiguous block. The entire process must reside in main memory.
Memory Management Design & Implementation Segmentation Chapter 4.

Memory Management Design & Implementation Segmentation Chapter 4.
Chapter 10 – Virtual Memory Organization Outline 10.1 Introduction 10.2Virtual Memory: Basic Concepts 10.3Block Mapping 10.4Paging 10.4.1Paging Address.

Chapter 10 – Virtual Memory Organization Outline 10.1 Introduction 10.2Virtual Memory: Basic Concepts 10.3Block Mapping 10.4Paging Paging Address.
Chapter 8.3: Memory Management

Chapter 8.3: Memory Management
1 Chapter 8 Virtual Memory Virtual memory is a storage allocation scheme in which secondary memory can be addressed as though it were part of main memory.

1 Chapter 8 Virtual Memory Virtual memory is a storage allocation scheme in which secondary memory can be addressed as though it were part of main memory.
Chapter 5: Memory Management Dhamdhere: Operating Systems— A Concept-Based Approach Slide No: 1 Copyright ©2005 Memory Management Chapter 5.

Chapter 5: Memory Management Dhamdhere: Operating Systems— A Concept-Based Approach Slide No: 1 Copyright ©2005 Memory Management Chapter 5.
Memory Management Five Requirements for Memory Management to satisfy: –Relocation Users generally don’t know where they will be placed in main memory May.

Memory Management Five Requirements for Memory Management to satisfy: –Relocation Users generally don’t know where they will be placed in main memory May.
1 Memory Management Virtual Memory Chapter 4. 2 The virtual memory concept In a multiprogramming environment, an entire process does not have to take.

1 Memory Management Virtual Memory Chapter 4. 2 The virtual memory concept In a multiprogramming environment, an entire process does not have to take.
03/22/2004CSCI 315 Operating Systems Design1 Virtual Memory Notice: The slides for this lecture have been largely based on those accompanying the textbook.

03/22/2004CSCI 315 Operating Systems Design1 Virtual Memory Notice: The slides for this lecture have been largely based on those accompanying the textbook.
Virtual Memory BY JEMINI ISLAM. What is Virtual Memory Virtual memory is a memory management system that gives a computer the appearance of having more.

Virtual Memory BY JEMINI ISLAM. What is Virtual Memory Virtual memory is a memory management system that gives a computer the appearance of having more.
A. Frank - P. Weisberg Operating Systems Simple/Basic Paging.

A. Frank - P. Weisberg Operating Systems Simple/Basic Paging.
CS 333 Introduction to Operating Systems Class 12 - Virtual Memory (2) Jonathan Walpole Computer Science Portland State University.

CS 333 Introduction to Operating Systems Class 12 - Virtual Memory (2) Jonathan Walpole Computer Science Portland State University.
1 Tuesday, July 04, 2006 Programs expand to fill the memory available to hold them. - Modified Parkinson’s Law.

1 Tuesday, July 04, 2006 "Programs expand to fill the memory available to hold them." - Modified Parkinson’s Law.
VIRTUAL MEMORY. Virtual memory technique is used to extents the size of physical memory When a program does not completely fit into the main memory, it.

VIRTUAL MEMORY. Virtual memory technique is used to extents the size of physical memory When a program does not completely fit into the main memory, it.
Virtual Memory By: Dinouje Fahih. Definition of Virtual Memory Virtual memory is a concept that, allows a computer and its operating system, to use a.

Virtual Memory By: Dinouje Fahih. Definition of Virtual Memory Virtual memory is a concept that, allows a computer and its operating system, to use a.

Similar presentations

Ads by Google