1. Electronic Systems Design Group Department of Electronics and Computer Science University of Southampton, UK Application of Group Delay Equalisation in Testing Fully Balanced OTA-C Filters Bashir Al-Hashimi bmah@ecs.soton.ac.ukrw01r@ecs.soton.ac.uk Reuben Wilcock

2. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 2 Outline Introduction Defect oriented testing Design of fully balanced OTA-C filter Fault models and simulation in filter Proposed test methodology Test circuitry design Results Conclusions

3. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 3 Introduction Integrated Circuits are subject to defects Testing is clearly necessary BIST increasingly attractive for complex IC’s Many analog BIST schemes in the literature: –Analog scan path approach [Wey, I&M ’90] –Time Domain BIST [Provost et al, GLS ’98] –Current mode approach [Lee et al, CAS-II ’99] –Reconfigurable SC biquad [Cota et al, DATE ’00] –Ramp stimuli based BIST [Nadal et al, DATE ’01]

4. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 4 Defect oriented testing Manufacturing process defects are the major cause of yield loss in ICs [Vinnakota et al] Short and open faults known as ‘hard faults’ Simple defect oriented tests can give high fault coverage for common faults [Xing, ITC ’98] Study fault affects in detail to aid BIST design Design Circuit Simulate with Faults Develop BIST

5. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 5 Filter Design Simulated LC ladder fully-balanced OTA-C filter –Low sensitivity to component variations –Symmetrical, differential design rejects noise –Only grounded capacitors –No sampling effects

6. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 6 Fault Models Select T-level OTA [Nauta, Electronic Letters, ’89] Simulate all possible short/open faults Build representative list – drop similar faults Create ‘faulty’ OTA subcircuits ShortsOpens Vin + to Iout + gate, M1 Vin + to Iout - drain, M2 Vin - to Iout + source, M4 etc… Vin- Vin+ Iout+ Iout- vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd - - + + gm

7. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 7 Fault Insertion Simulate filter with faulty OTA subcircuits –1V p-p sinusoidal test signal in passband –Gain understanding of effects these faults have Main effects of the detrimental faults: Majority of faults change output by  200mV in some way amplitude +ve offset -ve offset

8. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 8 Test Methodology Sinusoid test signal in passband Equaliser acts like filter at test frequency Compare outputs of filter and equaliser Filter Inputs Test Output Test Mode Filter Outputs On-Chip Oscillator? Fully Balanced Filter Fully Balanced Equaliser Analysis Window Detector Output Evaluation BIST

9. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 9 Equaliser Design First order OTA-C group delay equaliser –Much simpler circuit than filter itself –Matches filters of different types, orders and f c –Calculate C to match filter DC group delay –Signal inversion allows simpler analysis block design  (s) = = -d  (  ) dd 2C gmgm - - + + - - + + gm C C Equaliser Block

10. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 10 Test Circuitry Design Equaliser Filter Test output vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss vdd vss Analysis Window Detector Output Evaluation

11. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 11 Results: fault-free The fault-free response: –Filter and equaliser outputs cancel resulting in negligible analysis block output –The analysis output lies completely in the acceptable window –Test output is LOW Filter output Equaliser output Analysis block output Test output 0.8 0 4 -4 0 10200 Amplitude (V) Time (µs) Amplitude (V) FAULT- FREE

12. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 12 Results: faulty Faulty filter examples: Filter output Equaliser output Analysis block output Test output 0.8 0 4 -4 0 10200 Amplitude (V) Time (µs) Amplitude (V) FAULTY: output offset 0.8 0 4 -4 0 10200 Amplitude (V) Time (µs) Amplitude (V) FAULTY: output reduced

13. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 13 Conclusions Analog BIST for fully-balanced OTA-C filters Effective: short/open fault coverage of 99% Simple: area overhead from layout is 20% Almost no performance impact on filter Low accuracy test frequency required Tolerant to normal component variations Methodology is applicable to many filter types Filter Test

14. Electronic Systems Design Group University of Southampton, UK Department of Electronics and Computer Science Slide 14 Contact Reuben Wilcock Electronic Systems Design Department of Electronics and Computer Science University of Southampton United Kingdom rw01r@ecs.soton.ac.uk