# William Sandqvist It could be pedagogical to study a small 4 bit nibble computer in order to understand how real numbers are stored and.

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William Sandqvist william@kth.se It could be pedagogical to study a small 4 bit nibble computer in order to understand how real numbers are stored and handled! Normaly 32 bit registers are used, but the principles from the nibble computer will remain the same.

William Sandqvist william@kth.se The first microprocessor Intel 4004 1971 was a 4 bit (nibble) processor. The customer Busicom wanted a dedicated calculator chip, but the disobedient engineers created a general purpose processor.

William Sandqvist william@kth.se 4.3 Imagine a ”Nibble” computer Computer registers are ”rings”. A four bit register can hold 2 4 = 16 numbers. Either 8 positive (+0…+7) and 8 negative (-1…-8) ”signed numbers”, or 16 (0…F) ”unsigned numbers”. If a result is bigger than 16, the register overflows. (In some processors indicated with a Carry-flag).

William Sandqvist william@kth.se Real numbers in Nibble computer Imagine a ”Nibble” floating point format! Imagine a ”Nibble” fixed point format, Q 3 !

William Sandqvist william@kth.se Q 3 [b 3 b 2 b 1 b 0 ] Fixed point format The Q-format is the same as the signed numbers but downscaled: -1 < Q 3 < 1-b 0 The step between numbers is the weight of b 0 0.125 Fixed point circle!Fixed point number line!

William Sandqvist william@kth.se Floating point (Nibble) Floating point format Sign b 3 Significand 1.b 0 1.0 2 = 1.0 10 1.1 2 = 1.5 10 Exponent b 2 b 1 -1 (exess1) 2 00-1 = 0.5 2 01-1 = 1 2 10-1 = 2 2 11-1 = 4 + 1.0  0.5 = +0.5 + 1.0  1 = +1 + 1.0  2 = +2 + 1.0  4 = +4 + 1.5  0.5 = +0.75 + 1.5  1 = +1.5 + 1.5  2 = +3 + 1.5  4 = +6 - 1.0  0.5 = -0.5 - 1.0  1 = -1 - 1.0  2 = -2 - 1.0  4 = -4 - 1.5  0.5 = -0.75 - 1.5  1 = -1.5 - 1.5  2 = -3 - 1.5  4 = -6 Floating point number line!

William Sandqvist william@kth.se Quantisation error Maximum Quantisation Error MQE: Fixed point: (2 -3 )/2 = 2 -4 = 0.125/2 = 0.0625 Float: (6-4)/2 = 1

William Sandqvist william@kth.se The number Zero In fixed point formats the number zero is represented as [0000] In floating point format, there is no representation for zero! We could use, 0000 as +0 and 1000 as –0, as in the IEEE standard format! The IEEE 32 and 64 bit float standard Floating point circle!

William Sandqvist william@kth.se Converting Real numbers to Binary Hawe you forgotten how?

William Sandqvist william@kth.se 4.4 Six bit float Significand 1.b 2 b 1 b 0 1.000 2 = 1.000 10 1.001 2 = 1.125 10 1.010 2 = 1.25 10 1.011 2 = 1.375 10 1.100 2 = 1.5 10 1.101 2 = 1.625 10 1.110 2 = 1.75 10 1.111 2 = 1.875 10 Exponent b 4 b 3 -1 (exess1) 00-1 = -1 2 00-1 = 0.5 01-1 = 0 2 01-1 = 1 10-1 = 1 2 10-1 = 2 11-1 = 2 2 11-1 = 4 0.25 10 = 0.01 2 = 1.0 2  2 -2 exponent -2 not representable 0.8125 10 = 0.1101 2 = 1.101 2  2 -1 representable -1,375 10 = -1.011 2 = -1.011 2  2 0 representable 4.25 10 = 100.01 2 = 1.0001 2  2 2 significand 1.0001 not representable 7.5 10 = 111.1 2 = 1.111 2  2 2 representable

William Sandqvist william@kth.se Float Addition Algorithm: 1. Check for zeroes 2. Align significands 3. Add/Sub significands 4. Normalize result a = 001111 2  0 01 111  + 01 1.111 b = 010010 2  0 10 010  + 10 1.010 Align significands. 10 > 01 shift smaller number a to right to get same exponent: Significand 0.1111 exponent 10 Add significands: Normalize result: 10.0011 exp 10  1.00011 exp 11 Rounding: 1.00011 ~ 1.001 Result: 0 11 001 a = 1.875 b = 2.5 a+b = 4.5 (4.375)

William Sandqvist william@kth.se Float Multiplication Simpler than addition! Algorithm: 1. Check for zeroes 2. Add exponents and subtract Bias 3. Multiply significands 4. Normalize Exponents: 01 10 Bias = 1 exp = 01+10 -1 = 10 Multiply significands Normalize result: 10.010110 exp 10  1.0010110 exp 11 Rounding: 1.0010110 ~ 1.001 Result: 0 11 001 a = 1.875 b = 2.5 a*b = 4.5 (4.6875)

William Sandqvist william@kth.se IEEE – 32 bit float Dec  IEEE-754 By using the exess–127 format for the exponent, we can compare floats as if they were sign and magnitude integers!

William Sandqvist william@kth.se

5-4 Cache conflict misses for (i = 0; i < 50; i++) for(j = 0; j < 4; j++) x[i][j] = a[i][j] * c[i]; Data cache 1 k Word (Word = 32 bit). Cache line 4 Words. Conflict misses depending on memory placement of x and a ?

William Sandqvist william@kth.se Memory – Cache adressmapping Memorys are often Byte- organized, but we could draw it as if it was organized in Memory-lines with the same size as the Cache-line. Direct addressmapping: Memory-line: i  Cache-line: j = i % K If the CPU needs a data-item in a line, the whole line is transfered fom memory to cache.

William Sandqvist william@kth.se a and x always conflict miss … Conflict miss if the distans between the startaddress in memory of a and of x is a multiple of 1 k Words, 4096 Bytes. for(j = 0; j < 4; j++) x[i][j] = a[i][j] * c[i];

William Sandqvist william@kth.se a and x conflict miss 1:4 … for(j = 0; j < 4; j++) x[i][j] = a[i][j] * c[i]; Conflict miss 1:4 if the distans between the startaddress in memory of a and of x is a multiple of 1 k Words  3 Words, 4096 Bytes  12 Bytes.

William Sandqvist william@kth.se a and x no conflict miss … for(j = 0; j < 4; j++) x[i][j] = a[i][j] * c[i]; No conflict miss if the distans between the startaddresses in memory of a and of x is not a multiple of 1 k Words, and not a multiple of 1 k Words  3,  2,  1 Words!

William Sandqvist william@kth.se

8-1 Arbitration 3 Masters and 4 Slaves are connected to a classical bus. Read access pattern: M1M2M3 Rd S1Rd S2Rd S4 Rd S1Rd S3 Rd S2 Sequential execution, 7 cycles needed. 1. M1  Rd S1 2. M2  Rd S2 3. M3  Rd S4 4. M2  Rd S3 5. M3  Rd S3 6. M2  Rd S2 7. M1  Rd S1 Many other alternatives are possible!

William Sandqvist william@kth.se Slave side arbitration Weighted round robin slave-side arbitration. S1S2S3S4 M11--- M2-12- M3--11 Best case execution time (3 cycles) 1.M1  Rd S1 ; M2  Rd S2 ; M3  Rd S4 2.M1  Rd S1 ; M2  Rd S3 ; 3. ; M2  Rd S2 ; M3  Rd S3 Worst case execution time (4 cycles) 1.M1  Rd S1 ; M2  Rd S2 ; M3  Rd S4 2.M1  Rd S1 ; ; M3  Rd S3 3. ; M2  Rd S3 ; 4. ; M2  Rd S2 ; Connections and weights: M1M2M3 Rd S1Rd S2Rd S4 Rd S1Rd S3 Rd S2

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