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A Combinatorial Architecture for Instruction- Level Parallelism Prepared by: HongJun Yu.

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Presentation on theme: "A Combinatorial Architecture for Instruction- Level Parallelism Prepared by: HongJun Yu."— Presentation transcript:

1 A Combinatorial Architecture for Instruction- Level Parallelism Prepared by: HongJun Yu

2 Regulated Elements By Universal Scheme (REBUS) EXECUTABLE PROGRAM Partitioned Instruction Streams Processing Elements with Replicated Scratchpad Registers Combinatorial Interconnection Structure MCU Sliced Memory Hierarchy MEMORY SYSTEM

3 Processing Elements (PE) and Memory Coordination Units (MCU) PE MCU (X1, X2, X3, X4, X5, X6, X7) using (7, 7, 3, 3,1) Reg ……

4 Structure of MCU and its connections Processing Element Processing Element Processing Element To other MCUs To and From Main Memory Unit Controller Scratchpad Registers Cache Memory

5 Structure of PE Processor With Private Memory Global Signals Management Queues of Scratchpad Copies MCU Interface R1 R2 R3

6 Pairwise-balanced combinatorial interconnection X={x 1, X2, X3, X4, X5, X6, X7, X8, X9} a Balanced Incomplete Block (BIB) with configuration (b, v, r, k, λ) X={x 1, X2, X3, X4, X5, X6, X7, X8, X9} a Balanced Incomplete Block (BIB) with configuration (b, v, r, k, λ) v : element number; b: number of k- subsets; r: each element appears exactly in r subsets; λ : each pair of elements appears exactly in λ subsets v : element number; b: number of k- subsets; r: each element appears exactly in r subsets; λ : each pair of elements appears exactly in λ subsets v*r=b*k v*r=b*k For example (12,9,4,3,1) is a BIB For example (12,9,4,3,1) is a BIB

7 Cont’ A program can be partitioned amongst the PEs by having an instruction ’ s operand pair determine the PE to which the instruction should be designated A program can be partitioned amongst the PEs by having an instruction ’ s operand pair determine the PE to which the instruction should be designated ADD R1 R7 ADD R1 R7 MULT R2 R6 MULT R2 R6 DIV R4 R5 DIV R4 R5 PE #1 PE #5 PE #2

8 Excellent ideas: Implementing ultra parallelism using balanced incomplete block(BIB); Implementing ultra parallelism using balanced incomplete block(BIB); Expand parallelism from instruction level to assembly code level; Expand parallelism from instruction level to assembly code level; Parallelism is not restricted in a small size “ window ” of code; Parallelism is not restricted in a small size “ window ” of code; Support parallelism among a group of connected processors; Support parallelism among a group of connected processors; Compatible to current technologies using in compiler and superscalar. Compatible to current technologies using in compiler and superscalar. Could benefit to both RISC and CISC. Could benefit to both RISC and CISC.

9 Characteristics: Using fixed format of assembly code; Using fixed format of assembly code; Usage of memory coordination units (MCU); Usage of memory coordination units (MCU); Need data replication Need data replication

10 Future work Apply on multi-threaded processing Apply on multi-threaded processing Various instruction format support Various instruction format support


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