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Lec 12Systems Architecture1 Systems Architecture Lecture 12: Design of the MIPS ALU Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all.

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Presentation on theme: "Lec 12Systems Architecture1 Systems Architecture Lecture 12: Design of the MIPS ALU Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all."— Presentation transcript:

1 Lec 12Systems Architecture1 Systems Architecture Lecture 12: Design of the MIPS ALU Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software Approach, Third Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 2004 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED).

2 Lec 12Systems Architecture2 Introduction Objective: To learn what operations are performed by the Arithmetic Logic Unit (ALU) and to learn how the MIPS ALU is implemented. Topics –MIPS logical operations –Full Adder –1-But ALU –The design of the MIPS 32-Bit ALU –Overflow and Overflow Detection –Carry Lookahead

3 Lec 12Systems Architecture3 Addition and Subtraction Carry-ripple adder

4 Lec 12Systems Architecture4 Overflow Detection Overflow occurs in the following situations

5 Lec 12Systems Architecture5 Logical Operations Shift left << sll Shift right >> srl Shift right arithmetic sra Bitwise and & and, andi Bitwise or | or, ori Bitwise complement (not) ~ not (pseudo) Exclusive or ^ xor, xori

6 Lec 12Systems Architecture6 Representation of Shift Instruction Example sll$t2, $s0, 8 # $t2 = $s0 << 8 $t2 = $10, $s0 = $ op rs rt rd shamt func

7 Lec 12Systems Architecture7 Example use of Logical Operations Int data; struct { unsigned int ready: 1; unsigned int enable: 1; unsigned int receivedByte: 8; } receiver; … data = receiver.receivedByte; receiver.ready = 0; receiver.enable = 1; Assume data in $s0 receiver in $s1 sll $s0, $s1, 22 srl $s0, $s0, 24 andi $s1, $s1, 0xfffe ori $s1, $s1, 0x | receivedByte | enable | ready

8 Lec 12Systems Architecture8 Building Blocks

9 Lec 12Systems Architecture9 Full Adder Sum = parity(a, b, CarryIn) –a xor b xor c + a  b  c  a xor b xor c CarryOut = majority(a, b, CarryIn) –b  CarryIn + a  CarryIn + a  b + a  b  CarryIn  –b  CarryIn + a  CarryIn + a  b b a CarryIn Sum

10 Lec 12Systems Architecture10 One-Bit ALU

11 Lec 12Systems Architecture11 Building a 32-Bit ALU Chain 32 1-Bit ALUs

12 Lec 12Systems Architecture12 Supporting Subtraction Subtraction is equivalent to adding the inverse –In two’s complement a + b + 1

13 Lec 12Systems Architecture13 Overflow and SLT Modify last 1-Bit ALU –SLT set if (a < b)  a - b < 0 –Check sign bit after subtraction –Check overflow in last 1-Bit ALU –Need to take overflow into account for SLT

14 Lec 12Systems Architecture14 Overflow and SLT Overflow? –How do we check for overflow? –What do we do with slt if we encounter overflow?

15 Lec 12Systems Architecture15 Overflow and SLT When adding two positive numbers and a final carry out is produced, is this overflow? –Yes! This is intuitive. When adding two negative numbers and a final carry out is produced, is this overflow? –No! Recall 2’s complement sign extend proof and the (x + -x) example. –A final carry out is expected. Notice the carry in to the most significant (sign) bit ALU in each case and derive an overflow formula that will work in all cases. When overflow occurs, what happens to the SLT signal? Derive this as well.

16 Lec 12Systems Architecture16 32-Bit ALU with Sub and Slt

17 Lec 12Systems Architecture17 Support Beq a = b  a - b = 0 Zero = (Result31 +    + Result0)

18 Lec 12Systems Architecture18 Final 32-Bit ALU

19 Lec 12Systems Architecture19 Carry Lookahead Adder Why is it easy to add in your head? Why is it harder to add ? If there are no carries (or if we can figure them out a priori), we can compute the additions themselves in parallel. As it stands now, we must ripple the carries through each ALU, causing a linear time addition. This extra time is spent propagating the carry out to the next carry in. By computing the carry in advance, we can improve addition to logarithmic time.

20 Lec 12Systems Architecture20 Carry Lookahead Adder In binary addition there are only a few possible cases: –1 + 1 (a = b = 1) –0 + 0 (a = b = 0) –0 + 1 or (a xor b) Notice! –The a = b = 1 case will always produce a carry out (Cout = 1), regardless of the carry in –The a = b = 0 case will never produce a carry out (Cout = 0), regardless of the carry in –The a xor b case will result in Cout = Cin The result is the carry status (generate, kill, propagate) Carry status signals can be combined (for example, generate followed by a kill is a kill)

21 Lec 12Systems Architecture21 Carry Lookahead Adder if (a i-1 = b i-1 =0) then c i = 0 “kill” if (a i-1 = b i-1 =1) then c i = 1 “generate” if (a i-1  b i-1 ) then c i = c i-1 “propagate” + a i-1 b i-1 c i-1 cici

22 Lec 12Systems Architecture22 Carry Lookahead Adder We can logically define these carry status signals as: –Generate Signal Gi = Ai AND Bi –Propagate Signal Pi = Ai XOR Bi Now how do we compute Carry Out?

23 Lec 12Systems Architecture23 Carry Lookahead Adder Cout i = G i OR (P i AND Cin i ) But recall that Cin i is really the previous Cout i-1, and we can compute that as G i-1 OR (P i-1 AND Cin i-1 ) How did we define G and P? Can you write the recursive formula in terms of A and B only? If so, we can compute this fast.

24 Lec 12Systems Architecture24 Combined Carry Status x i = kill if (a i-1 = b i-1 ) x i = generate if (a i-1 = b i-1 ) x i = propagate if (a i-1  b i-1 ) y i = y i-1  x i = x 1    x i FA i-1 FA i + aiai bibi c i+1 + a i-1 b i-1 c i-1

25 Lec 12Systems Architecture25 Calculating Carry from Carry Status Lemma: –y i = kill  c i = 0 –y i = generate  c i = 1 –y i = propagate does not occur Proof: 1y i = kill  x i = kill  c i = 0 or –x i = propagate and y i-1 = kill and c i = majority(c i-1, a i, b i ) = c i-1 = kill (by induction) 2y i = generate  x i = generate  c i = 1 or –x i = propagate and y i-1 = generate and c i = majority(c i-1, a i, b i ) = 1 (by induction) 3y i = propagate  x i = propagate and y i-1 = propagate, which by induction leads to a contradiction

26 Lec 12Systems Architecture26 Characterize Carry in Parallel Fast (parallel computation of y i in log time) x0 x1 x2 x3 x4 x5 x6 x7 [0,1] [1,2] [2,3] [3,4] [4,5] [5,6] [6,7] [0,2] [0,3] [1,4] [2,5] [3,6] [4,7] [0,0] [0,1] [0,2] [0,3] [0,4] [0,5] [0,6] [0,7]


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