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Published byTaylor Sweeney Modified over 4 years ago

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**Exponential Challenges, Exponential Rewards— The Future of Moore’s Law**

Based on lecture of Shekhar Borkar Intel Fellow Circuit Research, Intel Labs

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**ISSCC 2003— Gordon Moore said…**

“No exponential is forever… But We can delay Forever”

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**Goal: 1TIPS by 2010 How do you get there? Pentium® 4 Architecture**

Pentium® Pro Architecture Pentium® Architecture 486 386 286 8086

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**Will high K happen? Would you count on it?**

Transistors Scaling Will high K happen? Would you count on it?

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**Technology has scaled well, will it in the future?**

Technology Scaling GATE Xj GATE SOURCE BODY DRAIN SOURCE DRAIN D Tox BODY Leff Dimensions scale down by 30% Doubles transistor density Oxide thickness scales down Faster transistor, higher performance Vdd & Vt scaling Lower active power Technology has scaled well, will it in the future?

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**Gate Oxide is Near Limit**

SOURCE BODY DRAIN SOURCE DRAIN Tox 70 nm BODY 70 nm Si3N4 CoSi2 130nm Transistor Will high K happen? Would you count on it?

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**Transistor Integration Capacity**

On track for 1billion transistor integration capacity

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**Transistor Integration Capacity**

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**Transistor Integration Capacity**

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**Transistor Integration Capacity**

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**Transistor Integration Capacity**

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**Exponential Challenge #1**

Subthreshold Leakage

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**Is Transistor a Good Switch?**

I = 1ma/u On I = ∞ I = 0 I ≠ 0 Sub-threshold Leakage Off I = 0

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**Sub-threshold Leakage**

Assume: 0.25mm, Ioff = 1na/m 5X increase each generation at 30ºC Sub-threshold leakage increases exponentially

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**Leakage power limits Vt scaling**

A. Grove, IEDM 2002 Leakage power limits Vt scaling

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The Power Crisis

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**Exponential Challenge #4**

Variations

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**Optimize each circuit for performance and power**

Impact on Path Delays Delay Probability Path Delay Due to variations in: Vdd, Vt, and Temp Path delay variability due to technological variations Impacts individual circuit performance and power Optimize each circuit for performance and power

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**Optimize each circuit for performance and power**

Impact on Path Delays Delay Probability Path Delay Due to variations in: Vdd, Vt, and Temp Path delay variability due to technological variations Impacts individual circuit performance and power How many silicon atoms (111pm) have on transistor channel (20nm)? 3D transistor is a solution? Optimize each circuit for performance and power

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**Shift in Design Paradigm**

From deterministic design to probabilistic and statistical design A path delay estimate is probabilistic (not deterministic) Multi-variable design optimization for Parameter variations Active and leakage power Performance

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**Exponential Challenge #6**

Economics

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**Exponential Costs Litho Cost FAB Cost $ per Transistor $ per MIPS**

G. Moore ISSCC 03 Litho Cost FAB Cost $ per Transistor $ per MIPS

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**Some Implications Tox scaling will slow down—may stop?**

Vdd scaling will slow down—may stop? Vt scaling will slow down—may stop? Approaching constant Vdd scaling Energy/logic op will not scale

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The Terascale Dilemma Many billion transistor integration capacity will be available But could be unusable due to power Logic transistor growth will slow down Transistor performance will be limited Solutions Low power design techniques Improve design efficiency

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**Exponential Challenge #5**

Platform & System

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**Platform Requirements**

500 1000 1500 2000 2500 3000 PC tower Mini tower m-tower Slim line Small pc System Volume ( cubic inch) Shrinking volume Quieter Yet, High Performance 0.5 1.0 1.5 50 100 150 200 Power (W) Thermal Budget (oC/W) 25 75 Heat-Sink Volume (in3) Projected Heat Dissipation Volume Projected Air Flow Rate Pentium ® III 250 Thermal Budget Air Flow Rate (CFM) Pentium ® 4 Thermal budget decreasing Higher heat sink volume Higher air flow rate

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**Active Power Reduction**

Slow Fast Low Supply Voltage High Supply Multiple Vdd Throughput oriented design Logic Block Freq = 1 Vdd = 1 Throughput = 1 Power = 1 Area = 1 Pwr Den = 1 Vdd Logic Block Freq = 0.5 Vdd = 0.5 Throughput = 1 Power = 0.25 Area = 2 Pwr Den = 0.125 Vdd/2

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**Design & mArch Efficiency**

Employ efficient design & mArchitectures

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**Improve mArch Efficiency**

Thermals & Power Delivery designed for full HW utilization Single Thread ST Wait for Mem Multi-Threading MT1 Wait for Mem MT2 Wait MT3 Multi-threading improves performance without impacting thermals & power delivery

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**Increase on-die Memory**

Large on die memory provides: Increased Data Bandwidth & Reduced Latency Hence, higher performance for much lower power

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**Chip Multi-Processing**

Cache Multi-core, each core Multi-threaded Shared cache and front side bus Each core has different Vdd & Freq Spreading hot spots Lower junction temperature

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**Example (Itanium Tukwila)**

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**Example (Itanium Tukwila)**

130 Watts 30 MBytes cache

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**Example (Itanium Tukwila)**

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**What the Cores Will look like?**

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**What the Cores Will look like?**

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**What the Cores Will look like?**

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**What the Cores Will look like?**

clocks run with the same frequency but unknown phases

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**What the Cores Will look like?**

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**What the Cores Will look like?**

Improvement of energy efficiency Intelligent redistribution workload Multiple functionalities

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**What the Cores Will look like?**

Several interconnection possibilities Mesh Ring

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Tera-Scale RMS - Recognition, Mining and Synthesis

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Tera-Scale

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Tera-Scale

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Tera-Scale

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**The Exponential Reward**

Multi Threaded Era of Thread & Processor Level Parallelism Special Purpose HW Multi-Threaded, Multi-Core Speculative, OOO Era of Instruction Level Parallelism Super Scalar 486 386 286 8086 Era of Pipelined Architecture

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**Summary—Delaying Forever**

Terascale transistor integration capacity will be available - Power and Energy are the barriers Variations will be even more prominent - shift from Deterministic to Probabilistic design Improve design efficiency Exploit integration capacity to deliver performance in power/cost envelope

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Exercícios Discuta um problema associados a integração dos dispositivos Comente a afirmação: - “A redução do tamanho dos transistores muda o paradigma de avaliação de consumo de energia e tempo de execução de determinístico para probabilístico” Porque o consumo de energia estático é tão problemático para as tecnologias futuras? Porque a redução da voltagem é um dos principais elementos a tratar para reduzir o consumo de energia? Como um sistema com várias alimentações pode contribuir para a redução do consumo de energia? Qual o efeito sobre o tempo de execução?

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Exercícios Faça uma ilustração que mostre como um programa multi-thread pode ocupar melhor os recursos de um sistema, reduzindo o gargalo de comunicação com a memória Qual o motivo do percentual de memória interno a um circuito integrado passar de 50% nos processadores atuais? Dada a limitação do escalamento, o que pode ser feito para continuar o crescente aumento do desempenho das máquinas? Quais as tendências em termos de computação (cores), infra-estrutura de comunicação e armazenamento para os próximos processadores?

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PP Test Review Sections 6-1 to 6-6

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