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MMU Memory Management Unit Chapter # 14 Memory Management Unit1.

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1 MMU Memory Management Unit Chapter # 14 Memory Management Unit1

2 Group#13 Asmaa Rabie Abdualaziz Islam Ameen Abdualaziz Doaa Ahmed Mohamed Sherif Mohamed Medhat 2 Memory Management Unit Presented by: Presented to Presented to : Dr.Amr Wassal CMP 2012

3 Agenda 1. What we will learn from chapter ?1. What we will learn from chapter ? 2. Introduction2. Introduction 3. Moving From An MPU To An MMU3. Moving From An MPU To An MMU 4. How Virtual Memory works4. How Virtual Memory works 4.1 The components of a virtual memory system 4.1 The components of a virtual memory system 4.2 Defining Regions Using Pages 4.2 Defining Regions Using Pages 4.3 Multitasking and The MMU 4.3 Multitasking and The MMU 4.4Memory Organization in a Virtual Memory System 5. Details Of The ARM MMU5. Details Of The ARM MMU 6. Page Table6. Page Table 6.1 Level Level Translation Table Base Address 6.2 Translation Table Base Address 6.3 Level Level 2 7. Translation Lookaside Buffer7. Translation Lookaside Buffer 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.3 TLB Operations 7.3 TLB Operations 8. Domain & Access permission8. Domain & Access permission 9. Caches and Write Buffer9. Caches and Write Buffer 10.Coprocessor 15 and MMU configuration10. Coprocessor 15 and MMU configuration 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE) 12. A small virtual memory system12. A small virtual memory system 3 Memory Management Unit

4 What will we learn from chapter? Learn basics of ARM MMU and some basic concepts that underlie the use of the virtual memory 4 Memory Management Unit

5 Agenda 1. What we will learn from chapter ?1. What we will learn from chapter ? 2. Introduction2. Introduction 3. Moving From An MPU To An MMU3. Moving From An MPU To An MMU 4. How Virtual Memory works4. How Virtual Memory works 4.1 The components of a virtual memory system 4.1 The components of a virtual memory system 4.2 Defining Regions Using Pages 4.2 Defining Regions Using Pages 4.3 Multitasking and The MMU 4.3 Multitasking and The MMU 4.4Memory Organization in a Virtual Memory System 5. Details Of The ARM MMU5. Details Of The ARM MMU 6. Page Table6. Page Table 6.1 Level Level Translation Table Base Address 6.2 Translation Table Base Address 6.3 Level Level 2 7. Translation Lookaside Buffer7. Translation Lookaside Buffer 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.3 TLB Operations 7.3 TLB Operations 8. Domain & Access permission8. Domain & Access permission 9. Caches and Write Buffer9. Caches and Write Buffer 10.Coprocessor 15 and MMU configuration10. Coprocessor 15 and MMU configuration 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE) 12. A small virtual memory system12. A small virtual memory system 5 Memory Management Unit

6 Virtual addresses: Assign by Compiler and Linker Physical addresses : Access the actual hardware components Introduction 6 Memory Management Unit

7 Agenda 1. What we will learn from chapter ?1. What we will learn from chapter ? 2. Introduction2. Introduction 3. Moving From An MPU To An MMU3. Moving From An MPU To An MMU 4. How Virtual Memory works4. How Virtual Memory works 4.1 The components of a virtual memory system 4.1 The components of a virtual memory system 4.2 Defining Regions Using Pages 4.2 Defining Regions Using Pages 4.3 Multitasking and The MMU 4.3 Multitasking and The MMU 4.4Memory Organization in a Virtual Memory System 5. Details Of The ARM MMU5. Details Of The ARM MMU 6. Page Table6. Page Table 6.1 Level Level Translation Table Base Address 6.2 Translation Table Base Address 6.3 Level Level 2 7. Translation Lookaside Buffer7. Translation Lookaside Buffer 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.3 TLB Operations 7.3 TLB Operations 8. Domain & Access permission8. Domain & Access permission 9. Caches and Write Buffer9. Caches and Write Buffer 10.Coprocessor 15 and MMU configuration10. Coprocessor 15 and MMU configuration 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE) 12. A small virtual memory system12. A small virtual memory system 7 Memory Management Unit

8 Moving From An MPU To An MMU 8 Memory Management Unit What is the difference between active and dormant region? Difference Between MPU & MMU

9 Agenda 1. What we will learn from chapter ?1. What we will learn from chapter ? 2. Introduction2. Introduction 3. Moving From An MPU To An MMU3. Moving From An MPU To An MMU 4. How Virtual Memory works4. How Virtual Memory works 4.1 The components of a virtual memory system 4.1 The components of a virtual memory system 4.2 Defining Regions Using Pages 4.2 Defining Regions Using Pages 4.3 Multitasking and The MMU 4.3 Multitasking and The MMU 4.4Memory Organization in a Virtual Memory System 5. Details Of The ARM MMU5. Details Of The ARM MMU 6. Page Table6. Page Table 6.1 Level Level Translation Table Base Address 6.2 Translation Table Base Address 6.3 Level Level 2 7. Translation Lookaside Buffer7. Translation Lookaside Buffer 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.3 TLB Operations 7.3 TLB Operations 8. Domain & Access permission8. Domain & Access permission 9. Caches and Write Buffer9. Caches and Write Buffer 10.Coprocessor 15 and MMU configuration10. Coprocessor 15 and MMU configuration 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE) 12. A small virtual memory system12. A small virtual memory system 9 Memory Management Unit

10 How Virtual Memory works 0x e3 0x e3 10 Memory Management Unit

11 The components of a virtual memory system Virtual memoryPhysical memory MMU Relocation register Page Page frame Page tables PTE 11 Memory Management Unit

12 Defining Regions Using Pages Defining Regions Using Pages Stack Data Text Region 3 Region 2 Region 1 Virtual Memory Physical Memory Page tables RAM Flash PTEPage Page frame 12 Memory Management Unit

13 13

14 Memory Management Unit 14

15 Agenda 1. What we will learn from chapter ?1. What we will learn from chapter ? 2. Introduction2. Introduction 3. Moving From An MPU To An MMU3. Moving From An MPU To An MMU 4. How Virtual Memory works4. How Virtual Memory works 4.1 The components of a virtual memory system 4.1 The components of a virtual memory system 4.2 Defining Regions Using Pages 4.2 Defining Regions Using Pages 4.3 Multitasking and The MMU 4.3 Multitasking and The MMU 4.4Memory Organization in a Virtual Memory System 5. Details Of The ARM MMU5. Details Of The ARM MMU 6. Page Table6. Page Table 6.1 Level Level Translation Table Base Address 6.2 Translation Table Base Address 6.3 Level Level 2 7. Translation Lookaside Buffer7. Translation Lookaside Buffer 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.3 TLB Operations 7.3 TLB Operations 8. Domain & Access permission8. Domain & Access permission 9. Caches and Write Buffer9. Caches and Write Buffer 10.Coprocessor 15 and MMU configuration10. Coprocessor 15 and MMU configuration 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE) 12. A small virtual memory system12. A small virtual memory system 15 Memory Management Unit

16 Page tables Translation Lookaside Table (TLB) Domain and access permission Caches and write buffer CP15: c1 control register Fast Context Switch Extension Details Of The ARM MMU 16 Memory Management Unit

17 Agenda 1. What we will learn from chapter ?1. What we will learn from chapter ? 2. Introduction2. Introduction 3. Moving From An MPU To An MMU3. Moving From An MPU To An MMU 4. How Virtual Memory works4. How Virtual Memory works 4.1 The components of a virtual memory system 4.1 The components of a virtual memory system 4.2 Defining Regions Using Pages 4.2 Defining Regions Using Pages 4.3 Multitasking and The MMU 4.3 Multitasking and The MMU 4.4Memory Organization in a Virtual Memory System 5. Details Of The ARM MMU5. Details Of The ARM MMU 6. Page Table6. Page Table 6.1 Level Level Translation Table Base Address 6.2 Translation Table Base Address 6.3 Level Level 2 7. Translation Lookaside Buffer7. Translation Lookaside Buffer 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.3 TLB Operations 7.3 TLB Operations 8. Domain & Access permission8. Domain & Access permission 9. Caches and Write Buffer9. Caches and Write Buffer 10.Coprocessor 15 and MMU configuration10. Coprocessor 15 and MMU configuration 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE) 12. A small virtual memory system12. A small virtual memory system 17 Memory Management Unit

18 L1 Entries for translating 1 MB pages Pointers to the starting address to level 2 page tables L2 Fine page table Coarse page table Page Table 18 Memory Management Unit

19 Level 1 page table accepts four types of entry A 1MB section translation entry A directory entry that points to a fine L2 page table A directory entry that points to a coarse L2 page table A fault entry that generates an abort exception Level 1 19 Memory Management Unit

20 L1 page entries The upper 12 bits of the page table entry replace the upper 12 bits of the virtual address to generate the physical address Domain Access Permission Buffered Cached Section Entry 20 Memory Management Unit

21 L1 page entries a pointer to the base address of a second-level coarse page table Coarse Entry Domain information for the 1 MB section of virtual memory represented by the L1 table entry. 21 Memory Management Unit

22 L1 page entries a pointer to the base address of a second-level fine page table Fine Entry Domain information for the 1 MB section of virtual memory represented by the L1 table entry. 22 Memory Management Unit

23 L1 page entries Fault Entry 23 Memory Management Unit

24 Translation Table Base Address The CP15:c2 register holds the translation table base address (TTB)—an address pointing to the location of the master L1 table in virtual memory. 24 Memory Management Unit

25 Level 2 page table accepts four types of entry A large page entry defines the attributes for a 64 KB page frame. A small page entry defines a 4 KB page frame. A tiny page entry defines a 1 KB page frame. A fault page entry generates a page fault abort exception when accessed. Level 2 25 Memory Management Unit

26 L2 page entries The entry also has four sets of permission bit fields A large PTE includes the base address of a 64 KB block of physical memory. Large page 26 Memory Management Unit

27 L2 page entries The entry also has four sets of permission bit fields A small PTE holds the base address of a 4 KB block of physical memory Small page 27 Memory Management Unit

28 L2 page entries The entry also has 1 permission bit fields A tiny PTE provides the base address of a 1 KB block of physical memory. Small page 28 Memory Management Unit

29 Fault L2 page entries 29 Memory Management Unit

30 Agenda 1. What we will learn from chapter ?1. What we will learn from chapter ? 2. Introduction2. Introduction 3. Moving From An MPU To An MMU3. Moving From An MPU To An MMU 4. How Virtual Memory works4. How Virtual Memory works 4.1 The components of a virtual memory system 4.1 The components of a virtual memory system 4.2 Defining Regions Using Pages 4.2 Defining Regions Using Pages 4.3 Multitasking and The MMU 4.3 Multitasking and The MMU 4.4Memory Organization in a Virtual Memory System 5. Details Of The ARM MMU5. Details Of The ARM MMU 6. Page Table6. Page Table 6.1 Level Level Translation Table Base Address 6.2 Translation Table Base Address 6.3 Level Level 2 7. Translation Lookaside Buffer7. Translation Lookaside Buffer 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.3 TLB Operations 7.3 TLB Operations 8. Domain & Access permission8. Domain & Access permission 9. Caches and Write Buffer9. Caches and Write Buffer 10.Coprocessor 15 and MMU configuration10. Coprocessor 15 and MMU configuration 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE) 12. A small virtual memory system12. A small virtual memory system 30 Memory Management Unit

31 Translation Lookaside Buffer Fully associative cache of recently used translations Stores Access permission set Use round-robin replacement algorithm Supports flush and lock operations 31 Memory Management Unit

32 L1 Page table virtual-to-physical memory translation using 1 MB sections L1 master page table Selects physical memory Base offset Base Page table entry Translation table base address Virtual address physical address Copied to TLB 32 Memory Management Unit

33 Two-level virtual-to-physical address translation using coarse page tables L1 master page table Coarse L2 page table L1 Page table entry L2 Page table entry Virtual address physical address Physical Base Page offset L2 offset L1 offset Step 1 Step 2 Copied to TLB L2 Page table base address Translation table base address 33 Memory Management Unit

34 TLB Operations 42f ab56 35de 9001 f8d fd Flush fd3 Lock down 34 Memory Management Unit

35 Agenda 1. What we will learn from chapter ?1. What we will learn from chapter ? 2. Introduction2. Introduction 3. Moving From An MPU To An MMU3. Moving From An MPU To An MMU 4. How Virtual Memory works4. How Virtual Memory works 4.1 The components of a virtual memory system 4.1 The components of a virtual memory system 4.2 Defining Regions Using Pages 4.2 Defining Regions Using Pages 4.3 Multitasking and The MMU 4.3 Multitasking and The MMU 4.4Memory Organization in a Virtual Memory System 5. Details Of The ARM MMU5. Details Of The ARM MMU 6. Page Table6. Page Table 6.1 Level Level Translation Table Base Address 6.2 Translation Table Base Address 6.3 Level Level 2 7. Translation Lookaside Buffer7. Translation Lookaside Buffer 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.3 TLB Operations 7.3 TLB Operations 8. Domain & Access permission8. Domain & Access permission 9. Caches and Write Buffer9. Caches and Write Buffer 10.Coprocessor 15 and MMU configuration10. Coprocessor 15 and MMU configuration 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE) 12. A small virtual memory system12. A small virtual memory system 35 Memory Management Unit

36 Domain & Access permission There are two different controls to manage a task’s access permission to memory. Primary: is the Domain. Secondary: is access permission set in the page tables. Domain control basic access to virtual memory by isolating on area of memory from another when sharing common virtual memory map 36 Memory Management Unit

37 Domain bit access bit assignment 37 Memory Management Unit

38 Page Table-Based Access permission 38 Memory Management Unit

39 Agenda 1. What we will learn from chapter ?1. What we will learn from chapter ? 2. Introduction2. Introduction 3. Moving From An MPU To An MMU3. Moving From An MPU To An MMU 4. How Virtual Memory works4. How Virtual Memory works 4.1 The components of a virtual memory system 4.1 The components of a virtual memory system 4.2 Defining Regions Using Pages 4.2 Defining Regions Using Pages 4.3 Multitasking and The MMU 4.3 Multitasking and The MMU 4.4Memory Organization in a Virtual Memory System 5. Details Of The ARM MMU5. Details Of The ARM MMU 6. Page Table6. Page Table 6.1 Level Level Translation Table Base Address 6.2 Translation Table Base Address 6.3 Level Level 2 7. Translation Lookaside Buffer7. Translation Lookaside Buffer 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.3 TLB Operations 7.3 TLB Operations 8. Domain & Access permission8. Domain & Access permission 9. Caches and Write Buffer9. Caches and Write Buffer 10.Coprocessor 15 and MMU configuration10. Coprocessor 15 and MMU configuration 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE) 12. A small virtual memory system12. A small virtual memory system 39 Memory Management Unit

40 Caches and Write Buffer 40 Memory Management Unit

41 Agenda 1. What we will learn from chapter ?1. What we will learn from chapter ? 2. Introduction2. Introduction 3. Moving From An MPU To An MMU3. Moving From An MPU To An MMU 4. How Virtual Memory works4. How Virtual Memory works 4.1 The components of a virtual memory system 4.1 The components of a virtual memory system 4.2 Defining Regions Using Pages 4.2 Defining Regions Using Pages 4.3 Multitasking and The MMU 4.3 Multitasking and The MMU 4.4Memory Organization in a Virtual Memory System 5. Details Of The ARM MMU5. Details Of The ARM MMU 6. Page Table6. Page Table 6.1 Level Level Translation Table Base Address 6.2 Translation Table Base Address 6.3 Level Level 2 7. Translation Lookaside Buffer7. Translation Lookaside Buffer 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.3 TLB Operations 7.3 TLB Operations 8. Domain & Access permission8. Domain & Access permission 9. Caches and Write Buffer9. Caches and Write Buffer 10.Coprocessor 15 and MMU configuration10. Coprocessor 15 and MMU configuration 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE) 12. A small virtual memory system12. A small virtual memory system 41 Memory Management Unit

42 Coprocessor 15 and MMU configuration 42 Memory Management Unit

43 Agenda 1. What we will learn from chapter ?1. What we will learn from chapter ? 2. Introduction2. Introduction 3. Moving From An MPU To An MMU3. Moving From An MPU To An MMU 4. How Virtual Memory works4. How Virtual Memory works 4.1 The components of a virtual memory system 4.1 The components of a virtual memory system 4.2 Defining Regions Using Pages 4.2 Defining Regions Using Pages 4.3 Multitasking and The MMU 4.3 Multitasking and The MMU 4.4Memory Organization in a Virtual Memory System 5. Details Of The ARM MMU5. Details Of The ARM MMU 6. Page Table6. Page Table 6.1 Level Level Translation Table Base Address 6.2 Translation Table Base Address 6.3 Level Level 2 7. Translation Lookaside Buffer7. Translation Lookaside Buffer 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.3 TLB Operations 7.3 TLB Operations 8. Domain & Access permission8. Domain & Access permission 9. Caches and Write Buffer9. Caches and Write Buffer 10.Coprocessor 15 and MMU configuration10. Coprocessor 15 and MMU configuration 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE) 12. A small virtual memory system12. A small virtual memory system 43 Memory Management Unit

44 Fast Context Switch Extension (FCSE) Enables multiple independent tasks to run in a fixed overlapping area of memory FCSE eliminates the need of flushing the cache and TLB Uses process ID to convert overlapping virtual address(VA) to a unique modified virtual address(MVA) MVA = VA + (0x * process ID) Memory Management Unit 44

45 1. Save active tasks context and put the task in dormant state 2.Write the awakening task’s process ID to CP15:c13 3.Locate set the current tasks' domain to no access and the awakening task’s domain to client access by writing to cp15:c3:c0 4.Restore the context of awakening task 5.Resume execution of re stored task Steps to perform context switch when using FCSE 45 Memory Management Unit

46 Agenda 1. What we will learn from chapter ?1. What we will learn from chapter ? 2. Introduction2. Introduction 3. Moving From An MPU To An MMU3. Moving From An MPU To An MMU 4. How Virtual Memory works4. How Virtual Memory works 4.1 The components of a virtual memory system 4.1 The components of a virtual memory system 4.2 Defining Regions Using Pages 4.2 Defining Regions Using Pages 4.3 Multitasking and The MMU 4.3 Multitasking and The MMU 4.4Memory Organization in a Virtual Memory System 5. Details Of The ARM MMU5. Details Of The ARM MMU 6. Page Table6. Page Table 6.1 Level Level Translation Table Base Address 6.2 Translation Table Base Address 6.3 Level Level 2 7. Translation Lookaside Buffer7. Translation Lookaside Buffer 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.1 L1 Page table virtual-to-physical memory translation using 1 MB sections 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.2 Two-level virtual-to-physical address translation using coarse page tables 7.3 TLB Operations 7.3 TLB Operations 8. Domain & Access permission8. Domain & Access permission 9. Caches and Write Buffer9. Caches and Write Buffer 10.Coprocessor 15 and MMU configuration10. Coprocessor 15 and MMU configuration 11. Fast Context Switch Extension (FCSE)11. Fast Context Switch Extension (FCSE) 12. A small virtual memory system12. A small virtual memory system 46 Memory Management Unit

47 3 Tasks The same execution region 256 MB of memory for peripheral devices Very simple example! A small virtual memory system 47 Memory Management Unit

48 1.Define a fixed system software region 2.Define 3 virtual memory maps for the 3 tasks 3.Locate regions in step 1 & 2 into the physical memory 4.Define and locate the page tables within the page table region 5.Data structures for regions and page tables 6.Initialize the MMU, caches, and write buffer 7.Set up a context switch routine to switch between tasks How to setup the MMU? 48 Memory Management Unit

49 16 KB for the master table 1 KB each for the four L2 tables. 12 KB free memory Shared libraries The transition routines for switching from privileged mode to user mode during a context switch The OS kernel code and data Fixed addressing to avoid the complexity of remapping when changing to a system mode context. 1- Fixed system software region 1MB 32 KB Controls the system device I/O space Noncached & Nonbuffered region 49 Memory Management Unit

50 2- Define Virtual Memory Maps for Each Task 32 KB Text, data, and stack of the running user task. Remap the Task region on task switch Discussed! 50 Memory Management Unit

51 3- Locate Regions in Physical Memory 51 Memory Management Unit

52 4- Define and Locate the Page Tables 52 Memory Management Unit

53 5- Define Page Table and Region Data Structures 53 Memory Management Unit 1)Page Table struct typedef struct { unsigned int vAddress; //Address of a 1 MBsection of virtual memory unsigned int ptAddress; //Location in virtual memory. unsigned int masterPtAddress; //Address of the parent master L1 page table. unsigned int type; //COARSE, FINE, or MASTER unsigned int dom; // Domain value } Pagetable;

54 5- Define Page Table and Region Data Structures 1)Page Table struct typedef struct { unsigned int vAddress; //Address of a 1 MBsection of virtual memory unsigned int ptAddress; //Location in virtual memory. unsigned int masterPtAddress; //Address of the parent master L1 page table. unsigned int type; //COARSE, FINE, or MASTER unsigned int dom; // Domain value } Pagetable; 54 Memory Management Unit

55 5- Define Page Table and Region Data Structures Example: /* vAddress, ptAddress, masterPtAddress, t ype, dom */ Pagetable systemPT = {0x , 0x1c000, 0x18000, COARSE, 3}; 55 Memory Management Unit

56 5- Define Page Table and Region Data Structures 1)Region struct typedef struct { unsigned int vAddress; // Address of the region in virtual memory unsigned int pageSize; //Size of a virtual page unsigned int numPages; // Number of pages in the region unsigned int AP; // Region access permissions unsigned int CB; // Cache and write buffer attribute unsigned int pAddress; // Address of the region in virtual memory Pagetable *PT; // pointer to the Pagetable in which the region resides } Region; 56 Memory Management Unit

57 5- Define Page Table and Region Data Structures Example: /* vAddress, pageSize, numPages, AP, CB, pAddress, *PT */ Region kernelRegion = {0x , 4, 16, RWNA, WT, 0x , &systemPT}; 57 Memory Management Unit

58 6- Initialize the MMU, caches, and write buffer 1.Initialize the page tables in main memory by filling them with FAULT entries 2.Fill in the page tables with translations that map regions to physical memory. 3.Activate the page tables. 4.Assign domain access rights. 5.Enable the MMU and cache hardware 58 Memory Management Unit

59 6- Initialize the MMU, caches, and write buffer 1)Initialize the page tables: mmuInitPT(Pagetable *); Fill the Page Table by Fault entries The size of the table is determined by reading the type of Page table defined in pt->type (Master, Coarse, Fine) Memory Management Unit 59

60 6- Initialize the MMU, caches, and write buffer 2)Filling Page Tables with Translations mmuMapRegion(Region * region ){ switch (region->PT->type){ case SECTION mmuMapSectionTableRegion(region); case COARSE: mmuMapCoarseTableRegion(region); case FINE: mmuMapFineTableRegion(region); } Memory Management Unit 60

61 6- Initialize the MMU, caches, and write buffer 3) Activating a Page Table Why? mmuAttachPT(Pagetable *pt); It activates an L1 master page table by placing its address into the TTB in the CP15:c2:c0 register Or activates an L2 page table by placing its base address into an L1 master page table entry Memory Management Unit 61

62 6- Initialize the MMU, caches, and write buffer 4) Assigning Domain Access and Enabling the MMU All active memory areas must have a domain assignment The minimum domain configuration places all regions in the same domain and sets the domain access to client access. void domainAccessSet(unsigned int value, unsigned int mask); Memory Management Unit 62

63 6- Initialize the MMU, caches, and write buffer 5) Enable the MMU /* Call the previous functions */ void mmuInit(){ mmuInitPT(Pagetable *); //Init the Page Tables mmuMapRegion(Region * region ) //Map The regions mmuAttachPT(Pagetable *pt); //Activate the Page Table void domainAccessSet(unsigned int value, unsigned int mask);//Set Domain Access } 63 Memory Management Unit

64 7- Establish a Context Switch Procedure 1.Save the active task context and place the task in a dormant state. 2.Flush the caches 3.Flush the TLB to remove translations for the retiring task 4.Configure the MMU to use new page tables 5.Restore the context of the awakening task 6.Resume execution of the restored task 64 Memory Management Unit

65 Any Questions 65 Memory Management Unit


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