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Quiz 4 Solution

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n Frequency = 2.5GHz, CLK = 0.4ns n CPI = 0.4, 30% loads and stores, n L1 hit =0, n L1-ICACHE : 2% miss rate, 32-byte blocks n L1-DCACHE :5% miss rate, 16-byte blocks n L2-Cache: 10% miss rate, access time:15 ns, 64-byte blocks n Memory : access time 75 ns n Miss penalty for data between L1 and L2=15ns+16/16*2.5ns=17.5ns n Miss penalty for inst between L1 and L2 =15ns+32/16*2.5ns =20ns n Miss penalty between L2 and Memory =75ns+64/16*7.5ns =105ns n Part a) n DATA_AMAT = L1 hit time+ L1 data miss rate *( L2 hit rate*(Data in L2 penalty)+L2 miss rate *(Data not in L2 but in memory penalty)) n = 0+0.05(0.9(17.5)+0.1(17.5+105))=1.4 n INST_AMAT = L1 hit time+ L1 inst miss rate *( L2 hit rate*(inst in L2 penalty)+L2 miss rate *(inst not in L2 but in memory penalty)) n = 0+0.02(0.9(20)+0.1(20+105))=0.61

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n Frequency = 2.5GHz, CLK = 0.4ns n CPI = 0.4, 30% loads and stores, n L1 hit =0, n L1-ICACHE : 2% miss rate, 32-byte blocks n L1-DCACHE :5% miss rate, 16-byte blocks n L2-Cache: 10% miss rate, access time:15 ns, 64-byte blocks n Memory : access time 75 ns n DATA_AMAT n = 0+0.05(0.9(17.5)+0.1(17.5+105))=1.4 n INST_AMAT n = 0+0.02(0.9(20)+0.1(20+105))=0.61 n Part b) n Over-all CPI= Ideal CPI+impact of data accesses+impact of inst accesses n =0.4+(0.3(AMAT_DATA)+1(AMAT_INST))xfrequency n We need to take frequency into account as this is CPI and not execution time. n =0.4+((0.3(1.4)+1(0.61))*2.5GHZ)=2.975

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n Frequency = 2.5GHz, CLK = 0.4ns n CPI = 0.4, 30% loads and stores, n L1 hit =0, n L1-ICACHE : 2% miss rate, 32-byte blocks n L1-DCACHE :5% miss rate, 16-byte blocks n L2-Cache: 10% miss rate, access time:15 ns, 64-byte blocks n Memory : access time 75 ns n Over-all CPI=0.4+((0.3(1.4)+1(0.61))*2.5GHZ)=2.975 n Part c) Replace 2.5GHZ processor w/ 3.6GHZ. Improvement? n New CPI=0.4+((0.3(1.4)+1(0.61))*3.6GHZ)=4.1 n execution time=CPI*Clock period n Improvement=old execution time/new execution time n =(2.975/2.5)/(4.1/3.6)= 1.19/1.13=1.05 n 5% improvement!

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n Part d) n 1-Bigger L1, cut missrate to half, L1 hit= 1 cycle =0.4 ns n DATA_AMAT = L1 hit time+ L1 data miss rate *( L2 hit rate*(Data in L2 penalty)+L2 miss rate *(Data not in L2 but in memory penalty)) n = 0.4+0.025(0.9(17.5)+0.1(17.5+105))=1.1 n INST_AMAT = L1 hit time+ L1 inst miss rate *( L2 hit rate*(inst in L2 penalty)+L2 miss rate *(inst not in L2 but in memory penalty)) n = 0.4+0.01(0.9(20)+0.1(20+105))=0.7 n Over-all CPI= Ideal CPI+impact of data accesses+impact of inst accesses n =0.4+(0.3(AMAT_DATA)+1(AMAT_INST))xfrequency n =0.4+(0.3(1.1)+1(0.7))*frequency=2.975. No improvement.

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n Part d) n 2-Smaller L2, L2 access time= 10, L2 miss rate=15% n Miss penalty for data between L1 and L2=10ns+16/16*2.5ns=12.5ns n Miss penalty for inst between L1 and L2 =10ns+32/16*2.5ns =15ns n DATA_AMAT = L1 hit time+ L1 data miss rate *( L2 hit rate*(Data in L2 penalty)+L2 miss rate *(Data not in L2 but in memory penalty)) n = 0+0.05(0.85(12.5)+0.15(12.5+105))=1.41 n INST_AMAT = L1 hit time+ L1 inst miss rate *( L2 hit rate*(inst in L2 penalty)+L2 miss rate *(inst not in L2 but in memory penalty)) n = 0+0.02(0.85(15)+0.15(15+105))=0.61 n Over-all CPI= Ideal CPI+impact of data accesses+impact of inst accesses n =0.4+(0.3(AMAT_DATA)+1(AMAT_INST))xfrequency n =0.4+(0.3(1.41)+1(0.61))*frequency=2.982. lose performance.

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