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KMUTT: S. Srakaew What is a “Microprocessor" KMUTT: S. Srakaew A Typical Microprocessor ALU C C A 32 310 A D D P C i n G r a W a i t 0 R0 R31 31 IR MAR.

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Presentation on theme: "KMUTT: S. Srakaew What is a “Microprocessor" KMUTT: S. Srakaew A Typical Microprocessor ALU C C A 32 310 A D D P C i n G r a W a i t 0 R0 R31 31 IR MAR."— Presentation transcript:

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2 KMUTT: S. Srakaew What is a “Microprocessor"

3 KMUTT: S. Srakaew A Typical Microprocessor ALU C C A A D D P C i n G r a W a i t 0 R0 R31 31 IR MAR To memory subsystem Data Path Main memory Memory bus Control Unit Control unit inputsControl signals out MDR PC AB bit general purpose registers Input/ output

4 KMUTT: S. Srakaew Processor, Microprocessor, and Microcontroller The processor Registers -- storage locations in the processor Arithmetic logic unit Control unit program counter keeps track of the address of the next instruction to be executed status register flags the instruction execution result The microprocessor A processor implemented on a very large scale integration (VLSI) chip Peripheral chips are needed to construct a product The Microcontroller The processor and peripheral functions implemented on one VLSI chip

5 KMUTT: S. Srakaew History of Microprocessor The 4004 Introduced date Manufacturer Register width Transistor count Form 1971 Intel 4-bit pin DIP 4-bit 12-bit None 0.74 MHz Data bus Address bus Cache Clock speed The Intel 8008 (later in 1971) An 8-bit version of 4004, with 14-bit address bus(16 KB)

6 KMUTT: S. Srakaew History of Microprocessor The The ancestor of the 80x86 and the Pentium Introduced date Manufacturer Register width Transistor count Form 1974 Intel 8-bit ~ pin DIP 8-bit 16-bit None 2 MHz Data bus Address bus Cache Clock speed

7 KMUTT: S. Srakaew History of Microprocessor Other 8-bit microprocessors in the same era as 8080 Manufacturer Fairchild National Semiconductor MOS Technology Motorola Product F-8 IMP PPS-8 Z-8 Rockwell International Zilog

8 KMUTT: S. Srakaew History of Microprocessor The The heart of Commodore and Apple II microcomputers Introduced date Manufacturer Register width Transistor count Form 1975 MOS Tech 8-bit pin DIP 8-bit 16-bit None 2 MHz Data bus Address bus Cache Clock speed

9 KMUTT: S. Srakaew History of Microprocessor The Z-80 - The heart of all PCs in the CPM era Introduced date Manufacturer Register width Transistor count Form 1976 Zilog 8-bit + 16-bit ~ pin DIP 8-bit 16-bit None MHz Data bus Address bus Cache Clock speed

10 KMUTT: S. Srakaew History of Microprocessor The The Z-80 competitor Introduced date Manufacturer Register width Transistor count Form 1977 Intel 8-bit + 16-bit pin DIP 8-bit 16-bit None 3-6 MHz Data bus Address bus Cache Clock speed

11 KMUTT: S. Srakaew History of Microprocessor The The first 16-bit version of Intel Introduced date Manufacturer Register width Transistor count Form 1978 Intel 16-bit pin DIP 16-bit 20-bit None 5-12 MHz Data bus Address bus Cache Clock speed

12 KMUTT: S. Srakaew History of Microprocessor The The chip that powered the well-known IBM PC Introduced date Manufacturer Register width Transistor count Form 1979 Intel 16-bit pin DIP 8-bit 16-bit None 4-12 MHz Data bus Address bus Cache Clock speed

13 KMUTT: S. Srakaew History of Microprocessor The The heart of the well-known Apple Macintosh Introduced date Manufacturer Register width Transistor count Form 1979 Motorola 16-bit bit None 4-12 MHz Data bus Address bus Cache Clock speed

14 KMUTT: S. Srakaew History of Microprocessor The 680X0 - The successors of the ClockVersionWidthIntroductionTransistor count 25MHz bit MHz bit MHz bit million -

15 KMUTT: S. Srakaew History of Microprocessor The The chip that powered the well-known IBM PC AT Introduced date Manufacturer Register width Transistor count Form 1982 Intel 16-bit 134, pin DIP, PGA 16-bit 24-bit None 8,10,12,16 MHz Data bus Address bus Cache Clock speed

16 KMUTT: S. Srakaew History of Microprocessor The 80386DX- The first 32-bit version of Intel Introduced date Manufacturer Register width Transistor count Form 1986 Intel 32-bit 134, pin PGA 32-bit None 16 MHz Data bus Address bus Cache Clock speed

17 KMUTT: S. Srakaew History of Microprocessor The 80386SX Introduced date Manufacturer Register width Transistor count Form 1988 Intel 32-bit 275, bit None 16 MHz Data bus Address bus Cache Clock speed 132-pin PGA

18 KMUTT: S. Srakaew History of Microprocessor The 80486DX Introduced date Manufacturer Register width Transistor count Form 1990 Intel 32-bit 1,200, bit 8K, L1 33 MHz Data bus Address bus Cache Clock speed 168-pin PGA

19 KMUTT: S. Srakaew History of Microprocessor The 80486SX Introduced date Manufacturer Register width Transistor count Form 1991 Intel 32-bit 900,000 8,16,32-bit 32-bit 8K, L1 20 MHz Data bus Address bus Cache Clock speed 168-pin PGA

20 KMUTT: S. Srakaew History of Microprocessor The 80486DX/2-66 Introduced date Manufacturer Register width Transistor count Form 1992 Intel 32-bit 1,200, bit 8K, L1 66 MHz Data bus Address bus Cache Clock speed 168-pin PGA

21 KMUTT: S. Srakaew History of Microprocessor The Pentium Introduced date Manufacturer Register width Transistor count Form 1993 Intel 32-bit 3,100, bit 32-bit 16K, L1 66 MHz Data bus Address bus Cache Clock speed Socket4: 274-pin PGA

22 KMUTT: S. Srakaew History of Microprocessor The Pentium Pro-200 Introduced date Manufacturer Register width Transistor count Form 1995 Intel 32-bit 3,100, bit 32-bit 16K, L1 200 MHz Data bus Address bus Cache Clock speed Socket 8

23 KMUTT: S. Srakaew History of Microprocessor The Pentium MMX-200 Introduced date Manufacturer Register width Transistor count Form 1997 Intel 32-bit 4,400, bit 32-bit 32K, L1 200 MHz Data bus Address bus Cache Clock speed Socket 7

24 KMUTT: S. Srakaew History of Microprocessor The Pentium II 233 Introduced date Manufacturer Register width Transistor count Form 1997 Intel 32-bit 7,500, bit 32-bit 32K, L1; 512K, L2 233 MHz Data bus Address bus Cache Clock speed Slot 1

25 KMUTT: S. Srakaew History of Microprocessor The Celeron 266 Introduced date Manufacturer Register width Transistor count Form 1998 Intel 32-bit 7,500, bit 32-bit 32K, L1 266 MHz Data bus Address bus Cache Clock speed Slot 1

26 KMUTT: S. Srakaew History of Microprocessor The Pentium III 500 Introduced date Manufacturer Register width Transistor count Form 1999 Intel 32-bit 9,500, bit 32-bit 32K, L1; 512K, L2 500 MHz Data bus Address bus Cache Clock speed Slot 1

27 KMUTT: S. Srakaew History of Microprocessor The Celeron 566 Introduced date Manufacturer Register width Transistor count Form 2000 Intel 32-bit 19,000, bit 32-bit 32K, L1; 128K, L2 500 MHz Data bus Address bus Cache Clock speed FC-PGA

28 KMUTT: S. Srakaew History of Microprocessor The Pentium Introduced date Manufacturer Register width Transistor count Form 2000 Intel 32-bit 42,000, bit 32-bit 8K, L1; 256K, L2 1.4 GHz Data bus Address bus Cache Clock speed Socket 423

29 KMUTT: S. Srakaew Performance Trends

30 KMUTT: S. Srakaew Performance Trends

31 KMUTT: S. Srakaew Growth in CPU Transistor Count (From Stallings)

32 KMUTT: S. Srakaew Performance Trends

33 KMUTT: S. Srakaew Performance Trends

34 KMUTT: S. Srakaew Intel Architecture Models

35 KMUTT: S. Srakaew Intel Architecture Models

36 KMUTT: S. Srakaew Intel Architecture Models Intel-based PC: IBM PC compatible

37 KMUTT: S. Srakaew IBM PC compatible Memory map

38 KMUTT: S. Srakaew IBM PC compatible Memory map: Transient program area(TPA)

39 KMUTT: S. Srakaew IBM PC compatible Memory map: System area

40 KMUTT: S. Srakaew IBM PC compatible I/O map

41 KMUTT: S. Srakaew Scales, Units, and Conventions Term K (kilo-) M (mega-) G (giga-) T (tera-) = 1, = 1,048, = 1,073,741, = 1,099,511,627,776 Normal UsageAs a power of 2 Term Usage m (milli-)  (micro-) n (nano-) p (pico-) Units: Bit (b), Byte (B), Nibble, Word (w), Double Word, Long Word, Second (s), Hertz (Hz) Note the differences between usages. You should commit the powers of 2 and 10 to memory.

42 KMUTT: S. Srakaew Two types of architectures Processor (CPU) Memory Unit(s) Physical address bus Data bus Processor external physical bus (or the “memory bus”) Conventional “processor bus” (From Alexandridis)

43 KMUTT: S. Srakaew Two types of architectures Processor (CPU) Data Memory Unit(s) Instruction Memory Unit(s) Harvard architecture external processor buses Data bus (for data) Address bus (for instruction addresses) Data bus (for instructions) Processor external physical bus for data (the “data bus”) Processor external physical bus for instructions (the “instruction bus”) Address bus (for data addresses) (From Alexandridis)

44 KMUTT: S. Srakaew Instruction Set Architecture... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. Amdahl, Blaaw, and Brooks, Organization of Programmable Storage -- Data Types & Data Structures: Encodings & Representations -- Instruction Set & Formats -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions

45 KMUTT: S. Srakaew The Intel bit processor

46 KMUTT: S. Srakaew Intel 8086 CPU

47 KMUTT: S. Srakaew Bus size control Parity control and generation Address drivers Write buffers (4) Data bus transceivers Bus-control request sequencer Burst control Cache control Barrel shifter Register file ALU FPU FP register file Segmentation unit Descriptor registers Limit and attribute PLA Paging unit Translation look-aside buffers Cache unit 8K-byte unified cache Control and protection unit Control ROM Instruction decode Prefetcher 32-byte code queue (2 x 16 bytes) Decoded instructions 32-bit base/ index bus Page attributes 32-bit system address 32-bit write data 32-bit read data 24-bit code stream Microinstruction bus 32-bit displacement bus Bus Interface Unit (BIU) 32-bit linear address bus 32-bit data bus Block diagram of the Intel 486 MMU Control Unit

48 KMUTT: S. Srakaew Intel 486 two arithmetic/logic functional units BIU (Bus Interface Unit) Integer Registers Integrated (Unified) (CACHE) (8 KB) Fetch Buffers & Decoder Integer Unit (ALU) FPU (Rudimentary) MMU * (Segmentation & Paging Unit) or Instructions Data/Operands Data Bus Address Bus BE0#-BE3# FPU Registers MMU * = Memory Management Unit

49 KMUTT: S. Srakaew The Pentium chip

50 KMUTT: S. Srakaew 486 and Pentium

51 KMUTT: S. Srakaew Intel Pentium (superscalar) block diagram BIU (Bus Interface Unit) Data Register File (RF) ICACHE (8KB) Prefetch, Buffers & Decoders (2) Integer Unit (ALU) (V-PIPE) FPU DCACHE (8KB) External Bus Lines Instructions Data/Operands IF ID EXE WB MEM Functional Units Integer Unit (ALU) (U-PIPE) ADD DIVIDE MPY BTB (Branch Target Buffer Integer instr. pipelines: 5 stages Floating-point instr. pipelines: 8 stages

52 KMUTT: S. Srakaew Intel-Based Processor Programmer’s Model Integer general Registers EAX 7 AX AHAL EDXDX DHDL ECXCX CHCL EBXBX BHBL EBPBP ESISI EDIDI ESPSP Status and instruction registers FLAGS/EFLAGS IP (instruction pointer)/EIP 0157 Segment registers CSCode DSData ESExtra SSStack FS GS

53 KMUTT: S. Srakaew Selector CS SS DS ES FS SelectorGS Physical base addressSegment limit 015 Segment registers (Program invisible) Program loads them wit “selectors” (Program visible) special segment registers OS & CPU load them with “selectors” 015 TR LDTR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Other segment attributes from descriptor (32)(20) (12) (Program invisible) Segment base address Access rights Segment limit (size) (12)(32)(20) (Task register) Local descriptor table register Global descriptor table register Interrupt descriptor table register GDTR IDTR Segment descriptor registers (loaded by CPU) (32) S e g m e n t d e s c r i p t o r Selector Intel memory management registers (part 1)

54 KMUTT: S. Srakaew Intel memory management registers (part 2) (Program invisible) POPO Control registers Reserved Page directory base register (PDBR) Page fault linear address Reserved PEPE MPMP EMEM TSTS ETET (Program invisible) R0 R1 R2 R3 R4 R5 R6 R7 SignExponentSignificand Control register Status register Tag word Instruction pointer Data pointer Tag field Debug registers Test registers Linear breakpoint address 0 Linear breakpoint address 1 Linear breakpoint address 2 Linear breakpoint address 3 Intel reserved do not define Breakpoint status Breakpoint control Cache test data Cache test status Cache test control TLB test control TLB test status DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 TR3 TR4 TR5 TR6 TR7 TLB = translation look-aside buffer

55 KMUTT: S. Srakaew Segmentation in the 16-bit Intel 8086 Converting an 8086 logical address into a 20-bit physical address Physical address 19 0 Upper 16 bits of code segment starting address (CS) Upper 16 bits of data segment starting address (DS) Upper 16 bits of stack segment starting address (SS) Upper 16 bits of extra segment starting address (ES) On chip mapping mechanism Special addition Offset in instructions Implicit segment register specification Logical address:

56 KMUTT: S. Srakaew Intel real-mode mapping Code Segment (64 Kbytes) Stack Segment (64 Kbytes) Data Segment (64 Kbytes) Extra Segment (64 Kbytes) Item Logical address 15 0 Offset X X YYYY0 16 (Implicit specification of the data segment register) Logical address space (256 K bytes) Extra Segment (64 Kbytes) Stack Segment (64 Kbytes) Data Segment (64 Kbytes) Code Segment (64 Kbytes) Item : : Physical memory space (1Mbyte) CS DS SS ES Four segment registers On-chip mapping table FFFFF

57 KMUTT: S. Srakaew The BIU section of the 8086 CPU Address/data bus (20 bits) Memory address latch Physical address Logical to physical address conversion (16 bits) 0000 Temp (16 bits) Adder 20 bit segment starting physical address: CS DS SS ES Select (From ALU or A-bus) 16 bit offset (from instruction or gen.purpose register) Bus interface unit (BIU) Physical upper 16 bits of segment starting address Segment register file (Mapping table)

58 KMUTT: S. Srakaew Motorola 68HC11 Microprocessor(Simplified)

59 KMUTT: S. Srakaew Motorola 68HC11 Programmer’s Model 7 Accumulator A 0 7 Accumulator B 0 15 Double accumulator D 0 15 Index register IX 0 15 Index register IY 0 15 Stack pointer 0 15 Program counter 0 S X H I N Z V C A:B D IX IY SP PC CCR Carry Overflow Zero Negative I interrupt mask Half-carry (from bit 3) X interrupt mask Stop disable

60 KMUTT: S. Srakaew Motorola 68HC11A8 Microcontroller pulse accumulator TIMER periodic interrupt COP watchdog PAI OC2 OC3 OC4 OC5 IC1 IC2 IC3 OC1OC1 ROM-8K bytes RAM-256 bytes EEPROM-512 bytes PORT A PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 SPI SS SCK MOSI MISO TxD RxD datadata directiondirection D port D PD5 PD4 PD3 PD2 PD1 PD0 SCI M68HC11 CPU ADDRESS/DATA BUS data direction C PORT B PORT C HANDSHAKE I/O P B 7 P B 6 P P B P P PP BBBBB PP PP P PP P C C CC C CCC STRA STRB parallel I/O single chip A 1 5 A 1 4 A 1 3 A 1 2 A 1 1 A 1 0 A 9 A 8 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 A D 0 R/WAS expanded A/D converter port E PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 V V REFH REFL interrupts RESET XIRQ IRQ oscillator XTAL EXTAL E MODA (LIR) MODB (V STB ) mode select power V V DD SS

61 KMUTT: S. Srakaew Motorola Instr. address unit Data address unit Data section Data buffer MMU and ATC Address pads Data cache Instr. cache Microsequencer and control Stage 3 Stage 2 Stage 1 Instruction pipe Logical instr. addresses Hit Logical data addresses Address bus 32 Data bus

62 KMUTT: S. Srakaew Motorola Floating point unit Integer unit Data address unit Instr. address unit Data MMU and ATC Instr. MMU and ATC Instr. cache Buffers Data cache Instr. data bus Operand data bus Physical data address Physical instr. address Address /data bus 32 Hit

63 KMUTT: S. Srakaew The Stored Program Concept It is the basic operating principle for every computer. It is so common that it is taken for granted. Without it, every instruction would have to be initiated manually. The stored program concept says that the program is stored with data in the computer’s memory. The computer is able to manipulate it as data—for example, to load it from disk, move it in memory, and store it back on disk.

64 KMUTT: S. Srakaew Machine, Processor, and Memory State The Machine State: contents of all registers in system, accessible to programmer or not The Processor State: registers internal to the CPU The Memory State: contents of registers in the memory system “State” is used in the formal finite state machine sense Maintaining or restoring the machine and processor state is important to many operations, especially procedure calls and interrupts

65 KMUTT: S. Srakaew Program Execution See animation

66 KMUTT: S. Srakaew The Computer Architect’s View Architect is concerned with design & performance Designs the ISA for optimum programming utility and optimum performance of implementation Designs the hardware for best implementation of the instructions Uses performance measurement tools, such as benchmark programs, to see that goals are met Balances performance of building blocks such as CPU, memory, I/O devices, and interconnections Meets performance goals at lowest cost

67 KMUTT: S. Srakaew Background - Definitions Computer = Computer system = Microprocessor- based system Bus-based configurations Instruction cycle phases: êInstruction Fetch & Opcode Decode êPossible operand read êInstruction execute

68 KMUTT: S. Srakaew Instruction cycle Bus cycles Input clock cycles Instruction Cycle B1B2B3 C1C2C3C4C1C2C3C4C1C2C3C4

69 KMUTT: S. Srakaew Background - Definitions Access to a slave port done with bus cycles Total number of bus cycles per instr. depends on: êwhether the instr. has been prefetched êwidth of instruction êneed to fetch an operand êwidth of external data bus ênumber of steps required to execute instruction clocks: system clock, processor clock clock cycle times:  system clock cycle time = C s  processor clock cycle time = C p

70 KMUTT: S. Srakaew 8086 Timing Diagram

71 KMUTT: S. Srakaew Buses Interconnections are very important to computer Most connections are shared A bus may be time-shared (multiplexed) connection A bus provides a data path and control Buses may be serial, parallel, or a combination  Serial buses transmit one bit at a time  Parallel buses transmit many bits simultaneously on many wires “Address bus”, “data bus”, “control bus”

72 KMUTT: S. Srakaew Data Storage Modules RAM Special- Purpose Modules Caches, MMUs I/O Interface Cards Program Storage Modules ROM Processor CPU Keyboard Display Cassette Floppy Disk ADC, DAC, Modem, etc. BUS (Address, Data, Control Signals) Conventional bus-based computer system (From Alexandridis)

73 KMUTT: S. Srakaew Input/system clock L2 Cache (& cache controller) Main DRAM Memory (& Controller) CPU BUS I/O SUBSYSTEM DMA controller Graphics controller etc. KEYBOARD HARD DRIVE CD ROM NETWORK INTERFACE GRAPHICS SENSORS ACTUATORS Processor Module Level 1 bus : CPU or processor bus A small, one-level-bus, computer system Hierarchy of buses (cont’d) PROCESSOR (CPU) (e.g., X MHz) (From Alexandridis)

74 KMUTT: S. Srakaew A single-board computer system with a local bus Hierarchy of buses (cont’d) Input/system clock L2 Cache (& cache controller) Main DRAM Memory (& Controller) Processor Module Level 1 bus : CPU or Processor Bus PROCESSOR (CPU) Local Bus Bridge (“chip-set”) Processor/Cache/Memory Subsystem Level 2 bus : Local Bus (PCI, VLBus, Sbus) I/O Expansion Boards IDE or SCSI cont’rs LAN cont’rs Video RAM (e.g., X MHz) (e.g., X/2 MHz) Local Bus Devices (Display system, CD ROM, hard drive, etc.) (From Alexandridis)

75 KMUTT: S. Srakaew CLOCK GENERATOR PROCESSOR (CPU) CO- PROCESSOR ADDRESS LATCHES ADDRESS DECODER DATA TRANSCEIVERS BUS CONTROLLER BYTE ENABLE CIRCUIT BURST LOGIC INTERRUPT CONTROL LOGIC BUS ARBITER “BYTE-ENABLES INTERRUPT REQUEST SIGNALS ARBITRATION LINES DATA BUS COMMANDS BUFFERED ADDRESS BUS ALE or AS C Interface components on the processor side Data Status/co ntrol CHIP SELECTS

76 KMUTT: S. Srakaew Input/system clock L2 Cache (& cache controller) Main DRAM Memory (& Controller) CPU BUS I/O SUBSYSTEM DMA controller Graphics controller etc. KEYBOARD HARD DRIVE CD ROM NETWORK INTERFACE GRAPHICS SENSORS ACTUATORS Processor Module Level 1 bus: CPU or processor bus A small, one-level-bus, computer system Hierarchy of buses (cont’d) PROCESSOR (CPU) (e.g., X MHz)

77 KMUTT: S. Srakaew Hierarchy of buses (cont’d)

78 KMUTT: S. Srakaew A single-board computer system with a local bus Hierarchy of buses (cont’d) System clock L2 Cache (& cache controller) Main DRAM Memory (& Controller) Processor Module Level 1 bus: CPU or Processor Bus PROCESSOR (CPU) Local Bus Bridge (“chip-set”) Processor/Cache/Memory Subsystem Level 2 bus: Local Bus (PCI, VLBus, Sbus) I/O Expansion Boards IDE or SCSI cont’rs LAN cont’rs Video RAM (e.g., X MHz) (e.g., X/2 MHz) Local Bus Devices (Display system, CD ROM, hard drive, etc.)

79 KMUTT: S. Srakaew Hierarchy of buses (cont’d)

80 KMUTT: S. Srakaew Hierarchy of buses (cont’d)

81 KMUTT: S. Srakaew Hierarchy of buses (cont’d)

82 KMUTT: S. Srakaew A larger, multiboard, computer system Hierarchy of buses (cont’d) System clock L2 Cache Main DRAM Memory Processor Module Level 1 bus: CPU or Processor Bus (CPU) Local Bus Bridge (“chip-set”) Processor/Cache/Memory Subsystem Level 2 bus: Local Bus (PCI, VLBus, Sbus) (e.g., X MHz) (e.g., X/2 MHz) Graphics Cont’lr AGP * I/O Expans’n Boards Local Bus Devices Level 3 bus: System or Expansion Bus (VMEbus, Futurebus, Multibus)(e.g., X/4 MHz) Processor/Master Board Shared System Memory Boards Shared System Memory Boards System Bus Bridge I/O Bus Interface Boards Level 4 I/O Bus (GPIB, LAN) * AGP = Accelerated Graphics Port

83 KMUTT: S. Srakaew Processor board #1 Global/System bus Controllers and adapters Memory Interface Main Memory Global/system memory Global/System I/O System I/O devices Multiprocessor computer systems PCI: Peripheral Component Interconnect SCSI: Small Computer System Interface GPIB: General-Purpose Instrument Bus LAN: Local Area Network Bus arbiter System bus interface Local I/O Local Memory Processor (CPU) Bus arbiter System bus interface Local I/O Local Memory Processor (CPU) Bus arbiter System bus interface Local I/O Local Memory Processor (CPU) Processor board #2Processor board #N

84 KMUTT: S. Srakaew Summary All computers consist of five components  Processor: (1) datapath and (2) control section  (3) Memory  (4) Input devices and (5) Output devices Not all “memory” are created equally  Cache: fast (expensive) memory is placed closer to the processor  Main memory: less expensive memory--we can have more Input and output (I/O) devices have the messiest organization: êWide range of speed: graphics vs.. keyboard êWide range of requirements: speed, standard, cost... etc. êLeast amount of research (so far) Memory and I/O ports will collectively be referred to as “slave ports”


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