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FPGA Intra-cluster Routing Crossbar Design Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223

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Generating Highly Routable Sparse Crossbars for PLDs Guy Lemieux, Paul Leventis, David Lewis International Symposium on FPGAs, 2000

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Basic Notation

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Fully Populated Crossbar Full capacity – can connect as many signals as the number of outputs Flexibility – Can connect any input to any output

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Full-capacity Minimal Crossbars Full capacity Reduced Flexibility: you lose the ability to connect any input to any output p = m(m – n + 1) switches

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Full-capacity Minimal Crossbars … Area savings is minimal if n >> m

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Perfect and Sparse Crossbars Perfect crossbars – Can disjointly route any m-sized subset of the n inputs to the m outputs – Both full and full-capacity minimal crossbars are perfect Sparse crossbars – Has p < m(m – n + 1) switches – Cannot be perfect

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Bipartite Graph Representation I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 O1O1 O2O2 O3O3 O4O4 I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 O1O1 O2O2 O3O3 O4O4

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Evaluation Challenge How “routable” is a given crossbar? – Build an FPGA, map 20+ applications, observe results Slow, highly subject to the application mix – Monte Carlo Test Generate random test vectors Route each test vector on the crossbar (network flow) Report number of successes as a percentage A highly routable sparse crossbar has a >= 95% success rate

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Hall’s Theorm Given a bipartite graph G = (V, E) – X, Y are the bipartite independent sets of G G has a matching of X onto Y if and only if N(v) is the set of neighbors of vertex v N(S) is the set of neighbors of all vertices in S Leverage Hall’s Theorem to generate routable sparse crossbars!

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Practical Issues Cannot enumerate all subsets of m inputs N(x) should be approximately equal for all input vertices x in X – Otherwise, any subset containing a large number of low-degree vertices is unlikely to be routable N(y) should be approximately equal for all output vertices y in Y – Symmetric argument

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Hamming Distance and Coding Theory Represent N(v) as a bitvector bv – bv[i] = 1 if v fans out to O i Hamming Distance – d(bv 1, bv 2 ) Strategy – Maximize d(bv i, bv j ) for every pair of distinct vertices v i and v j

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Switch Placement Optimizer Start with initial switch placement Generate random swap of switch positions – Accept the swap if there is an improvement – Otherwise, reject the swap Stop after a fixed number of swap candidates (e.g., 10K) fails to find an improvement Objective is to minimize:

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Example Identical Hamming costs before and after the swap Before: cannot route {1, 2, 3} After: reduces Hamming costs

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168x24 Crossbar, 10K Test Vectors

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Altera Flex 8000 HP Plasma Hextant

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# Switches vs. Routability

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Using Sparse Crossbars within LUT Clusters Guy Lemieux, David Lewis International Symposium on FPGAs, 2001

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Five Questions 1.Will depopulation save area, require greater routing area, or create unroutable architectures? 2.Will depopulation reduce or increase routing delays? 3.What amount of depopulation is reasonable? 4.How much area or delay reduction can be attained, if any? 5.What are the other effects of depopulating the cluster?

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Architecture and Parameters

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Results

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Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy Wenyi Feng and Sinan Kaptanoglu ACM Transactions on Reconfigurable Technology and Systems (TRETS), 1(1): article #6, March, 2008 Note: Paper is from Actel (now Microsemi)

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Count Configurations (Details Omitted) 784 Configurations 312 Configurations256 Configurations

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Routing Requirement Vector (RRV) An ordered list of N subsets containing K distinct signals The i th subset is K distinct signals to route to the i th K-LUT Total number of RRVs for the crossbar: M inputs KN outputs

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Entropy of an Intra-cluster Routing Crossbar H = lg(# routable RRVs) – Accounts for equivalence of LUT inputs Why Entropy? – # routable RRVs is huge – Minimum number of configuration bits to program the crossbar – Inversely correlated with usage of global routing muxes (details omitted) If we reduce the routability of the crossbar, we will end up programming more global routing muxes to compensate for the entropy loss

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Conceptual Idea intra-cluster crossbar global routing

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Theorem Let P and L be the number of muxes and switches in a crossbar – The entropy is at most Plg(L/P) – The entropy per switch is at most log(L/P) / (L/P) – These bounds are achieved only when each mux has size L/P and each configuration realizes a unique RRV Proof omitted because I DO NOT HATE YOU!

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What are we doing here? Lemieux and Lewis – Routability: Monte Carlo simulations – Area: Count switches Feng and Kaptanoglu – Routability: Crossbar entropy – Area: Entropy per switch – Caveat: Focus only on crossbars where we can count routable, non-redundant RRVs!

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Type-1 Crossbar 1-level – L2 muxes are driven directly by crossbar input signals – #routable RRVs depends on L2 crossbar topology Not area-efficient due to big L2 muxes Xilinx Virtex-style

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Type-2 Crossbar 2-level – L1 is sparsely populated – L2 is fully populated Fully populated L2 reduces area efficiency VPR – F c,in determines L1 population density

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Type-3 Crossbar 2-level, Partitioned – L1 partition P i only drives L2 partition O i – From input m to LUT input n, all paths go through muxes in P i and O i exclusively – #Routable RRVs is the product of #Routable RRVs for each disjoint sub-crossbar

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Proposed Type-3 Crossbar and Generation Algorithm Each sub-crossbar is Type-2 Can count #routable RRVs (Details omitted)

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Entropy vs. # Switches

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Entropy vs. Global Routing Mux Usage

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The Bottom Line… Who cares… – Theoretical properties are cute – Actel/Microsemi did not use these crossbars in their FPGAs Practical observation… – The cheaper you make the intra-cluster routing crossbar, the more expensive the global routing…

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A 65nm flash-based FPGA fabric optimized for low cost and power Jonathan W. Greene, et al. International Symposium on FPGAs, 2011 Note: Paper is from Microsemi (Feng and Kaptanoglu are co-authors)

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Corporate Secrets Divulged They used a Clos Network – Three parameters: m, n, r

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Clos Network Properties Used when the physical circuit switching needs to exceed the capacity of the largest feasible single crossbar Much cheaper than a fully populated nxn crossbar

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Strict-sense Nonblocking Clos Network (m > 2n – 1) An unused input on an ingress switch can always be connected to an unused output on an egress switch, without reconfiguration!

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Rearrangeably Nonblocking Clos Network (m > n) An unused input on an ingress switch can always be connected to an unused output on an egress switch, but reconfiguration may be necessary!

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Recursive Clos Network Design Scalable to any ODD number of stages – Replace center crossbar with a 3-stage Clos Network

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FPGA Technology Mapping Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.

FPGA Technology Mapping Dr. Philip Brisk Department of Computer Science and Engineering University of California, Riverside CS 223.

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